2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 #ifndef __REGS_AP_CLK_H__
12 #define __REGS_AP_CLK_H__
16 /* registers definitions for controller REGS_AP_CLK */
17 #define REG_AP_CLK_AP_AHB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0020)
18 #define REG_AP_CLK_AP_APB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0024)
19 #define REG_AP_CLK_GSP_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0028)
20 #define REG_AP_CLK_DISPC0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x002c)
21 #define REG_AP_CLK_DISPC0_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0030)
22 #define REG_AP_CLK_DISPC0_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0034)
23 #define REG_AP_CLK_DISPC1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0038)
24 #define REG_AP_CLK_DISPC1_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x003c)
25 #define REG_AP_CLK_DISPC1_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0040)
26 #define REG_AP_CLK_NFC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0044)
27 #define REG_AP_CLK_SDIO0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0048)
28 #define REG_AP_CLK_SDIO1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x004c)
29 #define REG_AP_CLK_SDIO2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0050)
30 #define REG_AP_CLK_EMMC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0054)
31 #define REG_AP_CLK_GPS_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0058)
32 #define REG_AP_CLK_GPS_TCXO_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x005c)
33 #define REG_AP_CLK_USB_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0060)
34 #define REG_AP_CLK_UART0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0064)
35 #define REG_AP_CLK_UART1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0068)
36 #define REG_AP_CLK_UART2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x006c)
37 #define REG_AP_CLK_UART3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0070)
38 #define REG_AP_CLK_UART4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0074)
39 #define REG_AP_CLK_I2C0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0078)
40 #define REG_AP_CLK_I2C1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x007c)
41 #define REG_AP_CLK_I2C2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0080)
42 #define REG_AP_CLK_I2C3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0084)
43 #define REG_AP_CLK_I2C4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0088)
44 #define REG_AP_CLK_SPI0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x008c)
45 #define REG_AP_CLK_SPI1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0090)
46 #define REG_AP_CLK_SPI2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0094)
47 #define REG_AP_CLK_IIS0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0098)
48 #define REG_AP_CLK_IIS1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x009c)
49 #define REG_AP_CLK_IIS2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a0)
50 #define REG_AP_CLK_IIS3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a4)
52 /* vars definitions for controller REGS_AP_CLK */
54 /* vars definitions for REG_AP_CLK_AP_AHB_CFG */
55 #define AP_AHB_CLK_SEL_SHIFT (0)
56 #define AP_AHB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT)
58 #define AP_APB_CLK_SEL_SHIFT (0)
59 #define AP_APB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT)
61 #endif //__REGS_AP_CLK_H__