1 /******************************************************************************
2 ** File Name: analog_reg_v3.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 03/03/2010 Tim.Luo Create. *
13 ** 05/07/2010 Mingwei.zhang Modify it for SC8800G. *
14 ******************************************************************************/
16 #ifndef _ANALOG_REG_V3_H_
17 #define _ANALOG_REG_V3_H_
21 /*----------------------------------------------------------------------------*
23 **-------------------------------------------------------------------------- */
25 /**---------------------------------------------------------------------------*
27 **---------------------------------------------------------------------------*/
32 /**----------------------------------------------------------------------------*
34 **----------------------------------------------------------------------------*/
36 //Analog die register define
41 #define ANA_APB_MOD_EN (ANA_REGS_GLB_PHYS + 0x00)
42 #define ANA_APB_CLK_EN (ANA_REGS_GLB_PHYS + 0x04)
43 #define ANA_APB_RTC_CLK_EN (ANA_REGS_GLB_PHYS + 0x08)
44 #define ANA_APB_ARM_RST (ANA_REGS_GLB_PHYS + 0x0C)
45 #define ANA_APB_DCDCPD_RTC_SET (ANA_REGS_GLB_PHYS + 0x10)
46 #define ANA_APB_DCDCPD_RTC_CLR (ANA_REGS_GLB_PHYS + 0x14)
47 #define ANA_APB_RTC_CTL (ANA_REGS_GLB_PHYS + 0x18)
48 #define ANA_APB_LDO_PD_CTL (ANA_REGS_GLB_PHYS + 0x1C)
49 #define ANA_APB_LDO_VC_CTL0 (ANA_REGS_GLB_PHYS + 0x20)
50 #define ANA_APB_LDO_VC_CTL1 (ANA_REGS_GLB_PHYS + 0x24)
51 #define ANA_APB_LDO_VC_CTL2 (ANA_REGS_GLB_PHYS + 0x28)
52 #define ANA_APB_LDO_CAL_CTL0 (ANA_REGS_GLB_PHYS + 0x2C)
53 #define ANA_APB_LDO_CAL_CTL1 (ANA_REGS_GLB_PHYS + 0x30)
54 #define ANA_APB_LDO_CAL_CTL2 (ANA_REGS_GLB_PHYS + 0x34)
55 #define ANA_APB_LDO_CAL_CTL3 (ANA_REGS_GLB_PHYS + 0x38)
56 #define ANA_APB_LDO_CAL_CTL4 (ANA_REGS_GLB_PHYS + 0x3C)
57 #define ANA_APB_LDO_CAL_CTL5 (ANA_REGS_GLB_PHYS + 0x40)
58 #define ANA_APB_LDO_CAL_CTL6 (ANA_REGS_GLB_PHYS + 0x44)
59 #define ANA_APB_AUXAD_CTL (ANA_REGS_GLB_PHYS + 0x48)
60 #define ANA_APB_DCDC_CTL0 (ANA_REGS_GLB_PHYS + 0x4C)
61 #define ANA_APB_DCDC_CTL1 (ANA_REGS_GLB_PHYS + 0x50)
62 #define ANA_APB_DCDC_CTL2 (ANA_REGS_GLB_PHYS + 0x54)
63 #define ANA_APB_DCDC_CTL3 (ANA_REGS_GLB_PHYS + 0x58)
64 #define ANA_APB_DCDC_CTL4 (ANA_REGS_GLB_PHYS + 0x5C)
65 #define ANA_APB_DCDC_CTL5 (ANA_REGS_GLB_PHYS + 0x60)
66 #define ANA_APB_DCDC_CTL6 (ANA_REGS_GLB_PHYS + 0x64)
67 #define ANA_APB_DDR2_CTL (ANA_REGS_GLB_PHYS + 0x68)
68 #define ANA_APB_SLPWAIT_DCARM (ANA_REGS_GLB_PHYS + 0x6C)
69 #define ANA_APB_LDO_XTL_CTL (ANA_REGS_GLB_PHYS + 0x70)
70 #define ANA_APB_LDO_SLP_CTL0 (ANA_REGS_GLB_PHYS + 0x74)
71 #define ANA_APB_LDO_SLP_CTL1 (ANA_REGS_GLB_PHYS + 0x78)
72 #define ANA_APB_LDO_SLP_CTL2 (ANA_REGS_GLB_PHYS + 0x7C)
73 #define ANA_APB_LDO_SLP_CTL3 (ANA_REGS_GLB_PHYS + 0x80)
74 #define ANA_APB_LDO_SLP_CTL4 (ANA_REGS_GLB_PHYS + 0x84)
75 #define ANA_APB_DCDC_SLP_CTL (ANA_REGS_GLB_PHYS + 0x88)
76 #define ANA_APB_XTL_WAIT_CTL (ANA_REGS_GLB_PHYS + 0x8C)
77 #define ANA_APB_FLASH_CTL (ANA_REGS_GLB_PHYS + 0x90)
78 #define ANA_APB_WHTLED_CTL0 (ANA_REGS_GLB_PHYS + 0x94)
79 #define ANA_APB_WHTLED_CTL1 (ANA_REGS_GLB_PHYS + 0x98)
80 #define ANA_APB_WHTLED_CTL2 (ANA_REGS_GLB_PHYS + 0x9C)
81 #define ANA_APB_ANA_DRV_CTL (ANA_REGS_GLB_PHYS + 0xA0)
82 #define ANA_APB_VIBR_CTL0 (ANA_REGS_GLB_PHYS + 0xA4)
83 #define ANA_APB_VIBR_CTL1 (ANA_REGS_GLB_PHYS + 0xA8)
84 #define ANA_APB_VIBR_CTL2 (ANA_REGS_GLB_PHYS + 0xAC)
85 #define ANA_APB_VIBR_PROT_VAL (ANA_REGS_GLB_PHYS + 0xB0)
86 #define ANA_APB_AUDIO_CTL (ANA_REGS_GLB_PHYS + 0xB4)
87 #define ANA_APB_CHGR_CTL0 (ANA_REGS_GLB_PHYS + 0xB8)
88 #define ANA_APB_CHGR_CTL1 (ANA_REGS_GLB_PHYS + 0xBC)
89 #define ANA_APB_CHGR_CTL2 (ANA_REGS_GLB_PHYS + 0xC0)
90 #define ANA_APB_CHGR_STS (ANA_REGS_GLB_PHYS + 0xC4)
91 #define ANA_APB_MIXED_CTL (ANA_REGS_GLB_PHYS + 0xC8)
92 #define ANA_APB_PWR_XTL_EN0 (ANA_REGS_GLB_PHYS + 0xCC)
93 #define ANA_APB_PWR_XTL_EN1 (ANA_REGS_GLB_PHYS + 0xD0)
94 #define ANA_APB_PWR_XTL_EN2 (ANA_REGS_GLB_PHYS + 0xD4)
95 #define ANA_APB_PWR_XTL_EN3 (ANA_REGS_GLB_PHYS + 0xD8)
96 #define ANA_APB_PWR_XTL_EN4 (ANA_REGS_GLB_PHYS + 0xDC)
97 #define ANA_APB_PWR_XTL_EN5 (ANA_REGS_GLB_PHYS + 0xE0)
98 #define ANA_APB_ANA_STS (ANA_REGS_GLB_PHYS + 0xE4)
99 #define ANA_APB_POR_RST_MONTR (ANA_REGS_GLB_PHYS + 0xE8)
100 #define ANA_APB_WDG_RST_MONTR (ANA_REGS_GLB_PHYS + 0xEC)
101 #define ANA_APB_POR_PIN_RST_MONTR (ANA_REGS_GLB_PHYS + 0xF0)
102 #define ANA_APB_POR_SRC_FLAG (ANA_REGS_GLB_PHYS + 0xF4)
103 #define ANA_APB_POR_7S_CTL (ANA_REGS_GLB_PHYS + 0xF8)
104 #define ANA_APB_INT_DBG (ANA_REGS_GLB_PHYS + 0xFC)
105 #define ANA_APB_GPI_DBG (ANA_REGS_GLB_PHYS + 0x100)
106 #define ANA_APB_HWRST_RTC (ANA_REGS_GLB_PHYS + 0x104)
107 #define ANA_APB_CHIP_ID_LOW (ANA_REGS_GLB_PHYS + 0x108)
108 #define ANA_APB_CHIP_ID_HIG (ANA_REGS_GLB_PHYS + 0x10C)
109 #define ANA_APB_ARM_MF_REG (ANA_REGS_GLB_PHYS + 0x110)
110 #define ANA_APB_AFUSE_CTL (ANA_REGS_GLB_PHYS + 0x114)
111 #define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x118)
112 #define ANA_APB_AFUSE_OUT1 (ANA_REGS_GLB_PHYS + 0x11C)
113 #define ANA_APB_AFUSE_OUT2 (ANA_REGS_GLB_PHYS + 0x120)
114 #define ANA_APB_AFUSE_OUT3 (ANA_REGS_GLB_PHYS + 0x124)
115 #define ANA_APB_ARCH_EN (ANA_REGS_GLB_PHYS + 0x128)
116 #define ANA_APB_MCU_WR_PROT_VAL (ANA_REGS_GLB_PHYS + 0x12C)
117 #define ANA_APB_DCDC_CORE (ANA_REGS_GLB_PHYS + 0x160)
118 #define ANA_APB_DCDC_ARM (ANA_REGS_GLB_PHYS + 0x164)
119 #define ANA_APB_DCDC_MEM (ANA_REGS_GLB_PHYS + 0x168)
120 #define ANA_APB_DCDC_GEN (ANA_REGS_GLB_PHYS + 0x16C)
121 #define ANA_APB_DCDC_WRF (ANA_REGS_GLB_PHYS + 0x170)
122 #define ANA_APB_DCDC_WPA (ANA_REGS_GLB_PHYS + 0x174)
123 #define ANA_APB_DCDC_WPA_DCM (ANA_REGS_GLB_PHYS + 0x17C)
126 #define CHGR_PD_STS_BIT BIT_15
127 #define CHGR_PD_CLR_BIT BIT_1
128 #define CHGR_PD_SET_BIT BIT_0
131 #define CHGR_SW_POINT_SHIFT 0
132 #define CHGR_SW_POINT_MSK (0x1F << CHGR_SW_POINT_SHIFT)
133 #define CHGR_CHG_CUR_SHIFT 10
134 #define CHGR_CHG_CUR_MSK (0x1F << CHGR_CHG_CUR_SHIFT)
137 #define CHGR_RECHG_BIT BIT_0
138 #define CHGR_CC_EN_BIT BIT_1
144 the VIBRATOR_CTL0 register bit
146 #define VIBR_STABLE_V_SHIFT 12
147 #define VIBR_STABLE_V_MSK (0x0F << VIBR_STABLE_V_SHIFT)
148 #define VIBR_INIT_V_SHIFT 8
149 #define VIBR_INIT_V_MSK (0x0F << VIBR_INIT_V_SHIFT)
150 #define VIBR_V_BP_SHIFT 4
151 #define VIBR_V_BP_MSK (0x0F << VIBR_V_BP_SHIFT)
152 #define VIBR_PD_RST BIT_3
153 #define VIBR_PD_SET BIT_2
154 #define VIBR_BP_EN BIT_1
155 #define VIBR_RTC_EN BIT_0
163 #endif //_ANALOG_REG_V3_H_