2 * Copyright (C) 2014 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
19 #ifndef __REGS_EFUSE_H__
20 #define __REGS_EFUSE_H__
24 /* registers definitions for controller REGS_EFUSE */
25 #define REG_EFUSE_DATA_RD SCI_ADDR(REGS_EFUSE_BASE, 0x0000)
26 #define REG_EFUSE_DATA_WR SCI_ADDR(REGS_EFUSE_BASE, 0x0004)
27 #define REG_EFUSE_READ_WRITE_INDEX SCI_ADDR(REGS_EFUSE_BASE, 0x0008)
28 #define REG_EFUSE_MODE_CTRL SCI_ADDR(REGS_EFUSE_BASE, 0x000c)
29 #define REG_EFUSE_CFG0 SCI_ADDR(REGS_EFUSE_BASE, 0x0010)
30 #define REG_EFUSE_CFG1 SCI_ADDR(REGS_EFUSE_BASE, 0x0014)
31 #define REG_EFUSE_STATUS SCI_ADDR(REGS_EFUSE_BASE, 0x0020)
32 #define REG_EFUSE_BLK_FLAG0 SCI_ADDR(REGS_EFUSE_BASE, 0x0024)
33 #define REG_EFUSE_BLK_FLAG1 SCI_ADDR(REGS_EFUSE_BASE, 0x0028)
34 #define REG_EFUSE_BLK_FLAG0_CLR SCI_ADDR(REGS_EFUSE_BASE, 0x0030)
35 #define REG_EFUSE_BLK_FLAG1_CLR SCI_ADDR(REGS_EFUSE_BASE, 0x0034)
36 #define REG_EFUSE_MAGIC_NUMBER SCI_ADDR(REGS_EFUSE_BASE, 0x0040)
37 #define REG_EFUSE_STROBE_LOW_WIDTH SCI_ADDR(REGS_EFUSE_BASE, 0x0044)
38 #define REG_EFUSE_EFUSE_DEB_CTRL SCI_ADDR(REGS_EFUSE_BASE, 0x0048)
40 /* bits definitions for register REG_EFUSE_READ_WRITE_INDEX */
41 #define BITS_READ_WRITE_INDEX(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
43 #define SHFT_READ_WRITE_INDEX ( 0 )
44 #define MASK_READ_WRITE_INDEX ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4) )
46 /* bits definitions for register REG_EFUSE_MODE_CTRL */
47 /* Write 1 to this bit start A_PGM mode(array PGM mode).
48 * This bit is self-clear, read this bit will always get 0.
50 #define BIT_PG_START ( BIT(0) )
51 #define BIT_RD_START ( BIT(1) )
52 #define BIT_STANDBY_START ( BIT(2) )
54 /* bits definitions for register REG_EFUSE_CFG0 */
55 #define BITS_TPGM_TIME_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
56 #define BITS_EFS_TYPE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
57 #define BIT_EFS_VDDQ_K1_ON ( BIT(28) )
58 #define BIT_EFS_VDDQ_K2_ON ( BIT(29) )
59 /* Set this bit will open 0.9v static power supply for efuse memory,
60 * before any operation towards to efuse memory this bit have to set to 1.
61 * Once this bit is cleared, the efuse will go to power down mode.
63 #define BIT_EFS_VDD_ON ( BIT(30) )
64 /* ONly set this bit can SW write register field of TPGM_TIME_CNT and start PGM mode,
65 * for protect sw unexpectedly programmed efuse memory.
67 #define BIT_PGM_EN ( BIT(31) )
69 /* bits definitions for register REG_EFUSE_CFG1 */
70 #define BIT_BLK0_AUTO_TEST_EN ( BIT(0) )
72 /* bits definitions for register REG_EFUSE_STATUS */
73 #define BIT_PGM_BUSY ( BIT(0) )
74 #define BIT_READ_BUSY ( BIT(1) )
75 #define BIT_STANDBY_BUSY ( BIT(2) )
77 /* bits definitions for register REG_EFUSE_BLK_FLAG0 */
78 #define BIT_BLK0_PROT_FLAG ( BIT(0) )
80 /* bits definitions for register REG_EFUSE_BLK_FLAG1 */
81 #define BIT_BLK0_ERR_FLAG ( BIT(0) )
83 /* bits definitions for register REG_EFUSE_BLK_FLAG0_CLR */
84 #define BIT_BLK0_PROT_FLAG_CLR ( BIT(0) )
86 /* bits definitions for register REG_EFUSE_BLK_FLAG1_CLR */
87 #define BIT_BLK0_ERR_FLAG_CLR ( BIT(0) )
89 /* bits definitions for register REG_EFUSE_MAGIC_NUMBER */
90 /* Magic number, only when this field is 0x8810, the efuse programming command can be handle.
91 * So, if SW want to program efuse memory, except open clocks and power, the follow conditions must be met:
93 * 2. EFUSE_MAGIC_NUMBER = 0x8810
95 #define BITS_MAGIC_NUMBER(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
96 #define BITS_DEB_MAGIC_NUMBER(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
98 /* bits definitions for register REG_EFUSE_STROBE_LOW_WIDTH */
99 #define BITS_EFUSE_STROBE_LOW_WIDTH(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
100 #define BITS_CLK_EFS_DIV(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
102 #define SHFT_CLK_EFS_DIV ( 16 )
103 #define MASK_CLK_EFS_DIV ( BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23) )
105 /* bits definitions for register REG_EFUSE_EFUSE_DEB_CTRL */
106 #define BIT_MARGIN_MODE_EN ( BIT(1) )
107 #define BIT_DOUBLE_BIT_DISABLE ( BIT(0) )
109 /* vars definitions for controller REGS_EFUSE */
110 #define EFUSE_MAGIC_NUMBER ( 0x8810 )
111 #define EFUSE_DEB_MAGIC_NUMBER ( 0x6868 )
112 #define BIT_EFUSE_PROT_LOCK ( BIT(31) )
114 #endif /* __REGS_EFUSE_H__ */