1 /******************************************************************************
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2 ** File Name: SPI_Test.h *
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3 ** Author: Zhonghe.Huang *
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4 ** DATE: 18/06/2010 *
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5 ** Copyright: 2002 Spreatrum, Incoporated. All Rights Reserved. *
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6 ** Description: This file define structure and varialbes for SPI_Test.c *
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7 ******************************************************************************
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9 ******************************************************************************
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11 ** ------------------------------------------------------------------------- *
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12 ** DATE NAME DESCRIPTION *
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13 ** 18/06/2010 Zhonghe.Huang Create. *
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14 ******************************************************************************/
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19 /**---------------------------------------------------------------------------*
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21 **---------------------------------------------------------------------------*/
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23 /**---------------------------------------------------------------------------*
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25 **---------------------------------------------------------------------------*/
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31 /**---------------------------------------------------------------------------*
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32 ** Macro Definition *
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33 **---------------------------------------------------------------------------*/
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38 #define SPI_USED_ID SPI2_ID
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40 #define CHN_SPI_INT 9
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41 #define DMA_SPI_TX 0x13
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43 #define SPI_TX_FIFO_DEPTH 16
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44 #define SPI_RX_FIFO_DEPTH 16
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45 #define SPI_INT_DIS_ALL 0
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46 #define SPI_RX_FULL_INT_EN BIT_6
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47 #define SPI_RX_FULL_INT_STS BIT_6
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48 #define SPI_RX_FULL_INT_CLR BIT_0
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49 #define SPI_RX_FIFO_REAL_EMPTY BIT_5
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50 #define SPI_S8_MODE_EN BIT_7
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51 #define SPI_CD_SEL 0x2 //cs1 is sel as cd signal
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54 Define the SPI interface mode for LCM
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56 #define SPIMODE_DISABLE 0
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57 #define SPIMODE_3WIRE_9BIT_SDA 1 // 3 wire 9 bit, cd bit, SDI/SDO share one IO
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58 #define SPIMODE_3WIRE_9BIT_SDIO 2 // 3 wire 9 bit, cd bit, SDI, SDO
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59 #define SPIMODE_4WIRE_8BIT_SDA 3 // 4 wire 8 bit, cd pin, SDI/SDO share one IO
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60 #define SPIMODE_4WIRE_8BIT_SDIO 4 // 4 wire 8 bit, cd pin, SDI, SDO
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63 Define the clk src for SPI mode
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65 #define SPICLK_SEL_192M 0
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66 #define SPICLK_SEL_154M 1
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67 #define SPICLK_SEL_96M 2
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68 #define SPICLK_SEL_26M 3
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71 SPI CS sel in master mode
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73 #define SPI_SEL_CS0 0x0E //2'B1110
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74 #define SPI_SEL_CS1 0x0D //2'B1101
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75 #define SPI_SEL_CS2 0x0B //2'B1011
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76 #define SPI_SEL_CS3 0x07 //2'B0111
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78 /**---------------------------------------------------------------------------*
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79 ** Structure Definition *
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80 **---------------------------------------------------------------------------*/
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126 }SPI_OPERATE_MODE_E;
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140 typedef struct _init_param
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144 MSB_LSB_SEL msb_lsb_sel;
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145 TRANCIEVE_MODE tx_rx_mode;
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146 SWT_MODE switch_mode;
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147 SPI_OPERATE_MODE_E op_mode;
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152 uint8 tx_empty_watermark;
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153 uint8 tx_full_watermark;
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154 uint8 rx_empty_watermark;
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155 uint8 rx_full_watermark;
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156 }SPI_INIT_PARM,*SPI_INIT_PARM_P;
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159 /**---------------------------------------------------------------------------*
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161 **---------------------------------------------------------------------------*/
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162 // SPI control register filed definitions
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165 VOLATILE uint32 data; // Transmit word or Receive word
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166 VOLATILE uint32 clkd; // clock dividor register
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167 VOLATILE uint32 ctl0; // control register
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168 VOLATILE uint32 ctl1; // Receive Data full threshold/Receive Data full threshold
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169 VOLATILE uint32 ctl2; // 2-wire mode reigster
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170 VOLATILE uint32 ctl3; // transmit data interval
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171 VOLATILE uint32 ctl4; // transmit data interval
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172 VOLATILE uint32 ctl5; // transmit data interval
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173 VOLATILE uint32 ien; // interrutp enable register
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174 VOLATILE uint32 iclr; // interrupt clear register
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175 VOLATILE uint32 iraw; // interrupt clear register
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176 VOLATILE uint32 ists; // interrupt clear register
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177 VOLATILE uint32 sts1; // fifo cnt register, bit[5:0] for RX and [13:8] for TX
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178 VOLATILE uint32 sts2; // masked interrupt status register
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179 VOLATILE uint32 dsp_wait; // Used for DSP control
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180 VOLATILE uint32 sts3; // tx_empty_threshold and tx_full_threshold
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181 VOLATILE uint32 ctl6;
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182 VOLATILE uint32 sts4;
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183 VOLATILE uint32 fifo_rst;
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184 VOLATILE uint32 ctl7; // SPI_RX_HLD_EN : SPI_TX_HLD_EN : SPI_MODE
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185 VOLATILE uint32 sts5; // CSN_IN_ERR_SYNC2
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186 VOLATILE uint32 ctl8; // SPI_CD_BIT : SPI_TX_DUMY_LEN : SPI_TX_DATA_LEN_H
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187 VOLATILE uint32 ctl9; // SPI_TX_DATA_LEN_L
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188 VOLATILE uint32 ctl10; // SPI_RX_DATA_LEN_H : SPI_RX_DUMY_LEN
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189 VOLATILE uint32 ctl11; // SPI_RX_DATA_LEN_L
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190 VOLATILE uint32 ctl12; // SW_TX_REQ : SW_RX_REQ
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193 /**---------------------------------------------------------------------------*
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194 ** Constant Variable *
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195 **---------------------------------------------------------------------------*/
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198 // ------------------------------------------------------------------------- //
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199 // Function Propertype
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200 // ------------------------------------------------------------------------- //
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203 PUBLIC void SPI_Enable( uint32 spi_id, BOOLEAN is_en);
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204 PUBLIC void SPI_Reset( uint32 spi_id, uint32 ms);
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205 PUBLIC void SPI_ClkSetting(uint32 spi_id, uint32 clk_src, uint32 clk_div);
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207 PUBLIC void SPI_SetCsLow( uint32 spi_sel_csx , BOOLEAN is_low);
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208 PUBLIC void SPI_SetCd( uint32 cd);
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209 PUBLIC void SPI_SetSpiMode(uint32 spi_mode);
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210 PUBLIC void SPI_SetDatawidth(uint32 datawidth);
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211 PUBLIC BOOLEAN SPI_EnableDMA(uint32 spi_index,BOOLEAN is_en);
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213 PUBLIC void SPI_SetTxLen(uint32 data_len, uint32 dummy_bitlen);
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214 PUBLIC void SPI_SetRxLen(uint32 data_len, uint32 dummy_bitlen);
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215 PUBLIC void SPI_TxReq( void );
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216 PUBLIC void SPI_RxReq( void );
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217 PUBLIC void SPI_WaitTxFinish();
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219 PUBLIC void SPI_Init(SPI_INIT_PARM *spi_parm);
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220 PUBLIC void SPI_WriteData(uint32 data, uint32 data_len, uint32 dummy_bitlen);
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221 PUBLIC uint32 SPI_ReadData( uint32 data_len, uint32 dummy_bitlen );
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226 #endif /*_SPI_TEST_H*/
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