1 /******************************************************************************
2 ** File Name: spi_reg_v0.h *
3 ** Author: Steve.Zhan *
5 ** Copyright: 2010 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 06/05/2010 Steve.Zhan Create. *
13 ******************************************************************************/
14 #ifndef _SPI_REG_V0_H_
15 #define _SPI_REG_V0_H_
16 /*----------------------------------------------------------------------------*
18 **------------------------------------------------------------------------- */
20 /**---------------------------------------------------------------------------*
22 **--------------------------------------------------------------------------*/
27 /**---------------------------------------------------------------------------*
29 **---------------------------------------------------------------------------*/
30 /*----------SPI Interface Control Registers----------*/
31 #define SPI_TXD (SPI_BASE + 0x0000)
32 #define SPI_CLKD (SPI_BASE + 0x0004)
33 #define SPI_CTL0 (SPI_BASE + 0x0008)
34 #define SPI_CTL1 (SPI_BASE + 0x000c)
35 #define SPI_CTL2 (SPI_BASE + 0x0010)
36 #define SPI_CTL3 (SPI_BASE + 0x0014)
37 #define SPI_CTL4 (SPI_BASE + 0x0018)
38 #define SPI_CTL5 (SPI_BASE + 0x001c)
39 #define SPI_INT_IEN (SPI_BASE + 0x0020)
40 #define SPI_INT_CLR (SPI_BASE + 0x0024)
41 #define SPI_INT_RAW (SPI_BASE + 0x0028)
42 #define SPI_INT_STS (SPI_BASE + 0x002c)
43 #define SPI_STS1 (SPI_BASE + 0x0030)
44 #define SPI_STS2 (SPI_BASE + 0x0034)
45 #define SPI_DSP_WAIT (SPI_BASE + 0x0038)
46 #define SPI_STS3 (SPI_BASE + 0x003c)
47 // SPI control register filed definitions
50 VOLATILE uint32 data; // data register
51 VOLATILE uint32 clkd; // clock dividor register
52 VOLATILE uint32 ctl0; // control register
53 VOLATILE uint32 ctl1; // Receive Data full threshold/Receive Data full threshold
54 VOLATILE uint32 ctl2; // 2-wire mode reigster
55 VOLATILE uint32 ctl3; // transmit data interval
56 VOLATILE uint32 ctl4; // transmit data interval
57 VOLATILE uint32 ctl5; // transmit data interval
58 VOLATILE uint32 ien; // interrutp enable register
59 VOLATILE uint32 iclr; // interrupt clear register
60 VOLATILE uint32 iraw; // interrupt clear register
61 VOLATILE uint32 ists; // interrupt clear register
62 VOLATILE uint32 sts1; // fifo cnt register, bit[5:0] for RX and [13:8] for TX
63 VOLATILE uint32 sts2; // masked interrupt status register
64 VOLATILE uint32 dsp_wait; // Used for DSP control
65 VOLATILE uint32 sts3; // Rx_cnt, working in only receive mode as master
68 VOLATILE uint32 fifo_rst;
71 // Bit define for register STS2
72 #define SPI_RX_FIFO_FULL BIT_0
73 #define SPI_RX_FIFO_EMPTY BIT_1
74 #define SPI_TX_FIFO_FULL BIT_2
75 #define SPI_TX_FIFO_EMPTY BIT_3
76 #define SPI_RX_FIFO_REALLY_FULL BIT_4
77 #define SPI_RX_FIFO_REALLY_EMPTY BIT_5
78 #define SPI_TX_FIFO_REALLY_FULL BIT_6
79 #define SPI_TX_FIFO_REALLY_EMPTY BIT_7
80 #define SPI_TX_BUSY BIT_8
81 // Bit define for register ctr1
82 #define SPI_RX_MODE BIT_12
83 #define SPI_TX_MODE BIT_13
84 // Bit define for register ctr2
85 #define SPI_DMA_EN BIT_6
86 // Bit define for register ctr4
87 #define SPI_START_RX BIT_9
90 /**----------------------------------------------------------------------------*
91 ** Local Function Prototype **
92 **----------------------------------------------------------------------------*/
94 /**----------------------------------------------------------------------------*
95 ** Function Prototype **
96 **----------------------------------------------------------------------------*/
99 /**----------------------------------------------------------------------------*
101 **----------------------------------------------------------------------------*/
105 /**---------------------------------------------------------------------------*/