1 /******************************************************************************
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2 ** File Name: sc8825_emc_cfg.h *
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3 ** Author: Johnny.Wang *
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4 ** DATE: 2012/12/04 *
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5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
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7 ******************************************************************************/
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8 #include "sci_types.h"
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12 /******************************************************************************
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14 ******************************************************************************/
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15 #define UL_ONEBITS 0xffffffff
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17 #define ONE 0x00000001
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21 /******************************************************************************
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23 ******************************************************************************/
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28 CTL_STATE_CONFIG_REQ,
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30 CTL_STATE_ACCESS_REQ,
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31 CTL_STATE_LOW_POWER,
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32 CTL_STATE_LOW_POWER_ENTRY_REQ,
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33 CTL_STATE_LOW_POWER_EXIT_REQ,
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58 DRAM_64MBIT = 0x00800000,
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59 DRAM_128MBIT = 0x01000000,
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60 DRAM_256MBIT = 0x02000000,
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61 DRAM_512MBIT = 0x04000000,
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62 DRAM_1GBIT = 0x08000000,
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63 DRAM_2GBIT = 0x10000000,
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64 DRAM_4GBIT = 0x20000000,
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65 DRAM_8GBIT = 0x40000000,
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66 DRAM_16GBIT = 0x80000000,
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92 DRAM_BT_SEQ = 0, //burst type = sequential(default)
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93 DRAM_BT_INT = 1 //burst type = interleaved
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98 DRAM_WRAP = 0, //warp mode
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99 DRAM_NO_WRAP = 1 //no warp mode
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128 CLK_24MHZ = 24000000,
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129 CLK_26MHZ = 26000000,
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130 CLK_38_4MHZ = 38400000,
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131 CLK_48MHZ = 48000000,
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132 CLK_64MHZ = 64000000,
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133 CLK_76_8MHZ = 76800000,
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134 CLK_96MHZ = 96000000,
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135 CLK_100MHZ = 100000000,
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136 CLK_150MHZ = 150000000,
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137 CLK_153_6MHZ = 153600000,
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138 CLK_192MHZ = 192000000,
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139 CLK_200MHZ = 200000000,
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140 CLK_333MHZ = 333000000,
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141 CLK_400MHZ = 400000000,
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142 CLK_427MHZ = 427000000,
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143 CLK_450MHZ = 450000000,
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144 CLK_500MHZ = 500000000,
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145 CLK_525MHZ = 525000000,
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146 CLK_537MHZ = 537000000,
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147 CLK_540MHZ = 540000000,
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148 CLK_550MHZ = 550000000,
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149 CLK_800MHZ = 800000000,
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150 CLK_1000MHZ = 1000000000,
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151 EMC_CLK_400MHZ = 400000000,
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152 EMC_CLK_450MHZ = 450000000,
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153 EMC_CLK_500MHZ = 500000000
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157 typedef enum EMC_CS_NUM_TAG
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164 typedef enum EMC_PORT_NUM_TAG
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170 EMC_PORT3_DSPP = 3,
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171 EMC_PORT4_DSPD = 4,
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172 EMC_PORT5_DISP = 5,
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181 RANK_BANK_ROW_COL = 0x000,
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182 RANK_ROW_BANK_COL = 0x100,
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183 BANK_ROW_RANK_COL = 0x200
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184 }EMC_ADDR_MAP_TYPE_E;
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188 EMC_PORT_BE = 0, //Best effot, low priority
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189 EMC_PORT_LL = 1, //Low latnecy,high priority
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190 EMC_PORT_DD = 2 //dynamic determind,normal priority
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191 }EMC_PORT_PRIORITY_E;
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195 PHY_ACT_INIT = BIT_0, //trigger DDR system initialization,include PHY initialization,DRAM initialization,and PHY training
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196 PHY_ACT_DLLSRST = BIT_1, //dll soft reset
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197 PHY_ACT_DLLOCK = BIT_2, //waite dll lock done
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198 PHY_ACT_ZCAL = BIT_3, //impedance calibrate,perform PHY impedance calibration
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199 PHY_ACT_ITMSRST = BIT_4, //interface timing module soft reset
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200 PHY_ACT_DDR3RST = BIT_5, //ddr3 reset
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201 PHY_ACT_DRAMINIT= BIT_6, //excute DRAM initialization
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202 PHY_ACT_DQSTRN = BIT_7, //excute dqs training routine
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203 PHY_ACT_EYETRN = BIT_8, //read data eye training,not support in this phy version
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204 PHY_ACT_ICPC = BIT_16, //initialization complete pin configuration
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205 PHY_ACT_DLLBYP = BIT_17, //DLL bypass
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206 PHY_ACT_CTLDINIT= BIT_18, //Control DRAM initialization,if set DRAM initialization will be excute by controller,
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207 PHY_ACT_CLRSR = BIT_28, //Clear all status register,include PGSR and DXnGSR
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208 PHY_ACT_LOCKBYP = BIT_29, //DLL lock bypass,if set,DLL lock wait will auto tigger after reset
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209 PHY_ACT_ZCALBYP = BIT_30, //impedance calibration bypass, if set, impedance calibration will auto tigger after reset
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210 PHY_ACT_INITBYP = BIT_31 //Initialization bypass
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215 PHY_STATE_INIT_DONE = 0x1,
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216 PHY_STATE_DLL_LOCK_DONE = 0x2,
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217 PHY_STATE_ZQCL_DONE = 0x4,
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218 PHY_STATE_DRAM_INIT_DONE= 0x8,
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219 PHY_STATE_DTDONE = 0x10,
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220 PHY_STATE_DTERR = 0x20,
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221 PHY_STATE_DTIERR = 0x40,
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222 PHY_STATE_DRIFT_ERR = 0x80,
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223 PHY_STATE_TQ = 0x80000000,
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229 MEM_ACCESS_BYTE = 1,
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230 MEM_ACCESS_HWORD = 2,
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231 MEM_ACCESS_WORD = 4
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232 }MEM_ACCESS_TYPE_E;
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243 DQS_STEP_DLY_MIN = 0,
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244 DQS_STEP_DLY_SUB3 = 0,
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245 DQS_STEP_DLY_SUB2 = 1,
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246 DQS_STEP_DLY_SUB1 = 2,
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247 DQS_STEP_DLY_NOM = 3,
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248 DQS_STEP_DLY_DEF = 3,
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249 DQS_STEP_DLY_ADD1 = 4,
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250 DQS_STEP_DLY_ADD2 = 5,
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251 DQS_STEP_DLY_ADD3 = 6,
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252 DQS_STEP_DLY_ADD4 = 7,
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253 DQS_STEP_DLY_MAX = 7
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256 //DQS gating phase select
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259 DQS_PHS_DLY_MIN = 0,
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260 DQS_PHS_DLY_90 = 0,
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261 DQS_PHS_DLY_180 = 1,
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262 DQS_PHS_DLY_DEF = 1,
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263 DQS_PHS_DLY_270 = 2,
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264 DQS_PHS_DLY_360 = 3,
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265 DQS_PHS_DLY_MAX = 3
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268 //DQS gating system latency
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271 DQS_CLK_DLY_MIN = 0,
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272 DQS_CLK_DLY_DEF = 0,
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273 DQS_CLK_DLY_1CLK = 1,
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274 DQS_CLK_DLY_2CLK = 2,
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275 DQS_CLK_DLY_3CLK = 3,
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276 DQS_CLK_DLY_4CLK = 4,
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277 DQS_CLK_DLY_5CLK = 5,
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278 DQS_CLK_DLY_MAX = 5
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281 //slave dll phase trim
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284 SDLL_PHS_DLY_DEF = 0x0,
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285 SDLL_PHS_DLY_36 = 0x3,
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286 SDLL_PHS_DLY_54 = 0x2,
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287 SDLL_PHS_DLY_72 = 0x1,
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288 SDLL_PHS_DLY_90 = 0x0,
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289 SDLL_PHS_DLY_108 = 0x4,
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290 SDLL_PHS_DLY_126 = 0x8,
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291 SDLL_PHS_DLY_144 = 0x12
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296 LPDDR2_DS_34_OHM = 0xd,
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297 LPDDR2_DS_40_OHM = 0xb,
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298 LPDDR2_DS_48_OHM = 0x9,
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299 LPDDR2_DS_60_OHM = 0x7,
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300 LPDDR2_DS_80_OHM = 0x5
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301 }LPDDR2_MEM_DS_T_E;
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305 PUBL_DS_34OHM = 0xd,
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306 PUBL_DS_40OHM = 0xb,
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307 PUBL_DS_48OHM = 0x9,
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308 PUBL_DS_60OHM = 0x7,
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309 PUBL_DS_80OHM = 0x5
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314 LPDDR1_DS_33_OHM = 0xa,
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315 LPDDR1_DS_31_OHM = 0xb,
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316 LPDDR1_DS_48_OHM = 0xc,
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317 LPDDR1_DS_43_OHM = 0xd,
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318 LPDDR1_DS_39_OHM = 0xe,
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319 LPDDR1_DS_55_OHM = 0x5,
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320 LPDDR1_DS_64_OHM = 0x4
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321 }LPDDR1_MEM_DS_T_E;
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326 DQS_PDU_688ohm = 1,
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327 DQS_PDU_611ohm = 2,
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328 DQS_PDU_550ohm = 3,
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329 DQS_PDU_500ohm = 4,
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331 DQS_PDU_458ohm = 5,
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332 DQS_PDU_393ohm = 6,
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333 DQS_PDU_344ohm = 7,
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353 CMD_MDR_NOT_EXIT = 0,
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354 CMD_MDR_RD_ONLY = 1,
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355 CMD_MDR_WR_ONLY = 2,
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357 CMD_MDR_SUCCESS = 4
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361 /******************************************************************************
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363 ******************************************************************************/
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366 // timing for lpddr1 and lpddr2
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367 uint32 tREFI; // average Refresh interval time between each row,normall = 7800 ns
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368 uint32 tRAS; // ACTIVE to PERCHARGE command period
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369 uint32 tRC; // ACTIVE to ACTIVE command period
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370 uint32 tRFC; // AUTO REFRESH to ACTIVE/AUTO REFRESH command period
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371 uint32 tRCD; // ACTIVE to READ/WRITE delay
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372 uint32 tRP; // PRECHARGE command period
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373 uint32 tRRD; // ACTIVE to ACTIVE delay
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374 uint32 tWR; // WRITE recovery time
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375 uint32 tWTR; // internal write to read command delay
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376 uint32 tXSR; // Self Refresh Exit to next valid command delay
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377 uint32 tXP; // Exit Power Down to next valid command delay
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378 // timing for lpddr2 and ddr3
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379 uint32 tMRR; // MODE REGISTR READ command period
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380 uint32 tCKESR; // CKE signal min pulse width during self-refresh
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381 uint32 tZQCS; // ZQ Calibration short time
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382 uint32 tZQCL; // ZQ Calibration long time
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383 }DRAM_TIMING_INFO_T, *DRAM_TIMING_INFO_T_PTR;
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387 DRAM_TYPE_E mem_type; //dram type: lpddr1,lpddr2-s2,lpddr2-s4
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388 uint32 cs_num; //cs number summary,should be 1 or 2
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389 MEM_BANK_NUM_E bank_num; //bank number,lpddr1 and lpddr2 usually 4,ddr3 usually 8
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390 DRAM_DENSITY_E cs0_cap; //cs0 density
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391 DRAM_DENSITY_E cs1_cap; //cs1 density
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393 IO_WIDTH_E io_width; //data io width, usually=16 or 32
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394 DRAM_BL_E bl; //burst lenght,usually=2,4,8,16
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395 DRAM_CL_E rl; //read cas latency, usually=1,2,3,4,5,6,7,8
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396 DRAM_CL_E wl; //write cas latency, usually=1,2,3,4,5,6,7,8
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397 } DRAM_MODE_INFO_T, *DRAM_MODE_INFO_T_PTR;
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403 DRAM_TIMING_INFO_T_PTR time_info;
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404 DRAM_MODE_INFO_T_PTR mode_info;
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406 DRAM_INFO_T, *DRAM_INFO_T_PTR;
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408 #define RDWR_ORDER_OFF FALSE
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409 #define RDWR_ORDER_ON TRUE
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412 uint32 port_data_quantum;
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414 EMC_PORT_PRIORITY_E port_priority;
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415 }EMC_CHN_INFO_T, *EMC_CHN_INFO_T_PTR;
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421 BOOLEAN DLL_LOCK_DONE;
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423 BOOLEAN DRAM_INIT_DONE;
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424 BOOLEAN DATA_TR_DONE;
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425 BOOLEAN DATA_TR_ERR;
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426 BOOLEAN DATA_TR_INTER_ERR;
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427 BOOLEAN DQS_DRIFT_ERROR;
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428 }EMC_PHY_STATUS_T,*EMC_PHY_STATUS_T_PTR;
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432 // MEM_DS_T_E mem_ds;
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433 SDLL_PHS_DLY_E sdll_phase_b0;
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434 SDLL_PHS_DLY_E sdll_phase_b1;
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435 SDLL_PHS_DLY_E sdll_phase_b2;
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436 SDLL_PHS_DLY_E sdll_phase_b3;
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437 DQS_STEP_DLY_E dqs_step_b0;
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438 DQS_STEP_DLY_E dqs_step_b1;
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439 DQS_STEP_DLY_E dqs_step_b2;
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440 DQS_STEP_DLY_E dqs_step_b3;
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441 }ADJ_PAR_T,*ADJ_PAR_T_PTR;
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447 LPDDR2_DEFAULT = 0x00,
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448 LPDDR2_SAMSUNG = 0x01,
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449 LPDDR2_QIMONDA = 0x02,
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450 LPDDR2_ELPIDA = 0x03,
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451 LPDDR2_ETRON = 0x04,
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452 LPDDR2_NANYA = 0X05,
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453 LPDDR2_HYNIX = 0x06,
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454 LPDDR2_MOSEL = 0X07,
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455 LPDDR2_WINBOND = 0X08,
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456 LPDDR2_ESMT = 0X09,
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457 LPDDR2_SPANSION= 0X0B,
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459 LPDDR2_ZMOS = 0X0D,
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460 LPDDR2_INTLE = 0X0E,
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461 LPDDR2_NUMONYX = 0XFE,
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462 LPDDR2_MiCRON = 0XFF
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464 }LPDDR2_MANUFACTURE_ID_E;
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467 LPDDR2_MANUFACTURE_ID_E cust_lpddr2_id;
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468 PUBL_DS_E cust_publ_ds;
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469 LPDDR2_MEM_DS_T_E cust_lpddr2_mem_ds;
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470 SDLL_PHS_DLY_E cust_b0_sdll_phs;
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471 SDLL_PHS_DLY_E cust_b1_sdll_phs;
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472 SDLL_PHS_DLY_E cust_b2_sdll_phs;
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473 SDLL_PHS_DLY_E cust_b3_sdll_phs;
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474 DQS_STEP_DLY_E cust_b0_dqs_step;
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475 DQS_STEP_DLY_E cust_b1_dqs_step;
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476 DQS_STEP_DLY_E cust_b2_dqs_step;
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477 DQS_STEP_DLY_E cust_b3_dqs_step;
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478 }customer_timing_t;
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480 /*******************************************************************************
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481 Variable and Array definiation
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482 *******************************************************************************/
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483 #define DRAM_BURST_TYPE DRAM_BT_SEQ
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484 #define DRAM_BURST_WRAP DRAM_NO_WRAP
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485 #define NONE_MDR 0XFF
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486 #define DQS_PDU_RES DQS_PDU_500ohm //dqs pull up and pull down resist
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488 #define EMC_SMALL_CODE_SIZE
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489 const EMC_CHN_INFO_T EMC_CHN_INFO_ARRAY[EMC_PORT_MAX] = {{0x10,RDWR_ORDER_OFF,EMC_PORT_BE},//AP port set
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490 {0x10,RDWR_ORDER_OFF,EMC_PORT_BE},//GPU port set
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491 {0x10,RDWR_ORDER_ON, EMC_PORT_BE},//MST port set
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492 {0x10,RDWR_ORDER_ON, EMC_PORT_LL},//DSPP port set
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493 {0x10,RDWR_ORDER_ON, EMC_PORT_LL},//DSPD port set
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494 {0x10,RDWR_ORDER_OFF,EMC_PORT_LL},//DISP port set
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495 {0x10,RDWR_ORDER_OFF,EMC_PORT_LL},//MM port set
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496 {0x10,RDWR_ORDER_ON, EMC_PORT_BE}};//CP port set
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497 const char* DRAM_CHIP_NAME_INFO_ARRAY[] =
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499 // "NORMAL_LPDDR1_1CS_1G_32BIT",
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500 "NORMAL_LPDDR1_1CS_2G_32BIT",
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501 "NORMAL_LPDDR1_2CS_4G_32BIT",
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502 "NORMAL_LPDDR2_1CS_4G_32BIT",
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503 "NORMAL_LPDDR2_2CS_8G_32BIT"
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504 // "HYNIX_LPDDR1_H9DA4GH4JJAMCR4EM",
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505 // "SAMSUNG_LPDDR2_KMKJS000VM"
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508 const DRAM_MODE_INFO_T DRAM_MODE_INFO_ARRAY[] =
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510 //{DRAM_LPDDR1, ONE_CS,FOUR_BANK,DRAM_1GBIT,DRAM_0BIT, IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//NORMAL_LPDDR1_1CS_1G_32BIT
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511 {DRAM_LPDDR1, ONE_CS,FOUR_BANK,DRAM_2GBIT,DRAM_0BIT, IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//NORMAL_LPDDR1_1CS_2G_32BIT
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512 {DRAM_LPDDR1, TWO_CS,FOUR_BANK,DRAM_2GBIT,DRAM_2GBIT, IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//NORMAL_LPDDR1_2CS_4G_32BIT
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513 {DRAM_LPDDR2_S4,ONE_CS,FOUR_BANK,DRAM_4GBIT,DRAM_0BIT, IO_WIDTH_32,DRAM_BL4,LPDDR2_RL6,LPDDR2_WL3},//NORMAL_LPDDR2_1CS_4G_32BIT
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514 {DRAM_LPDDR2_S4,TWO_CS,FOUR_BANK,DRAM_4GBIT,DRAM_4GBIT, IO_WIDTH_32,DRAM_BL4,LPDDR2_RL6,LPDDR2_WL3} //NORMAL_LPDDR2_2CS_8G_32BIT
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515 //{DRAM_LPDDR1, TWO_CS,FOUR_BANK,DRAM_2GBIT,DRAM_2GBIT, IO_WIDTH_32,DRAM_BL2,LPDDR1_CL3,LPDDR1_CL0},//HYNIX_LPDDR1_H9DA4GH4JJAMCR4EM
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516 //{DRAM_LPDDR2_S4,TWO_CS,FOUR_BANK,DRAM_4GBIT,DRAM_4GBIT, IO_WIDTH_32,DRAM_BL4,LPDDR2_RL6,LPDDR2_WL3} //SAMSUNG_LPDDR2_KMKJS000VM
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520 const DRAM_TIMING_INFO_T DRAM_TIMING_INFO_ARRAY[] =
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522 // ns ns ns tRFC(ns) ns tRP(ns) ns ns clk ns ns clk ns ns ns
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523 // tREFI tRAS tRC /tRFCab tRCD /tRPpb tRRD tWR tWTR tXSR tXP tMRR tCKESR tZQCS tZQCL
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524 // {7800, 50, 80, 110, 30, 30, 15, 15, 3, 140, 20, 0, 0, 0, 0},//NORMAL_LPDDR1_1CS_1G_32BIT
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525 {7800, 40, 80, 90, 20, 15, 15, 15, 2, 140, 20, 0, 0, 0, 0},//NORMAL_LPDDR1_1CS_2G_32BIT
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526 {7800, 40, 80, 90, 20, 15, 15, 15, 2, 140, 20, 0, 0, 0, 0},//NORMAL_LPDDR1_2CS_4G_32BIT
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527 {3900, 43, 65, 130, 20, 20, 10, 15, 3, 140, 20, 2, 15, 90, 360},//NORMAL_LPDDR2_1CS_4G_32BIT
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528 {3900, 43, 65, 130, 20, 20, 10, 15, 3, 140, 20, 2, 15, 90, 360} //NORMAL_LPDDR2_2CS_8G_32BIT
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529 // {7800, 50, 80, 90, 30, 30, 15, 15, 3, 140, 20, 0, 0, 0, 0},//HYNIX_LPDDR1_H9DA4GH4JJAMCR4EM
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530 // {3900, 50, 80, 130, 20, 30, 15, 15, 3, 140, 20, 2, 15, 90, 360} //SAMSUNG_LPDDR2_KMKJS000VM
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533 const customer_timing_t CUSTOMER_TIMING_INFO[] =
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545 DQS_STEP_DLY_ADD2},
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547 {LPDDR2_SAMSUNG, //manufacturer
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557 DQS_STEP_DLY_ADD2},
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559 {LPDDR2_MiCRON, //manufacturer
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569 DQS_STEP_DLY_ADD2},
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571 {LPDDR2_HYNIX, //manufacturer
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581 DQS_STEP_DLY_ADD2},
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585 /*******************************************************************************
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587 *******************************************************************************/
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