1 /******************************************************************************
2 ** File Name: dma_phy.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 2005-9-17 weihua.wang Create. *
13 ** 2005-12-28 weihua.wang modify the macro def of DMA_MAX_TRANSSIZE *
14 ** DMA_MAX_TRANSSIZE and include file for 6800 *
15 ** 12/06/2010 Jeff.Li Modify for new chip driver architecture. *
16 ******************************************************************************/
21 /**---------------------------------------------------------------------------*
23 **---------------------------------------------------------------------------*/
29 /**-----------------------------------------------------------------------------*
30 ** Macro for interface
31 **------------------------------------------------------------------------------*/
32 /**----------------------------------------------------------------------------*
34 **----------------------------------------------------------------------------*/
36 /**----------------------------------------------------------------------------*
37 ** Local Function Prototype **
38 **----------------------------------------------------------------------------*/
39 /**----------------------------------------------------------------------------*
40 ** Function Prototype **
41 **----------------------------------------------------------------------------*/
42 #if defined(PLATFORM_SC6600L)
43 /*****************************************************************************/
45 // Global resource dependence:
46 // Author: weihua.wang
48 /*****************************************************************************/
49 ISR_EXE_T DMA_IrqHandler (uint32 num);
51 //*****************************************************************************/
53 // Global resource dependence:
54 // Author: weihua.wang
56 /*****************************************************************************/
57 void DMA_HALInit (void);
59 /*****************************************************************************/
60 // Description: dma hw channel config
61 // Global resource dependence:
62 // Author: weihua.wang
63 // Note: channel : dma channel no
64 // dma_type: hard dma/soft dma
65 // int_type: burst/alltransfer/none
66 // chn_param: pointer to the dma channel param
67 /*****************************************************************************/
68 uint32 DMA_HALChannelCfg (uint32 channel, uint32 dma_type,uint32 int_type, DMA_CTL_CFG_PTR chn_param);
70 /*****************************************************************************/
71 // Description: dma hw channel config
72 // Global resource dependence:
73 // Author: weihua.wang
74 // Note: channel : dma channel no
75 // dma_type: hard dma/soft dma
76 // int_type: burst/alltransfer/none
77 // chn_param: pointer to the dma channel param
78 /*****************************************************************************/
79 uint32 DMA_HALlinklistCfg (DMA_CTL_CFG_PTR chn_param,DMA_CHx_CTL_T *listlinkcfg);
81 //*****************************************************************************/
82 // Description: dma interrupt call back register
83 // Global resource dependence:
84 // Author: weihua.wang
86 /*****************************************************************************/
87 uint32 DMA_HALRegCallBack (uint32 channel, DMA_ISR_HANDLER callback);
89 /*****************************************************************************/
90 void DMA_SetBlockDelay (uint32 delay);
92 #elif defined(PLATFORM_SC6800H) || defined(PLATFORM_SC8800G) || defined(PLATFORM_SC8800H)|| defined(CONFIG_SC8810)
93 //=============================================================================
94 // add function for new dma driver
95 //=============================================================================
97 /**---------------------------------------------------------------------------*
99 **----------------------------------------------------------------------------*/
100 //dma channel control register array
101 //this regster struct is used both by dma_phy and dma.c, it is also used as logic element for list mode
102 //so this struct is moved from dma_reg_v0.h to dma_phy.h
103 typedef struct _DMA_CHN_CTL_REG
106 volatile uint32 total_length;
107 volatile uint32 src_addr;
108 volatile uint32 dest_addr;
109 volatile uint32 ll_ptr;
110 volatile uint32 sdep;
113 } DMA_CHN_CTL_REG_T, *DMA_CHN_CTL_REG_T_PTR;
115 /**---------------------------------------------------------------------------*
116 ** Function Prototype **
117 **----------------------------------------------------------------------------*/
119 //*****************************************************************************/
120 // Description: Init DMA controller
121 // Global resource dependence:
122 // Author: Guofu.Huang
124 /*****************************************************************************/
125 PUBLIC void DMA_PHY_Init (void);
127 //*****************************************************************************/
128 // Description: pause or resume dma transfer
129 // Global resource dependence:
130 // Author: Guofu.Huang
131 // Note: is_pause: SCI_TRUE=pause,SCI_FALSE=resume
132 /*****************************************************************************/
133 PUBLIC void DMA_PHY_SetPause (BOOLEAN is_pause);
135 //*****************************************************************************/
136 // Description: setting dma wrap addr
137 // Global resource dependence:
138 // Author: Guofu.Huang
139 // Note: wrapstart_addr: start addr
140 // wrapend_addr:end addr
141 /*****************************************************************************/
142 PUBLIC void DMA_PHY_SetWrapAddr (uint32 wrapstart_addr, uint32 wrapend_addr);
144 //*****************************************************************************/
145 // Description: setting dma channnel user id
146 // Global resource dependence:
147 // Author: Guofu.Huang
148 // Note: channel: chn index
149 // uid:channel user id
150 /*****************************************************************************/
151 PUBLIC void DMA_PHY_SetChnUID (uint32 channel, uint32 uid);
153 //*****************************************************************************/
154 // Description: setting dma channnel work mode
155 // Global resource dependence:
156 // Author: Guofu.Huang
157 // Note: channel: chn index
158 // workmode:channel work mode
159 /*****************************************************************************/
160 PUBLIC void DMA_PHY_SetChnWorkMode (uint32 channel, DMA_CHN_WORKMODE_E workmode);
161 //*****************************************************************************/
162 // Description: setting dma channel priority
163 // Global resource dependence:
164 // Author: Guofu.Huang
165 // Note: channel: chn index
166 // priority: new priority value
167 /*****************************************************************************/
168 PUBLIC void DMA_PHY_SetChnPriority (uint32 chn, DMA_CHN_PRIORITY_E pri);
170 //*****************************************************************************/
171 // Description: Enable/Disable a dma channel
172 // Global resource dependence:
173 // Author: Guofu.Huang
174 // Note: channel: chn index
175 // is_enable: enable/disable a chn
176 /*****************************************************************************/
177 PUBLIC void DMA_PHY_ChnEnable (uint32 channel, BOOLEAN is_enable);
179 //*****************************************************************************/
180 // Description: configure dma interrupt
181 // Global resource dependence:
182 // Author: Guofu.Huang
183 // Note: channel: chn index
184 // inttype: dma chn interrupt type
185 // is_enable:enable/disable interrupt
186 /*****************************************************************************/
187 PUBLIC void DMA_PHY_ChnIntConfig (uint32 channel, uint32 inttype, DMA_HAL_ISR_HANDLER callback);
189 //*****************************************************************************/
190 // Description: configure dma channel related register
191 // Global resource dependence:
192 // Author: Guofu.Huang
193 // Note: chncfgstruct: dma chn configure structure
194 // chn_ctl_ptr: a pointer of dma chn control register array
195 /*****************************************************************************/
196 PUBLIC void DMA_PHY_FillChnCtlReg (DMA_CHNCFG_PTR chnparam, DMA_CHN_CTL_REG_T_PTR dma_chn_ctl_ptr);
197 //*****************************************************************************/
198 // Description: configure dma channel related register
199 // Global resource dependence:
200 // Author: Guofu.Huang
201 // Note: channel: chn index
202 // chncfgstruct: dma chn configure structure
203 /*****************************************************************************/
204 PUBLIC void DMA_PHY_ChnConfig (uint32 channel,DMA_CHNCFG_PTR chnparam);
206 /*****************************************************************************/
207 // Description: get dma channel transdone interrupt raw status
208 // Global resource dependence:
209 // Author: Guofu.Huang
210 // Note: channel:dma channel number,0-31
211 // Return value: return SCI_TRUE if the channel transfer finished,
212 /*****************************************************************************/
213 PUBLIC BOOLEAN DMA_PHY_PollingTransDone (uint32 channel);
215 /*****************************************************************************/
216 // Description: get dma channel blockdone interrupt raw status
217 // Global resource dependence:
218 // Author: Guofu.Huang
219 // Note: channel:dma channel number,0-31
220 // Return value: return SCI_TRUE if the channel transfer finished,
221 /*****************************************************************************/
222 PUBLIC BOOLEAN DMA_PHY_PollingBlockDone (uint32 channel);
224 /*****************************************************************************/
225 // Description: get dma channel listdone interrupt raw status
226 // Global resource dependence:
227 // Author: Guofu.Huang
228 // Note: channel:dma channel number,0-31
229 // Return value: return SCI_TRUE if the channel transfer finished,
230 /*****************************************************************************/
231 PUBLIC BOOLEAN DMA_PHY_PollingListDone (uint32 channel);
233 //*****************************************************************************/
234 // Description: get next nodeptr of list when using link list or soft list
235 // Global resource dependence:
236 // Author: Guofu.Huang
237 // Note: channel: dma channel index
238 // Return Value: the ptr of next node
239 /*****************************************************************************/
240 PUBLIC uint32 DMA_PHY_GetLinkListLLPtr (uint32 channel);
242 //*****************************************************************************/
243 // Description: check the current tranfser is the last node in the list
244 // Global resource dependence:
245 // Author: Guofu.Huang
246 // Note: channel: dma channel index
247 // Return Value: if LL_END is valid return SCI_TRUE, else return SCI_FALSE
248 /*****************************************************************************/
249 PUBLIC BOOLEAN DMA_PHY_IsLinkListLLEnd (uint32 channel);
250 //*****************************************************************************/
251 // Description: Set the node is the end
252 // Global resource dependence:
253 // Author: Guofu.Huang
254 // node_ptr:pointer of the node to be modified
255 // is_ll_end: is Linklist end or not
256 // Note: return the ptr of next node
257 /*****************************************************************************/
258 PUBLIC void DMA_PHY_SetLinkListNodeLLEnd (DMA_CHN_CTL_REG_T_PTR node_ptr, BOOLEAN is_ll_end);
260 /*****************************************************************************/
263 /**----------------------------------------------------------------------------*
265 **----------------------------------------------------------------------------*/
269 /**---------------------------------------------------------------------------*/