3 #include "sci_types.h"
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6 /******************************************************************************
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8 ******************************************************************************/
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9 #define INVALIDE_VAL 0xFFFFFFFF
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10 #define STATE_SDRAM_TYPE 0UL
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11 #define STATE_BIT_WIDTH 1UL
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12 #define STATE_COLUM 2UL
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13 #define STATE_ROW 3UL
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14 #define STATE_REINIT 4UL
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15 #define STATE_END 5UL
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17 #define DCFG0_AUTOREF_EN BIT_14
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18 #define STS3_SMEM_IDLE BIT_17
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19 #define STS3_DMEM_IDLE BIT_18
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20 #define STS3_EMC_IDLE BIT_31
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22 #define DCFG2_CNT_DONE BIT_14
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23 #define DCFG2_REF_CNT_RST BIT_15
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24 #define DCFG2_AUTO_SLEEP_MODE BIT_22
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25 #define DCFG2_AUTO_SLEEP_EN BIT_23
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26 #define DCFG2_SAMPLE_RST BIT_24
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27 #define DCFG2_SAMPLE_AUTO_RST_EN BIT_25
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28 #define DCFG0_DLL_LOCK_BIT BIT_14
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29 #define DCFG0_DLL_COMPENSATION_START BIT_11
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30 #define DCFG0_DLL_COMPENSATION_EN BIT_10
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32 #define BK_MODE_1 0 // 1 bank
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33 #define BK_MODE_2 1 // 2 bank
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34 #define BK_MODE_4 2 // 4 bank
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35 #define BK_MODE_8 3 // 8 bank
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37 #define DBURST_REG_BL_1 0
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38 #define DBURST_REG_BL_2 1
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39 #define DBURST_REG_BL_4 2
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40 #define DBURST_REG_BL_8 3
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42 //define mode register domain..
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43 #define MODE_REG_BL_1 0
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44 #define MODE_REG_BL_2 1
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45 #define MODE_REG_BL_4 2
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46 #define MODE_REG_BL_8 3
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48 #define MODE_REG_BT_SEQ 0
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49 #define MODE_REG_BT_INT 1
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51 #define MODE_REG_CL_1 1
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52 #define MODE_REG_CL_2 2
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53 #define MODE_REG_CL_3 3
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55 #define MODE_REG_OPMODE 0
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57 #define ROW_MODE_MASK 0x3
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58 #define COL_MODE_MASK 0x7
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59 #define DATA_WIDTH_MASK 0x1
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60 #define AUTO_PRECHARGE_MASK 0x3
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61 #define CS_POSITION_MASK 0x3
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64 #define EXT_MODE_DS_FULL 0
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65 #define EXT_MODE_DS_HALF 1
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66 #define EXT_MODE_DS_QUARTER 2
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67 #define EXT_MODE_DS_OCTANT 3
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68 #define EXT_MODE_DS_THREE_QUARTERS 4
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74 DDR_DRV_STR_FULL = 0, // 1/1
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75 DDR_DRV_STR_HALF = 1, // 1/2
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76 DDR_DRV_STR_QUAR = 2, // 1/4
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77 DDR_DRV_STR_OCTA = 3, // 1/8
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78 DDR_DRV_STR_TR_Q = 4 // 3/4
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79 }DDR_DRIVER_STRENGTH_T;
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82 #define EXT_MODE_FLAG 1
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83 #define EXT_MODE_PASR_ALL 0
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85 #define SDRAM_EXT_MODE_INVALID 0xffffffff
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87 #define SDRAM_EXT_MODE_REG ((EXT_MODE_FLAG<<15) | (EXT_MODE_DS_FULL<<5) | EXT_MODE_PASR_ALL)
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90 #define WAIT_EMC_IDLE do{ \
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91 while(0 == (REG32(EXT_MEM_STS3)&(STS3_SMEM_IDLE)));\
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92 while(0 == (REG32(EXT_MEM_STS3)&(STS3_DMEM_IDLE)));\
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93 while(0 == (REG32(EXT_MEM_STS3)&(STS3_EMC_IDLE))); \
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96 #define WAIT_EMC_DLL_LOCK do{ \
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97 while(0 == (REG32(EXT_MEM_CFG0_DLL)&(DCFG0_DLL_LOCK_BIT)));\
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102 #define ROW_LINE_MIN 11
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103 #define COLUMN_LINE_MIN 8
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105 /******************************************************************************
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107 ******************************************************************************/
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109 typedef enum SDRAM_ROW_MODE_TAG
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112 ROW_MODE_11 = SDRAM_MIN_ROW, // 11 bit row
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113 ROW_MODE_12, // 12 bit row
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114 ROW_MODE_13, // 13 bit row
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115 ROW_MODE_14, // 14 bit row
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116 SDRAM_MAX_ROW = ROW_MODE_14
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119 typedef enum SDRAM_COLUMN_MODE_TAG
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121 SDRAM_MIN_COLUMN = 0,
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122 COL_MODE_8 = SDRAM_MIN_COLUMN, //8 bit column
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123 COL_MODE_9, //9 bit column
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124 COL_MODE_10, //10 bit column
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125 COL_MODE_11, //11 bit column
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126 COL_MODE_12, //12 bit column
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127 COL_MODE_11_6G, // support 6G bit, column 11-bit
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128 ROW_MODE_15_6G, // support 6G bit, row 15-bit
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129 SDRAM_MAX_COLUMN = ROW_MODE_15_6G
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130 }SDRAM_COLUMN_MODE_E;
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134 BURST_LEN_1_WORD = 0,
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139 BURST_LEN_MAX = BURST_LEN_16_WORD
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140 }SDRAM_BURST_LEN_E;
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143 typedef enum SDRAM_CAS_LATENCY_TAG
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148 CAS_LATENCY_MAX = CAS_LATENCY_3
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149 }SDRAM_CAS_LATENCY_E;
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151 typedef enum SDRAM_CHIP_FEATURE_CL_TAG
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153 SDRAM_FEATURE_CL_2 = (1<<0),
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154 SDRAM_FEATURE_CL_3 = (1<<1),
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155 SDRAM_FEATURE_CL_MAX = SDRAM_FEATURE_CL_3
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157 SDRAM_CHIP_FEATURE_CL_E;
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159 typedef enum SDRAM_CHIP_FEATURE_BL_TAG
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161 SDRAM_FEATURE_BL_1 = (1<<0),
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162 SDRAM_FEATURE_BL_2 = (1<<1),
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163 SDRAM_FEATURE_BL_4 = (1<<2),
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164 SDRAM_FEATURE_BL_8 = (1<<3),
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165 SDRAM_FEATURE_BL_16 = (1<<4),
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166 SDRAM_FEATURE_BL_MAX = SDRAM_FEATURE_BL_16
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168 SDRAM_CHIP_FEATURE_BL_E;
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170 typedef enum SDRAM_CAP_TYPE_TAG
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173 CAP_64M_BIT =0x00800000,
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174 CAP_128M_BIT =0x01000000,
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175 CAP_256M_BIT =0x02000000,
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176 CAP_512M_BIT =0x04000000,
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177 CAP_1G_BIT =0x08000000,
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178 CAP_2G_BIT =0x10000000,
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179 CAP_4G_BIT =0x20000000,
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180 CAP_6G_BIT =0x30000000,
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181 CAP_MAX = CAP_6G_BIT
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189 }DMEM_DATA_WIDTH_E;
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199 EMC_CLK_26MHZ = 26000000,
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200 EMC_CLK_67MHZ = 67000000,
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201 EMC_CLK_133MHZ = 133333333,
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202 EMC_CLK_200MHZ = 200000000,
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203 EMC_CLK_266MHZ = 266666666,
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204 EMC_CLK_333MHZ = 333333333,
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205 EMC_CLK_370MHZ = 370000000,
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206 EMC_CLK_400MHZ = 400000000,
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207 EMC_CLK_MAX = EMC_CLK_400MHZ
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211 CHIP_CLK_26MHZ = 26000000,
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212 CHIP_CLK_800MHZ = 800000000,
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213 CHIP_CLK_850MHZ = 850000000,
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214 CHIP_CLK_900MHZ = 900000000,
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215 CHIP_CLK_1000MHZ = 1000000000,
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216 CHIP_CLK_1100MHZ = 1100000000,
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217 CHIP_CLK_1200MHZ = 1200000000,
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218 CHIP_CLK_1300MHZ = 1300000000,
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219 CHIP_CLK_1400MHZ = 1400000000,
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220 CHIP_CLK_1500MHZ = 1500000000,
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221 CHIP_CLK_MAX = CHIP_CLK_1500MHZ
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226 MEM_1K_BYTE = 1024,
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227 MEM_1M_BYTE = 1024*1024,
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228 MEM_1G_BYTE = 1024*1024*1024
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232 typedef enum MEM_RW_TYPE_TAG
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239 typedef enum MEM_ACCESS_TYPE_TAG
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241 MEM_ACCESS_TYPE_BYTE = 1,
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242 MEM_ACCESS_TYPE_HWORD = 2,
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243 MEM_ACCESS_TYPE_WORD = 4
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247 typedef enum MEM_ENDIAN_TYPE_TAG
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254 typedef enum EMC_ENDIAN_SWITCH_TAG
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256 EMC_ENDIAN_SWITCH_NONE = 3,
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257 EMC_ENDIAN_SWITCH_BYTE = 0,
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258 EMC_ENDIAN_SWITCH_HALF = 1,
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259 EMC_ENDIAN_SWITCH_WORD = 2,
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261 EMC_ENDIAN_SWITCH_E;
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263 typedef enum EMC_DVC_ENDIAN_TAG
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265 EMC_DVC_ENDIAN_DEFAULT = 0,
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266 EMC_DVC_ENDIAN_LITTLE = 0,
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267 EMC_DVC_ENDIAN_BIG = 1
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271 typedef enum EMC_AUTO_GATE_TAG
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273 EMC_AUTO_GATE_DEFAULT = 0,
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274 EMC_AUTO_GATE_DIS = 0,
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275 EMC_AUTO_GATE_EN = 1
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279 typedef enum EMC_AUTO_SLEEP_TAG
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281 EMC_AUTO_SLEEP_DEFAULT = 0,
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282 EMC_AUTO_SLEEP_DIS = 0,
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283 EMC_AUTO_SLEEP_EN = 1
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287 typedef enum EMC_CMD_QUEUE_TAG
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289 EMC_2DB = 0, // 2 stage device burst
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290 EMC_2DB_1CB, // 2-stage device burst and 1-stage channel burst
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291 EMC_2DB_2CB // 2-stage device burst and 2-stage channel burst
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295 typedef enum EMC_CS_MODE_TAG
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297 EMC_CS_MODE_DEFAULT = 0,
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298 EMC_CS0_ENLARGE = 1,
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299 EMC_CS1_ENLARGE = 2
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303 typedef enum EMC_CS_MAP_TAG
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305 EMC_ONE_CS_MAP_DEFAULT = 5,
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306 EMC_ONE_CS_MAP_32MBIT = 0,
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307 EMC_ONE_CS_MAP_64MBIT = 1,
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308 EMC_ONE_CS_MAP_128MBIT = 2,
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309 EMC_ONE_CS_MAP_256MBIT = 3,
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310 EMC_ONE_CS_MAP_512MBIT = 4,
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311 EMC_ONE_CS_MAP_1GBIT = 5,
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312 EMC_ONE_CS_MAP_2GBIT = 6,
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313 EMC_ONE_CS_MAP_4GBIT = 7,
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314 EMC_MAP_MAX = EMC_ONE_CS_MAP_4GBIT
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318 typedef enum EMC_CS_NUM_TAG
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325 typedef enum EMC_BURST_MODE_TAG
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332 typedef enum EMC_BURST_INVERT_TAG
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334 HBURST_TO_SINGLE = 0,
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337 EMC_BURST_INVERT_E;
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339 typedef enum EMC_CHL_NUM_TAG
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342 EMC_AXI_MIN = EMC_CHL_MIN,
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343 EMC_AXI_ARM = EMC_AXI_MIN,
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346 EMC_AXI_MAX = EMC_AXI_DISPC,
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348 EMC_AHB_CP_MTX = EMC_AHB_MIN,
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353 EMC_AHB_MAX = EMC_AHB_VSP,
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354 EMC_CHL_MAX = EMC_AHB_MAX
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359 typedef enum EMC_CLK_SYNC_TAG
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366 typedef enum EMC_REF_CS_TAG
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368 EMC_CS_AREF_OBO = 0, //CSs auto-refresh one by one
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369 EMC_CS_AREF_ALL //CSs auto-refresh at same time
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373 typedef enum EMC_CKE_SEL_TAG
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375 EMC_CKE_SEL_DEFAULT = 0,
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382 typedef enum EMC_DQS_GATE_LOOP_TAG
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384 EMC_DQS_GATE_DEFAULT = 0,
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385 EMC_DQS_GATE_DL = 0,
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386 EMC_DQS_GATE_DL_LB = 1,
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387 EMC_DQS_GATE_LB = 2
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389 EMC_DQS_GATE_LOOP_E;
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391 typedef enum EMC_DQS_GATE_MODE_TAG
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393 EMC_DQS_GATE_MODE_DEFAULT = 0,
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394 EMC_DQS_GATE_MODE0 = 0,
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395 EMC_DQS_GATE_MODE1 = 1
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397 EMC_DQS_GATE_MODE_E;
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399 typedef enum EMC_PHYL1_TIMING_NUM_TAG
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401 #ifdef SDR_SDRAM_SUPPORT
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402 EMC_PHYL1_TIMING_SDRAM_LATENCY2 = 0,
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403 EMC_PHYL1_TIMING_SDRAM_LATENCY3,
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405 EMC_PHYL1_TIMING_DDRAM_LATENCY2,
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406 EMC_PHYL1_TIMING_DDRAM_LATENCY3,
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407 EMC_PHYL1_TIMING_MATRIX_MAX
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408 }EMC_PHYL1_TIMING_NUM_E;
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410 typedef enum EMC_PHYL2_TIMING_NUM_TAG
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412 EMC_PHYL2_TIMING_DLL_OFF = 0,
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413 EMC_PHYL2_TIMING_DLL_ON,
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414 EMC_PHYL2_TIMING_MATRIX_MAX
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415 }EMC_PHYL2_TIMING_NUM_E;
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417 typedef enum SC8810_CLK_NUM_TAG
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419 ARM460_AHB230_EMC = 0,
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426 SEQ = 0, //set memory sequenally
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427 ROW_BY_ROW, //set memory row by row
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428 BANK_BY_BANK, //set memory bank by bank
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429 COL_BY_COL //set memory column by column
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442 }BURST_DATA_TYPE_E;
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446 MCU_CLK_MPLL_SOURCE,
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447 MCU_CLK_TDPLL_DIV2_SOURCE,
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448 MCU_CLK_TDPLL_DIV3_SOURCE,
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449 MCU_CLK_XTL_SOURCE,
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455 EMC_CLK_MPLL_DIV2_SOURCE,
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456 EMC_CLK_DPLL_SOURCE,
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457 EMC_CLK_TDPLL_DIV3_SOURCE,
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458 EMC_CLK_XTL_SOURCE,
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462 typedef enum EMC_CHANNEL_PRIORITY_TAG
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464 EMC_CHL_LOWEST_PRI = 0,
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469 EMC_CHL_HIGHEST_PRI = EMC_CHL_PRI_3,
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474 /******************************************************************************
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476 ******************************************************************************/
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479 //uint8 row_ref_max; //ROW_REFRESH_TIME,Refresh interval time , ns, tREF-max = 7800 ns
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481 uint8 row_pre_min; //ROW_PRECHARGE_TIME , ns, tRP-min = 27 ns.
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482 uint8 rcd_min; // T_RCD,ACTIVE to READ or WRITE delay , ns, tRCD-min = 27 ns
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483 uint32 wr_min; // T_WR ,WRITE recovery time , ns, tWR-min = 15 ns.
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484 uint8 rfc_min; //T_RFC, AUTO REFRESH command period , ns, tRFC-min = 80 ns.
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485 uint32 xsr_min; //T_XSR , ns, tXSR-min = 120 ns.
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486 uint8 ras_min; //T_RAS_MIN , row active time, ns, tRAS-min = 50ns
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488 uint8 mrd_min; //T_MRD , 2 cycles, tMRD-min = 2 cycles.
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490 }SDRAM_TIMING_PARA_T, *SDRAM_TIMING_PARA_T_PTR;
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492 typedef struct SDRAM_CFG_INFO_TAG
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494 SDRAM_ROW_MODE_E row_mode;
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495 SDRAM_COLUMN_MODE_E col_mode;
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496 DMEM_DATA_WIDTH_E data_width;
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497 SDRAM_BURST_LEN_E burst_length;
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498 SDRAM_CAS_LATENCY_E cas_latency;
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499 uint32 ext_mode_val;
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500 DMEM_TYPE_E sdram_type;
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501 EMC_CS_MAP_E cs_position;
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502 } SDRAM_CFG_INFO_T, *SDRAM_CFG_INFO_T_PTR;
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505 typedef struct SDRAM_MODE_TAG
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507 SDRAM_CAP_TYPE_E capacity;
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508 EMC_CS_MAP_E cs_position;
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509 SDRAM_ROW_MODE_E row_mode;
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510 SDRAM_COLUMN_MODE_E col_mode;
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511 DMEM_DATA_WIDTH_E data_width;
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512 // void * reserved;
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513 } SDRAM_MODE_T, * SDRAM_MODE_PTR;
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516 typedef struct EMC_PHY_L1_TIMING_TAG
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518 uint8 data_pad_ie_delay;
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519 uint8 data_pad_oe_delay;
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520 uint8 dqs_gate_pst_delay;
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521 uint8 dqs_gate_pre_delay;
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522 uint8 dqs_ie_delay;
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523 uint8 dqs_oe_delay;
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524 }EMC_PHY_L1_TIMING_T,*EMC_PHY_L1_TIMING_T_PTR;
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526 typedef struct EMC_PHY_L2_TIMING_TAG
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531 uint32 clkwr_dl_3;
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532 uint32 dqs_gate_pre_dl_0;
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533 uint32 dqs_gate_pre_dl_1;
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534 uint32 dqs_gate_pre_dl_2;
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535 uint32 dqs_gate_pre_dl_3;
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536 uint32 dqs_gate_pst_dl_0;
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537 uint32 dqs_gate_pst_dl_1;
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538 uint32 dqs_gate_pst_dl_2;
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539 uint32 dqs_gate_pst_dl_3;
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540 uint32 dqs_in_pos_dl_0;
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541 uint32 dqs_in_pos_dl_1;
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542 uint32 dqs_in_pos_dl_2;
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543 uint32 dqs_in_pos_dl_3;
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544 uint32 dqs_in_neg_dl_0;
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545 uint32 dqs_in_neg_dl_1;
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546 uint32 dqs_in_neg_dl_2;
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547 uint32 dqs_in_neg_dl_3;
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548 }EMC_PHY_L2_TIMING_T,*EMC_PHY_L2_TIMING_T_PTR;
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551 typedef struct EMC_DRM_PARAM_TAG
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553 char chip_name[100];
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554 SDRAM_TIMING_PARA_T time_param;
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555 SDRAM_CFG_INFO_T cfg_info;
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557 EMC_DRM_PARAM_T, *EMC_DRM_PARAM_T_PTR;
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560 typedef struct SDRAM_CHIP_FEATURE_TAG
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562 uint8 cas; // cas latency supported
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563 uint8 bl; // burst length supported
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564 SDRAM_CAP_TYPE_E cap;
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566 SDRAM_CHIP_FEATURE_T, *SDRAM_CHIP_FEATURE_T_PTR;
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571 CHIP_CLK_TYPE_E arm_clk;
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572 EMC_CLK_TYPE_E emc_clk;
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574 DDR_DRIVER_STRENGTH_T ddr_drv; // DDR SDRAM driver strength in mode register
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576 uint8 dqs_drv; //data_qs pin driver strength
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577 uint8 dat_drv; //data pin driver strength
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578 uint8 ctl_drv; //ctrl pin driver strength
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579 uint8 clk_drv; //clock pin driver strength
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581 uint8 clk_wr; // dll clk wr balance
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582 }EMC_PARAM_T, *EMC_PARAM_PTR;
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587 EMC_CHL_NUM_E emc_chl_num;
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588 EMC_CHL_PRI_E axi_chl_wr_pri;
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589 EMC_CHL_PRI_E axi_chl_rd_pri;
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590 EMC_CHL_PRI_E ahb_chl_pri;
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591 }EMC_CHL_INFO_T, *EMC_CHL_INFO_PTR;
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595 /*******************************************************************************
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597 *******************************************************************************/
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599 extern uint32 DRAM_CAP;
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600 //extern uint32 SDRAM_BASE;
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603 /*******************************************************************************
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605 *******************************************************************************/
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608 extern void sdram_init(void);
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