1 /******************************************************************************
2 ** File Name: int_reg_v3.h *
5 ** Copyright: 2008 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 06/14/2008 Yuhua.Shi Create. *
13 ** 05/05/2010 Mingwei.Zhang Modified for SC8800G *
14 ******************************************************************************/
15 #ifndef _INT_REG_V3_H_
16 #define _INT_REG_V3_H_
17 /*----------------------------------------------------------------------------*
19 **-------------------------------------------------------------------------- */
21 /**---------------------------------------------------------------------------*
23 **---------------------------------------------------------------------------*/
28 /**----------------------------------------------------------------------------*
30 **----------------------------------------------------------------------------*/
31 /*----------Interrupt Control Registers----------*/
33 #define INT_IRQ_BASE (INT_REG_BASE + 0x0000)
34 #define INT_IRQ_STS (INT_REG_BASE + 0x0000) //Interrupt status after masked by irq_enable.
35 #define INT_IRQ_RAW_STS (INT_REG_BASE + 0x0004) //Interrupt status from different interrupt source.
36 #define INT_IRQ_EN (INT_REG_BASE + 0x0008) //Enable bits for the corresponding interrupt sources.
37 #define INT_IRQ_DISABLE (INT_REG_BASE + 0x000C)
38 #define INT_IRQ_SOFT (INT_REG_BASE + 0x0010)
39 #define INT_IRQ_TEST_SRC (INT_REG_BASE + 0x0014)
40 #define INT_IRQ_TEST_SEL (INT_REG_BASE + 0x0018)
41 #define INT_IRQ_UINT_STS (INT_REG_BASE + 0x001C)
42 #define INT_FIQ_STS (INT_REG_BASE + 0x0020)
43 #define INT_FIQ_RAW_STS (INT_REG_BASE + 0x0024)
44 #define INT_FIQ_EN (INT_REG_BASE + 0x0028)
45 #define INT_FIQ_DISABLE (INT_REG_BASE + 0x002C)
46 #define INT_FIQ_SOFT (INT_REG_BASE + 0x0030)
47 #define INT_FIQ_TEST_SRC (INT_REG_BASE + 0x0034)
48 #define INT_FIQ_TEST_SEL (INT_REG_BASE + 0x0038)
49 #define INT_UINT_CTL (INT_REG_BASE + 0x003C)
52 #define INTCTL_SPECIAL_LATCH_IRQ BIT_0
53 #define INTCTL_SOFT_IRQ BIT_1
54 #define INTCTL_UART0_IRQ BIT_2
55 #define INTCTL_UART1_IRQ BIT_3
56 #define INTCTL_UART2_IRQ BIT_4
57 #define INTCTL_TIMER0_IRQ BIT_5
58 #define INTCTL_TIMER1_IRQ BIT_6
59 #define INTCTL_TIMER2_IRQ BIT_7
60 #define INTCTL_COMMTX BIT_7
61 #define INTCTL_GPIO_IRQ BIT_8
62 #define INTCTL_SPI_IRQ BIT_9
63 #define INTCTL_KPD_IRQ BIT_10
64 #define INTCTL_I2C_IRQ BIT_11
65 #define INTCTL_SIM0_IRQ BIT_12
66 #define INTCTL_SIM1_IRQ BIT_12
67 #define INTCTL_PIU_SER_INT_IRQ BIT_13
68 #define INTCTL_PIU_CR_HINT_IRQ BIT_14
69 #define INTCTL_DSP_IRQ0 BIT_15
70 #define INTCTL_DSP_IRQ1 BIT_16
71 #define INTCTL_SYST_IRQ BIT_17
72 #define INTCTL_EPT_IRQ BIT_18
73 #define INTCTL_IIS_IRQ BIT_19
74 #define INTCTL_DSP_INT_OR_IRQ BIT_20
75 #define INTCTL_DMA_IRQ BIT_21
76 #define INTCTL_VBC_IRQ BIT_22
77 #define INTCTL_VSP_IRQ BIT_23
78 #define INTCTL_ANA_DIE_IRQ BIT_24
79 #define INTCTL_ADI_IRQ BIT_25
80 #define INTCTL_USB_IRQ BIT_26
81 #define INTCTL_DCAM_IRQ BIT_27
82 #define INTCTL_NFC_IRQ BIT_28
83 #define INTCTL_LCDC_IRQ BIT_29
84 #define INTCTL_DRM_IRQ BIT_30
85 #define INTCTL_SDIO_IRQ BIT_30
86 #define INTCTL_BUS_MON_IRQ BIT_31
87 #define INTCTL_BUS_MON0_IRQ BIT_31
88 #define INTCTL_BUS_MON1_IRQ BIT_31
89 #define INTCTL_COMMRX_IRQ BIT_31
92 #define INTCTL_PCM_IRQ INTCTL_IIS_IRQ
93 #define INTCTL_ICLR_ALL 0xFFFFFFFF
96 /**----------------------------------------------------------------------------*
98 **----------------------------------------------------------------------------*/
100 #ifdef CHIP_ENDIAN_LITTLE
101 typedef union _INT_BIT_U
105 volatile int special_latch :1; //bit 0
106 volatile int soft :1; //BIT_1
107 volatile int uart0 :1; //BIT_2
108 volatile int uart1 :1; //BIT_3
109 volatile int uart2 :1; //BIT_4
110 volatile int timer0 :1; //BIT_5
111 volatile int timer1 :1; //BIT_6
112 volatile int timer2_commtx :1; //BIT_7
113 volatile int gpio :1; //BIT_8
114 volatile int spi :1; //BIT_9
115 volatile int kpd :1; //BIT_10
116 volatile int i2c :1; //BIT_11
117 volatile int sim :1; //BIT_12
118 volatile int piu_ser_int :1; //BIT_13
119 volatile int piu_cr_hint :1; //BIT_14
120 volatile int dsp0 :1; //BIT_15
121 volatile int dsp1 :1; //BIT_16
122 volatile int syst :1; //BIT_17
123 volatile int ept :1; //BIT_18
124 volatile int iis :1; //BIT_19
125 volatile int dsp_int_or :1; //BIT_20
126 volatile int dma :1; //BIT_21
127 volatile int vbc :1; //BIT_22
128 volatile int vsp :1; //BIT_23
129 volatile int ana_die :1; //BIT_24
130 volatile int adi :1; //BIT_25
131 volatile int usb :1; //BIT_26
132 volatile int dcam :1; //BIT_27
133 volatile int nfc :1; //BIT_28
134 volatile int lcdc :1; //BIT_29
135 volatile int sdio_drm :1; //BIT_30
136 volatile int mon_commrx :1; //BIT_31
138 volatile int dwValue ;
143 typedef union _INT_UART_RAW_U
145 struct INT_UART_RAW_MAP
147 volatile int rxd0 :1; //bit 0
148 volatile int ctsn0 :1; //bit 1
149 volatile int rxd1 :1; //bit 2
150 volatile int usbd_se0_wakeup :1; //bit 3
151 volatile int reserved :28;
153 volatile int dwValue ;
157 typedef union _INT_UART_CFG_U
159 struct INT_UART_CFG_MAP
161 volatile int rxd0_en :1; //bit 0
162 volatile int ctsn0_en :1; //bit 1
163 volatile int rxd1_en :1; //bit 2
164 volatile int usbd_se0_en :1; //bit 3
165 volatile int reserved :11; //bit 4-14
166 volatile int clr :1; //bit 15
167 volatile int rxd0_pol :1; //bit 16
168 volatile int ctsn0_pol :1; //bit 17
169 volatile int rxd1_pol :1; //bit 18
170 volatile int usbd_se0_pol :1; //bit 19
171 volatile int reserved_1 :12; //bit 20-31
173 volatile int dwValue ;
176 typedef union _INT_BIT_U
180 volatile int mon_commrx :1; //BIT_31
181 volatile int sdio_drm :1; //BIT_30
182 volatile int lcdc :1; //BIT_29
183 volatile int nfc :1; //BIT_28
184 volatile int dcam :1; //BIT_27
185 volatile int usb :1; //BIT_26
186 volatile int adi :1; //BIT_25
187 volatile int ana_die :1; //BIT_24
188 volatile int vsp :1; //BIT_23
189 volatile int vbc :1; //BIT_22
190 volatile int dma :1; //BIT_21
191 volatile int dsp_int_or :1; //BIT_20
192 volatile int iis :1; //BIT_19
193 volatile int ept :1; //BIT_18
194 volatile int syst :1; //BIT_17
195 volatile int dsp1 :1; //BIT_16
196 volatile int dsp0 :1; //BIT_15
197 volatile int piu_cr_hint :1; //BIT_14
198 volatile int piu_ser_int :1; //BIT_13
199 volatile int sim :1; //BIT_12
200 volatile int i2c :1; //BIT_11
201 volatile int kpd :1; //BIT_10
202 volatile int spi :1; //BIT_9
203 volatile int gpio :1; //BIT_8
204 volatile int timer2_commtx :1; //BIT_7
205 volatile int timer1 :1; //BIT_6
206 volatile int timer0 :1; //BIT_5
207 volatile int uart2 :1; //BIT_4
208 volatile int uart1 :1; //BIT_3
209 volatile int uart0 :1; //BIT_2
210 volatile int soft :1; //BIT_1
211 volatile int special_latch :1; //bit 0
213 volatile int dwValue ;
218 typedef union _INT_UART_RAW_U
220 struct INT_UART_RAW_MAP
222 volatile int reserved :28;
223 volatile int usbd_se0_wakeup :1; //bit 3
224 volatile int rxd1 :1; //bit 2
225 volatile int ctsn0 :1; //bit 1
226 volatile int rxd0 :1; //bit 0
228 volatile int dwValue ;
232 typedef union _INT_UART_CFG_U
234 struct INT_UART_CFG_MAP
236 volatile int reserved_1 :12; //bit 20-31
237 volatile int usbd_se0_pol :1; //bit 19
238 volatile int rxd1_pol :1; //bit 18
239 volatile int ctsn0_pol :1; //bit 17
240 volatile int rxd0_pol :1; //bit 16
241 volatile int clr :1; //bit 15
242 volatile int reserved :11; //bit 4-14
243 volatile int usbd_se0_en :1; //bit 3
244 volatile int rxd1_en :1; //bit 2
245 volatile int ctsn0_en :1; //bit 1
246 volatile int rxd0_en :1; //bit 0
248 volatile int dwValue ;
253 //IRQ Interrupt Control.
254 typedef struct INT_IRQ_S_
256 volatile INT_BIT_U sts;
257 volatile INT_BIT_U raw;
258 volatile INT_BIT_U en;
259 volatile INT_BIT_U clr;
260 volatile INT_BIT_U soft;
261 volatile INT_BIT_U t_src;
262 volatile INT_BIT_U t_sel;
263 volatile INT_UART_RAW_U uart_raw;
264 volatile INT_BIT_U f_sts;
265 volatile INT_BIT_U f_raw;
266 volatile INT_BIT_U f_en;
267 volatile INT_BIT_U f_dis;
268 volatile INT_BIT_U f_soft;
269 volatile INT_BIT_U ft_src;
270 volatile INT_BIT_U ft_sel;
271 volatile INT_UART_CFG_U uart_cfg;
274 //IRQ Interrupt Control.
275 typedef struct int_irq_tag
278 volatile int raw_sts;
284 typedef struct firq_tag
287 volatile int raw_sts;
293 /*----------Analog Die Interupt Status Registers----------*/
295 ///#define ANA_INTC_BASE 0x82000380
296 #define ANA_INT_STATUS (ANA_INTC_BASE + 0x00)
297 #define ANA_INT_RAW (ANA_INTC_BASE + 0x04)
298 #define ANA_INT_EN (ANA_INTC_BASE + 0x08)
300 #define ANA_INT_STATUS_SYNC (ANA_INTC_BASE + 0x0C)
302 #define ANA_MAX_INT_NUM 5
303 //#define ANA_INT_MSK 0x1F
305 #define ANA_TPC_IRQ BIT_4
306 #define ANA_WDG_IRQ BIT_3
307 #define ANA_RTC_IRQ BIT_2
308 #define ANA_GPIO_IRQ BIT_1
309 #define ANA_ADC_IRQ BIT_0
312 /**----------------------------------------------------------------------------*
313 ** Local Function Prototype **
314 **----------------------------------------------------------------------------*/
316 /**----------------------------------------------------------------------------*
317 ** Function Prototype **
318 **----------------------------------------------------------------------------*/
321 /**----------------------------------------------------------------------------*
323 **----------------------------------------------------------------------------*/
327 /**---------------------------------------------------------------------------*/
328 #endif //_INT_REG_V3_H_