2 * (C) Copyright 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifndef __ASM_ARCH_USB_HS_OTG_H_
23 #define __ASM_ARCH_USB_HS_OTG_H_
25 /* Core Global Registers */
26 #define OTG_GOTGCTL 0x000
27 #define OTG_GOTGINT 0x004
28 #define OTG_GAHBCFG 0x008
29 #define OTG_GUSBCFG 0x00C
30 #define OTG_GRSTCTL 0x010
31 #define OTG_GINTSTS 0x014
32 #define OTG_GINTMSK 0x018
33 #define OTG_GRXSTSR 0x01C
34 #define OTG_GRXSTSP 0x020
35 #define OTG_GRXFSIZ 0x024
36 #define OTG_GNPTXFSIZ 0x028
37 #define OTG_GNPTXSTS 0x02C
39 #define OTG_HPTXFSIZ 0x100
40 #define OTG_DPTXFSIZ1 0x104
41 #define OTG_DPTXFSIZ2 0x108
42 #define OTG_DPTXFSIZ3 0x10C
43 #define OTG_DPTXFSIZ4 0x110
44 #define OTG_DPTXFSIZ5 0x114
45 #define OTG_DPTXFSIZ6 0x118
46 #define OTG_DPTXFSIZ7 0x11C
47 #define OTG_DPTXFSIZ8 0x120
48 #define OTG_DPTXFSIZ9 0x124
49 #define OTG_DPTXFSIZ10 0x128
50 #define OTG_DPTXFSIZ11 0x12C
51 #define OTG_DPTXFSIZ12 0x130
52 #define OTG_DPTXFSIZ13 0x134
53 #define OTG_DPTXFSIZ14 0x138
54 #define OTG_DPTXFSIZ15 0x13C
56 /* Host Global Registers */
57 #define OTG_HCFG 0x400
58 #define OTG_HFIR 0x404
59 #define OTG_HFNUM 0x408
60 #define OTG_HPTXSTS 0x410
61 #define OTG_HAINT 0x414
62 #define OTG_HAINTMSK 0x418
64 /* Host Port Control & Status Registers */
65 #define OTG_HPRT 0x440
67 /* Host Channel-Specific Registers */
68 #define OTG_HCCHAR0 0x500
69 #define OTG_HCSPLT0 0x504
70 #define OTG_HCINT0 0x508
71 #define OTG_HCINTMSK0 0x50C
72 #define OTG_HCTSIZ0 0x510
73 #define OTG_HCDMA0 0x514
75 /* Device Global Registers */
76 #define OTG_DCFG 0x800
77 #define OTG_DCTL 0x804
78 #define OTG_DSTS 0x808
79 #define OTG_DIEPMSK 0x810
80 #define OTG_DOEPMSK 0x814
81 #define OTG_DAINT 0x818
82 #define OTG_DAINTMSK 0x81C
83 #define OTG_DTKNQR1 0x820
84 #define OTG_DTKNQR2 0x824
85 #define OTG_DVBUSDIS 0x828
86 #define OTG_DVBUSPULSE 0x82C
87 #define OTG_DTKNQR3 0x830
88 #define OTG_DTKNQR4 0x834
90 /* Device Logical IN Endpoint-Specific Registers */
91 #define OTG_DIEPCTL0 0x900
92 #define OTG_DIEPINT0 0x908
93 #define OTG_DIEPTSIZ0 0x910
94 #define OTG_DIEPDMA0 0x914
96 /* Device Logical OUT Endpoint-Specific Registers */
97 #define OTG_DOEPCTL0 0xB00
98 #define OTG_DOEPINT0 0xB08
99 #define OTG_DOEPTSIZ0 0xB10
100 #define OTG_DOEPDMA0 0xB14
102 /* Power & clock gating registers */
103 #define OTG_PCGCCTRL 0xE00
105 /* Endpoint FIFO address */
106 #define OTG_EP0_FIFO 0x1000
108 /* OTG PHY CORE REGISTERS */
109 #define OTG_PHYPWR 0x0
110 #define OTG_PHYCTRL 0x4
111 #define OTG_RSTCON 0x8
112 #define OTG_PHYTUN0 0x20
113 #define OTG_PHYTUN1 0x24
115 /* register for power control on PMU */
116 static inline unsigned int s5p_get_usb_power_reg(void)
118 if (cpu_is_s5pc100())
120 else if (cpu_is_s5pc110())