2 * (C) Copyright 2009 Samsung Electronics
3 * Hakgoo Lee <goodguy.lee@samsung.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifndef __ASM_ARCH_INTR_H_
23 #define __ASM_ARCH_INTR_H_
25 #define S5P_VIC0_BASE 0xF2000000
26 #define S5P_VIC1_BASE 0xF2100000
27 #define S5P_VIC2_BASE 0xF2200000
28 #define S5P_VIC3_BASE 0xF2300000
30 #define S5P_GPIO_BASE 0xE0200000
33 #define VIC0_IRQ_STATUS (S5P_VIC0_BASE + 0x00)
34 #define VIC0_INT_SELECT (S5P_VIC0_BASE + 0x0C)
35 #define VIC0_INT_ENABLE (S5P_VIC0_BASE + 0x10)
36 #define VIC0_INT_ENCLEAR (S5P_VIC0_BASE + 0x14)
37 #define VIC0_SOFT_INTCLEAR (S5P_VIC0_BASE + 0x1C)
38 #define VIC0_VECT_ADDR (S5P_VIC0_BASE + 0x100)
39 #define VIC0_ADDR (S5P_VIC0_BASE + 0xF00)
41 #define VIC1_IRQ_STATUS (S5P_VIC1_BASE + 0x00)
42 #define VIC1_INT_SELECT (S5P_VIC1_BASE + 0x0C)
43 #define VIC1_INT_ENABLE (S5P_VIC1_BASE + 0x10)
44 #define VIC1_INT_ENCLEAR (S5P_VIC1_BASE + 0x14)
45 #define VIC1_SOFT_INTCLEAR (S5P_VIC1_BASE + 0x1C)
46 #define VIC1_VECT_ADDR (S5P_VIC1_BASE + 0x100)
47 #define VIC1_ADDR (S5P_VIC1_BASE + 0xF00)
49 #define VIC2_IRQ_STATUS (S5P_VIC2_BASE + 0x00)
50 #define VIC2_INT_SELECT (S5P_VIC2_BASE + 0x0C)
51 #define VIC2_INT_ENABLE (S5P_VIC2_BASE + 0x10)
52 #define VIC2_INT_ENCLEAR (S5P_VIC2_BASE + 0x14)
53 #define VIC2_SOFT_INTCLEAR (S5P_VIC2_BASE + 0x1C)
54 #define VIC2_VECT_ADDR (S5P_VIC2_BASE + 0x100)
55 #define VIC2_ADDR (S5P_VIC2_BASE + 0xF00)
57 #define VIC3_IRQ_STATUS (S5P_VIC3_BASE + 0x00)
58 #define VIC3_INT_SELECT (S5P_VIC3_BASE + 0x0C)
59 #define VIC3_INT_ENABLE (S5P_VIC3_BASE + 0x10)
60 #define VIC3_INT_ENCLEAR (S5P_VIC3_BASE + 0x14)
61 #define VIC3_SOFT_INTCLEAR (S5P_VIC3_BASE + 0x1C)
62 #define VIC3_VECT_ADDR (S5P_VIC3_BASE + 0x100)
63 #define VIC3_ADDR (S5P_VIC3_BASE + 0xF00)
66 #define GPH0_CON (S5P_GPIO_BASE + 0xC00)
67 #define GPH1_CON (S5P_GPIO_BASE + 0xC20)
68 #define GPH2_CON (S5P_GPIO_BASE + 0xC40)
69 #define GPH3_CON (S5P_GPIO_BASE + 0xC60)
71 #define EXT_INT0_CON (S5P_GPIO_BASE + 0xE00)
72 #define EXT_INT1_CON (S5P_GPIO_BASE + 0xE04)
73 #define EXT_INT2_CON (S5P_GPIO_BASE + 0xE08)
74 #define EXT_INT3_CON (S5P_GPIO_BASE + 0xE0C)
76 #define EXT_INT0_MASK (S5P_GPIO_BASE + 0xF00)
77 #define EXT_INT1_MASK (S5P_GPIO_BASE + 0xF04)
78 #define EXT_INT2_MASK (S5P_GPIO_BASE + 0xF08)
79 #define EXT_INT3_MASK (S5P_GPIO_BASE + 0xF0C)
81 #define EXT_INT0_PEND (S5P_GPIO_BASE + 0xF40)
82 #define EXT_INT1_PEND (S5P_GPIO_BASE + 0xF44)
83 #define EXT_INT2_PEND (S5P_GPIO_BASE + 0xF48)
84 #define EXT_INT3_PEND (S5P_GPIO_BASE + 0xF4C)
86 #define EXT_INT_CON_LOW 0x0
87 #define EXT_INT_CON_HIGH 0x1
88 #define EXT_INT_CON_FALL 0x2
89 #define EXT_INT_CON_RISE 0x3
90 #define EXT_INT_CON_BOTH 0x4
94 void s5p_gpio_intr_config(u32 num);
95 void s5p_ext_intr_config(u32 num, u8 mode);
96 void s5p_ext_intr_enable(u32 num);
97 void s5p_ext_intr_disable(u32 num);
98 void s5p_ext_intr_clear(u32 num);
99 void s5p_vic_clear_vect_addr(void);
100 u32 s5p_vic_get_irq_num(void);
101 void s5p_vic_set_vect_addr(u32 num, void *handler);
102 void s5p_vic_intr_enable(u32 num);
103 void s5p_vic_intr_disable(u32 num);
104 void s5p_vic_soft_intr_clear(u32 num);
105 void s5p_intr_init(void);