1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015, Freescale Semiconductor, Inc.
6 #ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
7 #define __ARCH_ARM_MACH_S32V234_MMDC_H__
12 #define MMDC_MDCTL 0x0
13 #define MMDC_MDPDC 0x4
14 #define MMDC_MDOTC 0x8
15 #define MMDC_MDCFG0 0xC
16 #define MMDC_MDCFG1 0x10
17 #define MMDC_MDCFG2 0x14
18 #define MMDC_MDMISC 0x18
19 #define MMDC_MDSCR 0x1C
20 #define MMDC_MDREF 0x20
21 #define MMDC_MDRWD 0x2C
22 #define MMDC_MDOR 0x30
23 #define MMDC_MDMRR 0x34
24 #define MMDC_MDCFG3LP 0x38
25 #define MMDC_MDMR4 0x3C
26 #define MMDC_MDASP 0x40
27 #define MMDC_MAARCR 0x400
28 #define MMDC_MAPSR 0x404
29 #define MMDC_MAEXIDR0 0x408
30 #define MMDC_MAEXIDR1 0x40C
31 #define MMDC_MADPCR0 0x410
32 #define MMDC_MADPCR1 0x414
33 #define MMDC_MADPSR0 0x418
34 #define MMDC_MADPSR1 0x41C
35 #define MMDC_MADPSR2 0x420
36 #define MMDC_MADPSR3 0x424
37 #define MMDC_MADPSR4 0x428
38 #define MMDC_MADPSR5 0x42C
39 #define MMDC_MASBS0 0x430
40 #define MMDC_MASBS1 0x434
41 #define MMDC_MAGENP 0x440
42 #define MMDC_MPZQHWCTRL 0x800
43 #define MMDC_MPWLGCR 0x808
44 #define MMDC_MPWLDECTRL0 0x80C
45 #define MMDC_MPWLDECTRL1 0x810
46 #define MMDC_MPWLDLST 0x814
47 #define MMDC_MPODTCTRL 0x818
48 #define MMDC_MPRDDQBY0DL 0x81C
49 #define MMDC_MPRDDQBY1DL 0x820
50 #define MMDC_MPRDDQBY2DL 0x824
51 #define MMDC_MPRDDQBY3DL 0x828
52 #define MMDC_MPDGCTRL0 0x83C
53 #define MMDC_MPDGCTRL1 0x840
54 #define MMDC_MPDGDLST0 0x844
55 #define MMDC_MPRDDLCTL 0x848
56 #define MMDC_MPRDDLST 0x84C
57 #define MMDC_MPWRDLCTL 0x850
58 #define MMDC_MPWRDLST 0x854
59 #define MMDC_MPZQLP2CTL 0x85C
60 #define MMDC_MPRDDLHWCTL 0x860
61 #define MMDC_MPWRDLHWCTL 0x864
62 #define MMDC_MPRDDLHWST0 0x868
63 #define MMDC_MPRDDLHWST1 0x86C
64 #define MMDC_MPWRDLHWST1 0x870
65 #define MMDC_MPWRDLHWST2 0x874
66 #define MMDC_MPWLHWERR 0x878
67 #define MMDC_MPDGHWST0 0x87C
68 #define MMDC_MPDGHWST1 0x880
69 #define MMDC_MPDGHWST2 0x884
70 #define MMDC_MPDGHWST3 0x888
71 #define MMDC_MPPDCMPR1 0x88C
72 #define MMDC_MPPDCMPR2 0x890
73 #define MMDC_MPSWDAR0 0x894
74 #define MMDC_MPSWDRDR0 0x898
75 #define MMDC_MPSWDRDR1 0x89C
76 #define MMDC_MPSWDRDR2 0x8A0
77 #define MMDC_MPSWDRDR3 0x8A4
78 #define MMDC_MPSWDRDR4 0x8A8
79 #define MMDC_MPSWDRDR5 0x8AC
80 #define MMDC_MPSWDRDR6 0x8B0
81 #define MMDC_MPSWDRDR7 0x8B4
82 #define MMDC_MPMUR0 0x8B8
83 #define MMDC_MPDCCR 0x8C0
85 #define MMDC_MPMUR0_FRC_MSR (1 << 11)
86 #define MMDC_MPZQHWCTRL_ZQ_HW_FOR (1 << 16)