1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd
6 #ifndef _ASM_ARCH_SDRAM_COMMON_H
7 #define _ASM_ARCH_SDRAM_COMMON_H
9 struct sdram_cap_info {
11 /* dram column number, 0 means this channel is invalid */
13 /* dram bank number, 3:8bank, 2:4bank */
15 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
17 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
20 * row_3_4 = 1: 6Gb or 12Gb die
21 * row_3_4 = 0: normal die, power of 2
26 unsigned int cs0_high16bit_row;
27 unsigned int cs1_high16bit_row;
28 unsigned int ddrconfig;
31 struct sdram_base_params {
32 unsigned int ddr_freq;
33 unsigned int dramtype;
34 unsigned int num_channels;
39 #if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
40 inline void sdram_print_dram_type(unsigned char dramtype)
44 inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
45 struct sdram_base_params *base)
49 inline void sdram_print_stride(unsigned int stride)
53 void sdram_print_dram_type(unsigned char dramtype);
54 void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
55 struct sdram_base_params *base);
56 void sdram_print_stride(unsigned int stride);
57 #endif /* CONFIG_RAM_ROCKCHIP_DEBUG */