arch/arm/include/asm/arch-rockchip/grf_rv1108.h

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_GRF_RV1108_H
   7 #define _ASM_ARCH_GRF_RV1108_H
   8
   9 #include <common.h>
  10
  11 struct rv1108_grf {
  12         u32 reserved[4];
  13         u32 gpio1a_iomux;
  14         u32 gpio1b_iomux;
  15         u32 gpio1c_iomux;
  16         u32 gpio1d_iomux;
  17         u32 gpio2a_iomux;
  18         u32 gpio2b_iomux;
  19         u32 gpio2c_iomux;
  20         u32 gpio2d_iomux;
  21         u32 gpio3a_iomux;
  22         u32 gpio3b_iomux;
  23         u32 gpio3c_iomux;
  24         u32 gpio3d_iomux;
  25         u32 reserved1[52];
  26         u32 gpio1a_pull;
  27         u32 gpio1b_pull;
  28         u32 gpio1c_pull;
  29         u32 gpio1d_pull;
  30         u32 gpio2a_pull;
  31         u32 gpio2b_pull;
  32         u32 gpio2c_pull;
  33         u32 gpio2d_pull;
  34         u32 gpio3a_pull;
  35         u32 gpio3b_pull;
  36         u32 gpio3c_pull;
  37         u32 gpio3d_pull;
  38         u32 reserved2[52];
  39         u32 gpio1a_drv;
  40         u32 gpio1b_drv;
  41         u32 gpio1c_drv;
  42         u32 gpio1d_drv;
  43         u32 gpio2a_drv;
  44         u32 gpio2b_drv;
  45         u32 gpio2c_drv;
  46         u32 gpio2d_drv;
  47         u32 gpio3a_drv;
  48         u32 gpio3b_drv;
  49         u32 gpio3c_drv;
  50         u32 gpio3d_drv;
  51         u32 reserved3[50];
  52         u32 gpio1l_sr;
  53         u32 gpio1h_sr;
  54         u32 gpio2l_sr;
  55         u32 gpio2h_sr;
  56         u32 gpio3l_sr;
  57         u32 gpio3h_sr;
  58         u32 reserved4[26];
  59         u32 gpio1l_smt;
  60         u32 gpio1h_smt;
  61         u32 gpio2l_smt;
  62         u32 gpio2h_smt;
  63         u32 gpio3l_smt;
  64         u32 gpio3h_smt;
  65         u32 reserved5[24];
  66         u32 soc_con0;
  67         u32 soc_con1;
  68         u32 soc_con2;
  69         u32 soc_con3;
  70         u32 soc_con4;
  71         u32 soc_con5;
  72         u32 soc_con6;
  73         u32 soc_con7;
  74         u32 soc_con8;
  75         u32 soc_con9;
  76         u32 soc_con10;
  77         u32 soc_con11;
  78         u32 reserved6[20];
  79         u32 soc_status0;
  80         u32 soc_status1;
  81         u32 reserved7[30];
  82         u32 cpu_con0;
  83         u32 cpu_con1;
  84         u32 reserved8[30];
  85         u32 os_reg0;
  86         u32 os_reg1;
  87         u32 os_reg2;
  88         u32 os_reg3;
  89         u32 reserved9[29];
  90         u32 ddr_status;
  91         u32 reserved10[30];
  92         u32 sig_det_con;
  93         u32 reserved11[3];
  94         u32 sig_det_status;
  95         u32 reserved12[3];
  96         u32 sig_det_clr;
  97         u32 reserved13[23];
  98         u32 host_con0;
  99         u32 host_con1;
 100         u32 reserved14[2];
 101         u32 dma_con0;
 102         u32 dma_con1;
 103         u32 reserved15[539];
 104         u32 uoc_status;
 105         u32 host_status;
 106         u32 gmac_con0;
 107         u32 chip_id;
 108 };
 109 check_member(rv1108_grf, chip_id, 0xf90);
 110
 111 /* GRF_GPIO1B_IOMUX */
 112 enum {
 113         GPIO1B7_SHIFT           = 14,
 114         GPIO1B7_MASK            = 3 << GPIO1B7_SHIFT,
 115         GPIO1B7_GPIO            = 0,
 116         GPIO1B7_LCDC_D12,
 117         GPIO1B7_I2S_SDIO2_M0,
 118         GPIO1B7_GMAC_RXDV,
 119
 120         GPIO1B6_SHIFT           = 12,
 121         GPIO1B6_MASK            = 3 << GPIO1B6_SHIFT,
 122         GPIO1B6_GPIO            = 0,
 123         GPIO1B6_LCDC_D13,
 124         GPIO1B6_I2S_LRCLKTX_M0,
 125         GPIO1B6_GMAC_RXD1,
 126
 127         GPIO1B5_SHIFT           = 10,
 128         GPIO1B5_MASK            = 3 << GPIO1B5_SHIFT,
 129         GPIO1B5_GPIO            = 0,
 130         GPIO1B5_LCDC_D14,
 131         GPIO1B5_I2S_SDIO1_M0,
 132         GPIO1B5_GMAC_RXD0,
 133
 134         GPIO1B4_SHIFT           = 8,
 135         GPIO1B4_MASK            = 3 << GPIO1B4_SHIFT,
 136         GPIO1B4_GPIO            = 0,
 137         GPIO1B4_LCDC_D15,
 138         GPIO1B4_I2S_MCLK_M0,
 139         GPIO1B4_GMAC_TXEN,
 140
 141         GPIO1B3_SHIFT           = 6,
 142         GPIO1B3_MASK            = 3 << GPIO1B3_SHIFT,
 143         GPIO1B3_GPIO            = 0,
 144         GPIO1B3_LCDC_D16,
 145         GPIO1B3_I2S_SCLK_M0,
 146         GPIO1B3_GMAC_TXD1,
 147
 148         GPIO1B2_SHIFT           = 4,
 149         GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
 150         GPIO1B2_GPIO            = 0,
 151         GPIO1B2_LCDC_D17,
 152         GPIO1B2_I2S_SDIO_M0,
 153         GPIO1B2_GMAC_TXD0,
 154
 155         GPIO1B1_SHIFT           = 2,
 156         GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
 157         GPIO1B1_GPIO            = 0,
 158         GPIO1B1_LCDC_D9,
 159         GPIO1B1_PWM7,
 160
 161         GPIO1B0_SHIFT           = 0,
 162         GPIO1B0_MASK            = 3,
 163         GPIO1B0_GPIO            = 0,
 164         GPIO1B0_LCDC_D8,
 165         GPIO1B0_PWM6,
 166 };
 167
 168 /* GRF_GPIO1C_IOMUX */
 169 enum {
 170         GPIO1C7_SHIFT           = 14,
 171         GPIO1C7_MASK            = 3 << GPIO1C7_SHIFT,
 172         GPIO1C7_GPIO            = 0,
 173         GPIO1C7_CIF_D5,
 174         GPIO1C7_I2S_SDIO2_M1,
 175
 176         GPIO1C6_SHIFT           = 12,
 177         GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
 178         GPIO1C6_GPIO            = 0,
 179         GPIO1C6_CIF_D4,
 180         GPIO1C6_I2S_LRCLKTX_M1,
 181
 182         GPIO1C5_SHIFT           = 10,
 183         GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
 184         GPIO1C5_GPIO            = 0,
 185         GPIO1C5_LCDC_CLK,
 186         GPIO1C5_GMAC_CLK,
 187
 188         GPIO1C4_SHIFT           = 8,
 189         GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
 190         GPIO1C4_GPIO            = 0,
 191         GPIO1C4_LCDC_HSYNC,
 192         GPIO1C4_GMAC_MDC,
 193
 194         GPIO1C3_SHIFT           = 6,
 195         GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
 196         GPIO1C3_GPIO            = 0,
 197         GPIO1C3_LCDC_VSYNC,
 198         GPIO1C3_GMAC_MDIO,
 199
 200         GPIO1C2_SHIFT           = 4,
 201         GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT,
 202         GPIO1C2_GPIO            = 0,
 203         GPIO1C2_LCDC_EN,
 204         GPIO1C2_I2S_SDIO3_M0,
 205         GPIO1C2_GMAC_RXER,
 206
 207         GPIO1C1_SHIFT           = 2,
 208         GPIO1C1_MASK            = 3 << GPIO1C1_SHIFT,
 209         GPIO1C1_GPIO            = 0,
 210         GPIO1C1_LCDC_D10,
 211         GPIO1C1_I2S_SDI_M0,
 212         GPIO1C1_PWM4,
 213
 214         GPIO1C0_SHIFT           = 0,
 215         GPIO1C0_MASK            = 3,
 216         GPIO1C0_GPIO            = 0,
 217         GPIO1C0_LCDC_D11,
 218         GPIO1C0_I2S_LRCLKRX_M0,
 219 };
 220
 221 /* GRF_GPIO1D_OIMUX */
 222 enum {
 223         GPIO1D7_SHIFT           = 14,
 224         GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
 225         GPIO1D7_GPIO            = 0,
 226         GPIO1D7_HDMI_CEC,
 227         GPIO1D7_DSP_RTCK,
 228
 229         GPIO1D6_SHIFT           = 12,
 230         GPIO1D6_MASK            = 1 << GPIO1D6_SHIFT,
 231         GPIO1D6_GPIO            = 0,
 232         GPIO1D6_HDMI_HPD_M0,
 233
 234         GPIO1D5_SHIFT           = 10,
 235         GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
 236         GPIO1D5_GPIO            = 0,
 237         GPIO1D5_UART2_RTSN,
 238         GPIO1D5_HDMI_SDA_M0,
 239
 240         GPIO1D4_SHIFT           = 8,
 241         GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
 242         GPIO1D4_GPIO            = 0,
 243         GPIO1D4_UART2_CTSN,
 244         GPIO1D4_HDMI_SCL_M0,
 245
 246         GPIO1D3_SHIFT           = 6,
 247         GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
 248         GPIO1D3_GPIO            = 0,
 249         GPIO1D3_UART0_SOUT,
 250         GPIO1D3_SPI_TXD_M0,
 251
 252         GPIO1D2_SHIFT           = 4,
 253         GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
 254         GPIO1D2_GPIO            = 0,
 255         GPIO1D2_UART0_SIN,
 256         GPIO1D2_SPI_RXD_M0,
 257         GPIO1D2_DSP_TDI,
 258
 259         GPIO1D1_SHIFT           = 2,
 260         GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
 261         GPIO1D1_GPIO            = 0,
 262         GPIO1D1_UART0_RTSN,
 263         GPIO1D1_SPI_CSN0_M0,
 264         GPIO1D1_DSP_TMS,
 265
 266         GPIO1D0_SHIFT           = 0,
 267         GPIO1D0_MASK            = 3,
 268         GPIO1D0_GPIO            = 0,
 269         GPIO1D0_UART0_CTSN,
 270         GPIO1D0_SPI_CLK_M0,
 271         GPIO1D0_DSP_TCK,
 272 };
 273
 274 /* GRF_GPIO2A_IOMUX */
 275 enum {
 276         GPIO2A7_SHIFT           = 14,
 277         GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
 278         GPIO2A7_GPIO            = 0,
 279         GPIO2A7_FLASH_D7,
 280         GPIO2A7_EMMC_D7,
 281
 282         GPIO2A6_SHIFT           = 12,
 283         GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
 284         GPIO2A6_GPIO            = 0,
 285         GPIO2A6_FLASH_D6,
 286         GPIO2A6_EMMC_D6,
 287
 288         GPIO2A5_SHIFT           = 10,
 289         GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
 290         GPIO2A5_GPIO            = 0,
 291         GPIO2A5_FLASH_D5,
 292         GPIO2A5_EMMC_D5,
 293
 294         GPIO2A4_SHIFT           = 8,
 295         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 296         GPIO2A4_GPIO            = 0,
 297         GPIO2A4_FLASH_D4,
 298         GPIO2A4_EMMC_D4,
 299
 300         GPIO2A3_SHIFT           = 6,
 301         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 302         GPIO2A3_GPIO            = 0,
 303         GPIO2A3_FLASH_D3,
 304         GPIO2A3_EMMC_D3,
 305         GPIO2A3_SFC_HOLD_IO3,
 306
 307         GPIO2A2_SHIFT           = 4,
 308         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 309         GPIO2A2_GPIO            = 0,
 310         GPIO2A2_FLASH_D2,
 311         GPIO2A2_EMMC_D2,
 312         GPIO2A2_SFC_WP_IO2,
 313
 314         GPIO2A1_SHIFT           = 2,
 315         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 316         GPIO2A1_GPIO            = 0,
 317         GPIO2A1_FLASH_D1,
 318         GPIO2A1_EMMC_D1,
 319         GPIO2A1_SFC_SO_IO1,
 320
 321         GPIO2A0_SHIFT           = 0,
 322         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 323         GPIO2A0_GPIO            = 0,
 324         GPIO2A0_FLASH_D0,
 325         GPIO2A0_EMMC_D0,
 326         GPIO2A0_SFC_SI_IO0,
 327 };
 328
 329 /* GRF_GPIO2D_IOMUX */
 330 enum {
 331         GPIO2B7_SHIFT           = 14,
 332         GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
 333         GPIO2B7_GPIO            = 0,
 334         GPIO2B7_FLASH_CS1,
 335         GPIO2B7_SFC_CLK,
 336
 337         GPIO2B6_SHIFT           = 12,
 338         GPIO2B6_MASK            = 1 << GPIO2B6_SHIFT,
 339         GPIO2B6_GPIO            = 0,
 340         GPIO2B6_EMMC_CLKO,
 341
 342         GPIO2B5_SHIFT           = 10,
 343         GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
 344         GPIO2B5_GPIO            = 0,
 345         GPIO2B5_FLASH_CS0,
 346
 347         GPIO2B4_SHIFT           = 8,
 348         GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
 349         GPIO2B4_GPIO            = 0,
 350         GPIO2B4_FLASH_RDY,
 351         GPIO2B4_EMMC_CMD,
 352         GPIO2B4_SFC_CSN0,
 353
 354         GPIO2B3_SHIFT           = 6,
 355         GPIO2B3_MASK            = 1 << GPIO2B3_SHIFT,
 356         GPIO2B3_GPIO            = 0,
 357         GPIO2B3_FLASH_RDN,
 358
 359         GPIO2B2_SHIFT           = 4,
 360         GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
 361         GPIO2B2_GPIO            = 0,
 362         GPIO2B2_FLASH_WRN,
 363
 364         GPIO2B1_SHIFT           = 2,
 365         GPIO2B1_MASK            = 1 << GPIO2B1_SHIFT,
 366         GPIO2B1_GPIO            = 0,
 367         GPIO2B1_FLASH_CLE,
 368
 369         GPIO2B0_SHIFT           = 0,
 370         GPIO2B0_MASK            = 1 << GPIO2B0_SHIFT,
 371         GPIO2B0_GPIO            = 0,
 372         GPIO2B0_FLASH_ALE,
 373 };
 374
 375 /* GRF_GPIO2D_IOMUX */
 376 enum {
 377         GPIO2D7_SHIFT           = 14,
 378         GPIO2D7_MASK            = 1 << GPIO2D7_SHIFT,
 379         GPIO2D7_GPIO            = 0,
 380         GPIO2D7_SDIO_D0,
 381
 382         GPIO2D6_SHIFT           = 12,
 383         GPIO2D6_MASK            = 1 << GPIO2D6_SHIFT,
 384         GPIO2D6_GPIO            = 0,
 385         GPIO2D6_SDIO_CMD,
 386
 387         GPIO2D5_SHIFT           = 10,
 388         GPIO2D5_MASK            = 1 << GPIO2D5_SHIFT,
 389         GPIO2D5_GPIO            = 0,
 390         GPIO2D5_SDIO_CLKO,
 391
 392         GPIO2D4_SHIFT           = 8,
 393         GPIO2D4_MASK            = 1 << GPIO2D4_SHIFT,
 394         GPIO2D4_GPIO            = 0,
 395         GPIO2D4_I2C1_SCL,
 396
 397         GPIO2D3_SHIFT           = 6,
 398         GPIO2D3_MASK            = 1 << GPIO2D3_SHIFT,
 399         GPIO2D3_GPIO            = 0,
 400         GPIO2D3_I2C1_SDA,
 401
 402         GPIO2D2_SHIFT           = 4,
 403         GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
 404         GPIO2D2_GPIO            = 0,
 405         GPIO2D2_UART2_SOUT_M0,
 406         GPIO2D2_JTAG_TCK,
 407
 408         GPIO2D1_SHIFT           = 2,
 409         GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
 410         GPIO2D1_GPIO            = 0,
 411         GPIO2D1_UART2_SIN_M0,
 412         GPIO2D1_JTAG_TMS,
 413         GPIO2D1_DSP_TMS,
 414
 415         GPIO2D0_SHIFT           = 0,
 416         GPIO2D0_MASK            = 3,
 417         GPIO2D0_GPIO            = 0,
 418         GPIO2D0_UART0_CTSN,
 419         GPIO2D0_SPI_CLK_M0,
 420         GPIO2D0_DSP_TCK,
 421 };
 422
 423 /* GRF_GPIO3A_IOMUX */
 424 enum {
 425         GPIO3A7_SHIFT           = 14,
 426         GPIO3A7_MASK            = 1 << GPIO3A7_SHIFT,
 427         GPIO3A7_GPIO            = 0,
 428
 429         GPIO3A6_SHIFT           = 12,
 430         GPIO3A6_MASK            = 1 << GPIO3A6_SHIFT,
 431         GPIO3A6_GPIO            = 0,
 432         GPIO3A6_UART1_SOUT,
 433
 434         GPIO3A5_SHIFT           = 10,
 435         GPIO3A5_MASK            = 1 << GPIO3A5_SHIFT,
 436         GPIO3A5_GPIO            = 0,
 437         GPIO3A5_UART1_SIN,
 438
 439         GPIO3A4_SHIFT           = 8,
 440         GPIO3A4_MASK            = 1 << GPIO3A4_SHIFT,
 441         GPIO3A4_GPIO            = 0,
 442         GPIO3A4_UART1_CTSN,
 443
 444         GPIO3A3_SHIFT           = 6,
 445         GPIO3A3_MASK            = 1 << GPIO3A3_SHIFT,
 446         GPIO3A3_GPIO            = 0,
 447         GPIO3A3_UART1_RTSN,
 448
 449         GPIO3A2_SHIFT           = 4,
 450         GPIO3A2_MASK            = 1 << GPIO3A2_SHIFT,
 451         GPIO3A2_GPIO            = 0,
 452         GPIO3A2_SDIO_D3,
 453
 454         GPIO3A1_SHIFT           = 2,
 455         GPIO3A1_MASK            = 1 << GPIO3A1_SHIFT,
 456         GPIO3A1_GPIO            = 0,
 457         GPIO3A1_SDIO_D2,
 458
 459         GPIO3A0_SHIFT           = 0,
 460         GPIO3A0_MASK            = 1,
 461         GPIO3A0_GPIO            = 0,
 462         GPIO3A0_SDIO_D1,
 463 };
 464
 465 /* GRF_GPIO3C_IOMUX */
 466 enum {
 467         GPIO3C7_SHIFT           = 14,
 468         GPIO3C7_MASK            = 1 << GPIO3C7_SHIFT,
 469         GPIO3C7_GPIO            = 0,
 470         GPIO3C7_CIF_CLKI,
 471
 472         GPIO3C6_SHIFT           = 12,
 473         GPIO3C6_MASK            = 1 << GPIO3C6_SHIFT,
 474         GPIO3C6_GPIO            = 0,
 475         GPIO3C6_CIF_VSYNC,
 476
 477         GPIO3C5_SHIFT           = 10,
 478         GPIO3C5_MASK            = 1 << GPIO3C5_SHIFT,
 479         GPIO3C5_GPIO            = 0,
 480         GPIO3C5_SDMMC_CMD,
 481
 482         GPIO3C4_SHIFT           = 8,
 483         GPIO3C4_MASK            = 1 << GPIO3C4_SHIFT,
 484         GPIO3C4_GPIO            = 0,
 485         GPIO3C4_SDMMC_CLKO,
 486
 487         GPIO3C3_SHIFT           = 6,
 488         GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
 489         GPIO3C3_GPIO            = 0,
 490         GPIO3C3_SDMMC_D0,
 491         GPIO3C3_UART2_SOUT_M1,
 492
 493         GPIO3C2_SHIFT           = 4,
 494         GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
 495         GPIO3C2_GPIO            = 0,
 496         GPIO3C2_SDMMC_D1,
 497         GPIO3C2_UART2_SIN_M1,
 498
 499         GPIOC1_SHIFT            = 2,
 500         GPIOC1_MASK             = 1 << GPIOC1_SHIFT,
 501         GPIOC1_GPIO             = 0,
 502         GPIOC1_SDMMC_D2,
 503
 504         GPIOC0_SHIFT            = 0,
 505         GPIOC0_MASK             = 1,
 506         GPIO3C0_GPIO            = 0,
 507         GPIO3C0_SDMMC_D3,
 508 };
 509 #endif