arch/arm/include/asm/arch-rockchip/grf_rk3036.h

   1 /*
   2  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_GRF_RK3036_H
   7 #define _ASM_ARCH_GRF_RK3036_H
   8
   9 #include <common.h>
  10
  11 struct rk3036_grf {
  12         unsigned int reserved[0x2a];
  13         unsigned int gpio0a_iomux;
  14         unsigned int gpio0b_iomux;
  15         unsigned int gpio0c_iomux;
  16         unsigned int gpio0d_iomux;
  17
  18         unsigned int gpio1a_iomux;
  19         unsigned int gpio1b_iomux;
  20         unsigned int gpio1c_iomux;
  21         unsigned int gpio1d_iomux;
  22
  23         unsigned int gpio2a_iomux;
  24         unsigned int gpio2b_iomux;
  25         unsigned int gpio2c_iomux;
  26         unsigned int gpio2d_iomux;
  27
  28         unsigned int reserved2[0x0a];
  29         unsigned int gpiods;
  30         unsigned int reserved3[0x05];
  31         unsigned int gpio0l_pull;
  32         unsigned int gpio0h_pull;
  33         unsigned int gpio1l_pull;
  34         unsigned int gpio1h_pull;
  35         unsigned int gpio2l_pull;
  36         unsigned int gpio2h_pull;
  37         unsigned int reserved4[4];
  38         unsigned int soc_con0;
  39         unsigned int soc_con1;
  40         unsigned int soc_con2;
  41         unsigned int soc_status0;
  42         unsigned int reserved5;
  43         unsigned int soc_con3;
  44         unsigned int reserved6;
  45         unsigned int dmac_con0;
  46         unsigned int dmac_con1;
  47         unsigned int dmac_con2;
  48         unsigned int reserved7[5];
  49         unsigned int uoc0_con5;
  50         unsigned int reserved8[4];
  51         unsigned int uoc1_con4;
  52         unsigned int uoc1_con5;
  53         unsigned int reserved9;
  54         unsigned int ddrc_stat;
  55         unsigned int uoc_con6;
  56         unsigned int soc_status1;
  57         unsigned int cpu_con0;
  58         unsigned int cpu_con1;
  59         unsigned int cpu_con2;
  60         unsigned int cpu_con3;
  61         unsigned int reserved10;
  62         unsigned int reserved11;
  63         unsigned int cpu_status0;
  64         unsigned int cpu_status1;
  65         unsigned int os_reg[8];
  66         unsigned int reserved12[6];
  67         unsigned int dll_con[4];
  68         unsigned int dll_status[4];
  69         unsigned int dfi_wrnum;
  70         unsigned int dfi_rdnum;
  71         unsigned int dfi_actnum;
  72         unsigned int dfi_timerval;
  73         unsigned int nfi_fifo[4];
  74         unsigned int reserved13[0x10];
  75         unsigned int usbphy0_con[8];
  76         unsigned int usbphy1_con[8];
  77         unsigned int reserved14[0x10];
  78         unsigned int chip_tag;
  79         unsigned int sdmmc_det_cnt;
  80 };
  81 check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
  82
  83 /* GRF_GPIO0A_IOMUX */
  84 enum {
  85         GPIO0A3_SHIFT           = 6,
  86         GPIO0A3_MASK            = 1,
  87         GPIO0A3_GPIO            = 0,
  88         GPIO0A3_I2C1_SDA,
  89
  90         GPIO0A2_SHIFT           = 4,
  91         GPIO0A2_MASK            = 1,
  92         GPIO0A2_GPIO            = 0,
  93         GPIO0A2_I2C1_SCL,
  94
  95         GPIO0A1_SHIFT           = 2,
  96         GPIO0A1_MASK            = 3,
  97         GPIO0A1_GPIO            = 0,
  98         GPIO0A1_I2C0_SDA,
  99         GPIO0A1_PWM2,
 100
 101         GPIO0A0_SHIFT           = 0,
 102         GPIO0A0_MASK            = 3,
 103         GPIO0A0_GPIO            = 0,
 104         GPIO0A0_I2C0_SCL,
 105         GPIO0A0_PWM1,
 106
 107 };
 108
 109 /* GRF_GPIO0B_IOMUX */
 110 enum {
 111         GPIO0B6_SHIFT           = 12,
 112         GPIO0B6_MASK            = 3,
 113         GPIO0B6_GPIO            = 0,
 114         GPIO0B6_MMC1_D3,
 115         GPIO0B6_I2S1_SCLK,
 116
 117         GPIO0B5_SHIFT           = 10,
 118         GPIO0B5_MASK            = 3,
 119         GPIO0B5_GPIO            = 0,
 120         GPIO0B5_MMC1_D2,
 121         GPIO0B5_I2S1_SDI,
 122
 123         GPIO0B4_SHIFT           = 8,
 124         GPIO0B4_MASK            = 3,
 125         GPIO0B4_GPIO            = 0,
 126         GPIO0B4_MMC1_D1,
 127         GPIO0B4_I2S1_LRCKTX,
 128
 129         GPIO0B3_SHIFT           = 6,
 130         GPIO0B3_MASK            = 3,
 131         GPIO0B3_GPIO            = 0,
 132         GPIO0B3_MMC1_D0,
 133         GPIO0B3_I2S1_LRCKRX,
 134
 135         GPIO0B1_SHIFT           = 2,
 136         GPIO0B1_MASK            = 3,
 137         GPIO0B1_GPIO            = 0,
 138         GPIO0B1_MMC1_CLKOUT,
 139         GPIO0B1_I2S1_MCLK,
 140
 141         GPIO0B0_SHIFT           = 0,
 142         GPIO0B0_MASK            = 3,
 143         GPIO0B0_GPIO            = 0,
 144         GPIO0B0_MMC1_CMD,
 145         GPIO0B0_I2S1_SDO,
 146 };
 147
 148 /* GRF_GPIO0C_IOMUX */
 149 enum {
 150         GPIO0C4_SHIFT           = 8,
 151         GPIO0C4_MASK            = 1,
 152         GPIO0C4_GPIO            = 0,
 153         GPIO0C4_DRIVE_VBUS,
 154
 155         GPIO0C3_SHIFT           = 6,
 156         GPIO0C3_MASK            = 1,
 157         GPIO0C3_GPIO            = 0,
 158         GPIO0C3_UART0_CTSN,
 159
 160         GPIO0C2_SHIFT           = 4,
 161         GPIO0C2_MASK            = 1,
 162         GPIO0C2_GPIO            = 0,
 163         GPIO0C2_UART0_RTSN,
 164
 165         GPIO0C1_SHIFT           = 2,
 166         GPIO0C1_MASK            = 1,
 167         GPIO0C1_GPIO            = 0,
 168         GPIO0C1_UART0_SIN,
 169
 170
 171         GPIO0C0_SHIFT           = 0,
 172         GPIO0C0_MASK            = 1,
 173         GPIO0C0_GPIO            = 0,
 174         GPIO0C0_UART0_SOUT,
 175 };
 176
 177 /* GRF_GPIO0D_IOMUX */
 178 enum {
 179         GPIO0D4_SHIFT           = 8,
 180         GPIO0D4_MASK            = 1,
 181         GPIO0D4_GPIO            = 0,
 182         GPIO0D4_SPDIF,
 183
 184         GPIO0D3_SHIFT           = 6,
 185         GPIO0D3_MASK            = 1,
 186         GPIO0D3_GPIO            = 0,
 187         GPIO0D3_PWM3,
 188
 189         GPIO0D2_SHIFT           = 4,
 190         GPIO0D2_MASK            = 1,
 191         GPIO0D2_GPIO            = 0,
 192         GPIO0D2_PWM0,
 193 };
 194
 195 /* GRF_GPIO1A_IOMUX */
 196 enum {
 197         GPIO1A5_SHIFT           = 10,
 198         GPIO1A5_MASK            = 1,
 199         GPIO1A5_GPIO            = 0,
 200         GPIO1A5_I2S_SDI,
 201
 202         GPIO1A4_SHIFT           = 8,
 203         GPIO1A4_MASK            = 1,
 204         GPIO1A4_GPIO            = 0,
 205         GPIO1A4_I2S_SD0,
 206
 207         GPIO1A3_SHIFT           = 6,
 208         GPIO1A3_MASK            = 1,
 209         GPIO1A3_GPIO            = 0,
 210         GPIO1A3_I2S_LRCKTX,
 211
 212         GPIO1A2_SHIFT           = 4,
 213         GPIO1A2_MASK            = 6,
 214         GPIO1A2_GPIO            = 0,
 215         GPIO1A2_I2S_LRCKRX,
 216         GPIO1A2_I2S_PWM1_0,
 217
 218         GPIO1A1_SHIFT           = 2,
 219         GPIO1A1_MASK            = 1,
 220         GPIO1A1_GPIO            = 0,
 221         GPIO1A1_I2S_SCLK,
 222
 223         GPIO1A0_SHIFT           = 0,
 224         GPIO1A0_MASK            = 1,
 225         GPIO1A0_GPIO            = 0,
 226         GPIO1A0_I2S_MCLK,
 227
 228 };
 229
 230 /* GRF_GPIO1B_IOMUX */
 231 enum {
 232         GPIO1B7_SHIFT           = 14,
 233         GPIO1B7_MASK            = 1,
 234         GPIO1B7_GPIO            = 0,
 235         GPIO1B7_MMC0_CMD,
 236
 237         GPIO1B3_SHIFT           = 6,
 238         GPIO1B3_MASK            = 1,
 239         GPIO1B3_GPIO            = 0,
 240         GPIO1B3_HDMI_HPD,
 241
 242         GPIO1B2_SHIFT           = 4,
 243         GPIO1B2_MASK            = 1,
 244         GPIO1B2_GPIO            = 0,
 245         GPIO1B2_HDMI_SCL,
 246
 247         GPIO1B1_SHIFT           = 2,
 248         GPIO1B1_MASK            = 1,
 249         GPIO1B1_GPIO            = 0,
 250         GPIO1B1_HDMI_SDA,
 251
 252         GPIO1B0_SHIFT           = 0,
 253         GPIO1B0_MASK            = 1,
 254         GPIO1B0_GPIO            = 0,
 255         GPIO1B0_HDMI_CEC,
 256 };
 257
 258 /* GRF_GPIO1C_IOMUX */
 259 enum {
 260         GPIO1C5_SHIFT           = 10,
 261         GPIO1C5_MASK            = 3,
 262         GPIO1C5_GPIO            = 0,
 263         GPIO1C5_MMC0_D3,
 264         GPIO1C5_JTAG_TMS,
 265
 266         GPIO1C4_SHIFT           = 8,
 267         GPIO1C4_MASK            = 3,
 268         GPIO1C4_GPIO            = 0,
 269         GPIO1C4_MMC0_D2,
 270         GPIO1C4_JTAG_TCK,
 271
 272         GPIO1C3_SHIFT           = 6,
 273         GPIO1C3_MASK            = 3,
 274         GPIO1C3_GPIO            = 0,
 275         GPIO1C3_MMC0_D1,
 276         GPIO1C3_UART2_SOUT,
 277
 278         GPIO1C2_SHIFT           = 4,
 279         GPIO1C2_MASK            = 3,
 280         GPIO1C2_GPIO            = 0,
 281         GPIO1C2_MMC0_D0,
 282         GPIO1C2_UART2_SIN,
 283
 284         GPIO1C1_SHIFT           = 2,
 285         GPIO1C1_MASK            = 1,
 286         GPIO1C1_GPIO            = 0,
 287         GPIO1C1_MMC0_DETN,
 288
 289         GPIO1C0_SHIFT           = 0,
 290         GPIO1C0_MASK            = 1,
 291         GPIO1C0_GPIO            = 0,
 292         GPIO1C0_MMC0_CLKOUT,
 293 };
 294
 295 /* GRF_GPIO1D_IOMUX */
 296 enum {
 297         GPIO1D7_SHIFT           = 14,
 298         GPIO1D7_MASK            = 3,
 299         GPIO1D7_GPIO            = 0,
 300         GPIO1D7_NAND_D7,
 301         GPIO1D7_EMMC_D7,
 302         GPIO1D7_SPI_CSN1,
 303
 304         GPIO1D6_SHIFT           = 12,
 305         GPIO1D6_MASK            = 3,
 306         GPIO1D6_GPIO            = 0,
 307         GPIO1D6_NAND_D6,
 308         GPIO1D6_EMMC_D6,
 309         GPIO1D6_SPI_CSN0,
 310
 311         GPIO1D5_SHIFT           = 10,
 312         GPIO1D5_MASK            = 3,
 313         GPIO1D5_GPIO            = 0,
 314         GPIO1D5_NAND_D5,
 315         GPIO1D5_EMMC_D5,
 316         GPIO1D5_SPI_TXD,
 317
 318         GPIO1D4_SHIFT           = 8,
 319         GPIO1D4_MASK            = 3,
 320         GPIO1D4_GPIO            = 0,
 321         GPIO1D4_NAND_D4,
 322         GPIO1D4_EMMC_D4,
 323         GPIO1D4_SPI_RXD,
 324
 325         GPIO1D3_SHIFT           = 6,
 326         GPIO1D3_MASK            = 3,
 327         GPIO1D3_GPIO            = 0,
 328         GPIO1D3_NAND_D3,
 329         GPIO1D3_EMMC_D3,
 330         GPIO1D3_SFC_SIO3,
 331
 332         GPIO1D2_SHIFT           = 4,
 333         GPIO1D2_MASK            = 3,
 334         GPIO1D2_GPIO            = 0,
 335         GPIO1D2_NAND_D2,
 336         GPIO1D2_EMMC_D2,
 337         GPIO1D2_SFC_SIO2,
 338
 339         GPIO1D1_SHIFT           = 2,
 340         GPIO1D1_MASK            = 3,
 341         GPIO1D1_GPIO            = 0,
 342         GPIO1D1_NAND_D1,
 343         GPIO1D1_EMMC_D1,
 344         GPIO1D1_SFC_SIO1,
 345
 346         GPIO1D0_SHIFT           = 0,
 347         GPIO1D0_MASK            = 3,
 348         GPIO1D0_GPIO            = 0,
 349         GPIO1D0_NAND_D0,
 350         GPIO1D0_EMMC_D0,
 351         GPIO1D0_SFC_SIO0,
 352 };
 353
 354 /* GRF_GPIO2A_IOMUX */
 355 enum {
 356         GPIO2A7_SHIFT           = 14,
 357         GPIO2A7_MASK            = 1,
 358         GPIO2A7_GPIO            = 0,
 359         GPIO2A7_TESTCLK_OUT,
 360
 361         GPIO2A6_SHIFT           = 12,
 362         GPIO2A6_MASK            = 1,
 363         GPIO2A6_GPIO            = 0,
 364         GPIO2A6_NAND_CS0,
 365
 366         GPIO2A4_SHIFT           = 8,
 367         GPIO2A4_MASK            = 3,
 368         GPIO2A4_GPIO            = 0,
 369         GPIO2A4_NAND_RDY,
 370         GPIO2A4_EMMC_CMD,
 371         GPIO2A3_SFC_CLK,
 372
 373         GPIO2A3_SHIFT           = 6,
 374         GPIO2A3_MASK            = 3,
 375         GPIO2A3_GPIO            = 0,
 376         GPIO2A3_NAND_RDN,
 377         GPIO2A4_SFC_CSN1,
 378
 379         GPIO2A2_SHIFT           = 4,
 380         GPIO2A2_MASK            = 3,
 381         GPIO2A2_GPIO            = 0,
 382         GPIO2A2_NAND_WRN,
 383         GPIO2A4_SFC_CSN0,
 384
 385         GPIO2A1_SHIFT           = 2,
 386         GPIO2A1_MASK            = 3,
 387         GPIO2A1_GPIO            = 0,
 388         GPIO2A1_NAND_CLE,
 389         GPIO2A1_EMMC_CLKOUT,
 390
 391         GPIO2A0_SHIFT           = 0,
 392         GPIO2A0_MASK            = 3,
 393         GPIO2A0_GPIO            = 0,
 394         GPIO2A0_NAND_ALE,
 395         GPIO2A0_SPI_CLK,
 396 };
 397
 398 /* GRF_GPIO2B_IOMUX */
 399 enum {
 400         GPIO2B7_SHIFT           = 14,
 401         GPIO2B7_MASK            = 1,
 402         GPIO2B7_GPIO            = 0,
 403         GPIO2B7_MAC_RXER,
 404
 405         GPIO2B6_SHIFT           = 12,
 406         GPIO2B6_MASK            = 3,
 407         GPIO2B6_GPIO            = 0,
 408         GPIO2B6_MAC_CLKOUT,
 409         GPIO2B6_MAC_CLKIN,
 410
 411         GPIO2B5_SHIFT           = 10,
 412         GPIO2B5_MASK            = 1,
 413         GPIO2B5_GPIO            = 0,
 414         GPIO2B5_MAC_TXEN,
 415
 416         GPIO2B4_SHIFT           = 8,
 417         GPIO2B4_MASK            = 1,
 418         GPIO2B4_GPIO            = 0,
 419         GPIO2B4_MAC_MDIO,
 420
 421         GPIO2B2_SHIFT           = 4,
 422         GPIO2B2_MASK            = 1,
 423         GPIO2B2_GPIO            = 0,
 424         GPIO2B2_MAC_CRS,
 425 };
 426
 427 /* GRF_GPIO2C_IOMUX */
 428 enum {
 429         GPIO2C7_SHIFT           = 14,
 430         GPIO2C7_MASK            = 3,
 431         GPIO2C7_GPIO            = 0,
 432         GPIO2C7_UART1_SOUT,
 433         GPIO2C7_TESTCLK_OUT1,
 434
 435         GPIO2C6_SHIFT           = 12,
 436         GPIO2C6_MASK            = 1,
 437         GPIO2C6_GPIO            = 0,
 438         GPIO2C6_UART1_SIN,
 439
 440         GPIO2C5_SHIFT           = 10,
 441         GPIO2C5_MASK            = 1,
 442         GPIO2C5_GPIO            = 0,
 443         GPIO2C5_I2C2_SCL,
 444
 445         GPIO2C4_SHIFT           = 8,
 446         GPIO2C4_MASK            = 1,
 447         GPIO2C4_GPIO            = 0,
 448         GPIO2C4_I2C2_SDA,
 449
 450         GPIO2C3_SHIFT           = 6,
 451         GPIO2C3_MASK            = 1,
 452         GPIO2C3_GPIO            = 0,
 453         GPIO2C3_MAC_TXD0,
 454
 455         GPIO2C2_SHIFT           = 4,
 456         GPIO2C2_MASK            = 1,
 457         GPIO2C2_GPIO            = 0,
 458         GPIO2C2_MAC_TXD1,
 459
 460         GPIO2C1_SHIFT           = 2,
 461         GPIO2C1_MASK            = 1,
 462         GPIO2C1_GPIO            = 0,
 463         GPIO2C1_MAC_RXD0,
 464
 465         GPIO2C0_SHIFT           = 0,
 466         GPIO2C0_MASK            = 1,
 467         GPIO2C0_GPIO            = 0,
 468         GPIO2C0_MAC_RXD1,
 469 };
 470
 471 /* GRF_GPIO2D_IOMUX */
 472 enum {
 473         GPIO2D6_SHIFT           = 12,
 474         GPIO2D6_MASK            = 1,
 475         GPIO2D6_GPIO            = 0,
 476         GPIO2D6_I2S_SDO1,
 477
 478         GPIO2D5_SHIFT           = 10,
 479         GPIO2D5_MASK            = 1,
 480         GPIO2D5_GPIO            = 0,
 481         GPIO2D5_I2S_SDO2,
 482
 483         GPIO2D4_SHIFT           = 8,
 484         GPIO2D4_MASK            = 1,
 485         GPIO2D4_GPIO            = 0,
 486         GPIO2D4_I2S_SDO3,
 487
 488         GPIO2D1_SHIFT           = 2,
 489         GPIO2D1_MASK            = 1,
 490         GPIO2D1_GPIO            = 0,
 491         GPIO2D1_MAC_MDC,
 492 };
 493 #endif