arch/arm/include/asm/arch-rockchip/edp_rk3288.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2015 Google, Inc
   4  * Copyright 2014 Rockchip Inc.
   5  */
   6
   7 #ifndef _ASM_ARCH_EDP_H
   8 #define _ASM_ARCH_EDP_H
   9
  10 struct rk3288_edp {
  11         u8      res0[0x10];
  12         u32     dp_tx_version;
  13         u8      res1[0x4];
  14         u32     func_en_1;
  15         u32     func_en_2;
  16         u32     video_ctl_1;
  17         u32     video_ctl_2;
  18         u32     video_ctl_3;
  19         u32     video_ctl_4;
  20         u8      res2[0xc];
  21         u32     video_ctl_8;
  22         u8      res3[0x4];
  23         u32     video_ctl_10;
  24         u32     total_line_l;
  25         u32     total_line_h;
  26         u32     active_line_l;
  27         u32     active_line_h;
  28         u32     v_f_porch;
  29         u32     vsync;
  30         u32     v_b_porch;
  31         u32     total_pixel_l;
  32         u32     total_pixel_h;
  33         u32     active_pixel_l;
  34         u32     active_pixel_h;
  35         u32     h_f_porch_l;
  36         u32     h_f_porch_h;
  37         u32     hsync_l;
  38         u32     hysnc_h;
  39         u32     h_b_porch_l;
  40         u32     h_b_porch_h;
  41         u32     vid_status;
  42         u32     total_line_sta_l;
  43         u32     total_line_sta_h;
  44         u32     active_line_sta_l;
  45         u32     active_line_sta_h;
  46         u32     v_f_porch_sta;
  47         u32     vsync_sta;
  48         u32     v_b_porch_sta;
  49         u32     total_pixel_sta_l;
  50         u32     total_pixel_sta_h;
  51         u32     active_pixel_sta_l;
  52         u32     active_pixel_sta_h;
  53         u32     h_f_porch_sta_l;
  54         u32     h_f_porch_sta_h;
  55         u32     hsync_sta_l;
  56         u32     hsync_sta_h;
  57         u32     h_b_porch_sta_l;
  58         u32     h_b_porch__sta_h;
  59         u8      res4[0x28];
  60         u32     pll_reg_1;
  61         u8      res5[4];
  62         u32     ssc_reg;
  63         u8      res6[0xc];
  64         u32     tx_common;
  65         u32     tx_common2;
  66         u8      res7[0x4];
  67         u32     dp_aux;
  68         u32     dp_bias;
  69         u32     dp_test;
  70         u32     dp_pd;
  71         u32     dp_reserv1;
  72         u32     dp_reserv2;
  73         u8      res8[0x224];
  74         u32     lane_map;
  75         u8      res9[0x14];
  76         u32     analog_ctl_2;
  77         u8      res10[0x48];
  78         u32     int_state;
  79         u32     common_int_sta_1;
  80         u32     common_int_sta_2;
  81         u32     common_int_sta_3;
  82         u32     common_int_sta_4;
  83         u32     spdif_biphase_int_sta;
  84         u8      res11[0x4];
  85         u32     dp_int_sta;
  86         u32     common_int_mask_1;
  87         u32     common_int_mask_2;
  88         u32     common_int_mask_3;
  89         u32     common_int_mask_4;
  90         u8      res12[0x08];
  91         u32     int_sta_mask;
  92         u32     int_ctl;
  93         u8      res13[0x200];
  94         u32     sys_ctl_1;
  95         u32     sys_ctl_2;
  96         u32     sys_ctl_3;
  97         u32     sys_ctl_4;
  98         u32     dp_vid_ctl;
  99         u8      res14[0x4];
 100         u32     dp_aud_ctl;
 101         u8      res15[0x24];
 102         u32     pkt_send_ctl;
 103         u8      res16[0x4];
 104         u32     dp_hdcp_ctl;
 105         u8      res17[0x34];
 106         u32     link_bw_set;
 107         u32     lane_count_set;
 108         u32     dp_training_ptn_set;
 109         u32     ln_link_trn_ctl[4];
 110         u8      res18[0x4];
 111         u32     dp_hw_link_training;
 112         u8      res19[0x1c];
 113         u32     dp_debug_ctl;
 114         u32     hpd_deglitch_l;
 115         u32     hpd_deglitch_h;
 116         u8      res20[0x14];
 117         u32     dp_link_debug_ctl;
 118         u8      res21[0x1c];
 119         u32     m_vid_0;
 120         u32     m_vid_1;
 121         u32     m_vid_2;
 122         u32     n_vid_0;
 123         u32     n_vid_1;
 124         u32     n_vid_2;
 125         u32     m_vid_mon;
 126         u8      res22[0x14];
 127         u32     dp_video_fifo_thrd;
 128         u8      res23[0x8];
 129         u32     dp_audio_margin;
 130         u8      res24[0x20];
 131         u32     dp_m_cal_ctl;
 132         u32     m_vid_gen_filter_th;
 133         u8      res25[0x10];
 134         u32     m_aud_gen_filter_th;
 135         u8      res26[0x4];
 136         u32     aux_ch_sta;
 137         u32     aux_err_num;
 138         u32     aux_ch_defer_dtl;
 139         u32     aux_rx_comm;
 140         u32     buf_data_ctl;
 141         u32     aux_ch_ctl_1;
 142         u32     aux_addr_7_0;
 143         u32     aux_addr_15_8;
 144         u32     aux_addr_19_16;
 145         u32     aux_ch_ctl_2;
 146         u8      res27[0x18];
 147         u32     buf_data[16];
 148         u32     soc_general_ctl;
 149         u8      res29[0x1e0];
 150         u32     pll_reg_2;
 151         u32     pll_reg_3;
 152         u32     pll_reg_4;
 153         u8      res30[0x10];
 154         u32     pll_reg_5;
 155 };
 156 check_member(rk3288_edp, pll_reg_5, 0xa00);
 157
 158 /* func_en_1 */
 159 #define VID_CAP_FUNC_EN_N                       (0x1 << 6)
 160 #define VID_FIFO_FUNC_EN_N                      (0x1 << 5)
 161 #define AUD_FIFO_FUNC_EN_N                      (0x1 << 4)
 162 #define AUD_FUNC_EN_N                           (0x1 << 3)
 163 #define HDCP_FUNC_EN_N                          (0x1 << 2)
 164 #define SW_FUNC_EN_N                            (0x1 << 0)
 165
 166 /* func_en_2 */
 167 #define SSC_FUNC_EN_N                           (0x1 << 7)
 168 #define AUX_FUNC_EN_N                           (0x1 << 2)
 169 #define SERDES_FIFO_FUNC_EN_N                   (0x1 << 1)
 170 #define LS_CLK_DOMAIN_FUNC_EN_N                 (0x1 << 0)
 171
 172 /* video_ctl_1 */
 173 #define VIDEO_EN                                (0x1 << 7)
 174 #define VIDEO_MUTE                              (0x1 << 6)
 175
 176 /* video_ctl_2 */
 177 #define IN_D_RANGE_MASK                         (0x1 << 7)
 178 #define IN_D_RANGE_SHIFT                        (7)
 179 #define IN_D_RANGE_CEA                          (0x1 << 7)
 180 #define IN_D_RANGE_VESA                         (0x0 << 7)
 181 #define IN_BPC_MASK                             (0x7 << 4)
 182 #define IN_BPC_SHIFT                            (4)
 183 #define IN_BPC_12_BITS                          (0x3 << 4)
 184 #define IN_BPC_10_BITS                          (0x2 << 4)
 185 #define IN_BPC_8_BITS                           (0x1 << 4)
 186 #define IN_BPC_6_BITS                           (0x0 << 4)
 187 #define IN_COLOR_F_MASK                         (0x3 << 0)
 188 #define IN_COLOR_F_SHIFT                        (0)
 189 #define IN_COLOR_F_YCBCR444                     (0x2 << 0)
 190 #define IN_COLOR_F_YCBCR422                     (0x1 << 0)
 191 #define IN_COLOR_F_RGB                          (0x0 << 0)
 192
 193 /* video_ctl_3 */
 194 #define IN_YC_COEFFI_MASK                       (0x1 << 7)
 195 #define IN_YC_COEFFI_SHIFT                      (7)
 196 #define IN_YC_COEFFI_ITU709                     (0x1 << 7)
 197 #define IN_YC_COEFFI_ITU601                     (0x0 << 7)
 198 #define VID_CHK_UPDATE_TYPE_MASK                (0x1 << 4)
 199 #define VID_CHK_UPDATE_TYPE_SHIFT               (4)
 200 #define VID_CHK_UPDATE_TYPE_1                   (0x1 << 4)
 201 #define VID_CHK_UPDATE_TYPE_0                   (0x0 << 4)
 202
 203 /* video_ctl_4 */
 204 #define BIST_EN                                 (0x1 << 3)
 205 #define BIST_WH_64                              (0x1 << 2)
 206 #define BIST_WH_32                              (0x0 << 2)
 207 #define BIST_TYPE_COLR_BAR                      (0x0 << 0)
 208 #define BIST_TYPE_GRAY_BAR                      (0x1 << 0)
 209 #define BIST_TYPE_MOBILE_BAR                    (0x2 << 0)
 210
 211 /* video_ctl_8 */
 212 #define VID_HRES_TH(x)                          (((x) & 0xf) << 4)
 213 #define VID_VRES_TH(x)                          (((x) & 0xf) << 0)
 214
 215 /* video_ctl_10 */
 216 #define F_SEL                                   (0x1 << 4)
 217 #define INTERACE_SCAN_CFG                       (0x1 << 2)
 218 #define INTERACD_SCAN_CFG_OFFSET                2
 219 #define VSYNC_POLARITY_CFG                      (0x1 << 1)
 220 #define VSYNC_POLARITY_CFG_OFFSET               1
 221 #define HSYNC_POLARITY_CFG                      (0x1 << 0)
 222 #define HSYNC_POLARITY_CFG_OFFSET               0
 223
 224 /* dp_pd */
 225 #define PD_INC_BG                               (0x1 << 7)
 226 #define PD_EXP_BG                               (0x1 << 6)
 227 #define PD_AUX                                  (0x1 << 5)
 228 #define PD_PLL                                  (0x1 << 4)
 229 #define PD_CH3                                  (0x1 << 3)
 230 #define PD_CH2                                  (0x1 << 2)
 231 #define PD_CH1                                  (0x1 << 1)
 232 #define PD_CH0                                  (0x1 << 0)
 233
 234 /* pll_reg_1 */
 235 #define REF_CLK_24M                             (0x1 << 1)
 236 #define REF_CLK_27M                             (0x0 << 1)
 237
 238 /* line_map */
 239 #define LANE3_MAP_LOGIC_LANE_0                  (0x0 << 6)
 240 #define LANE3_MAP_LOGIC_LANE_1                  (0x1 << 6)
 241 #define LANE3_MAP_LOGIC_LANE_2                  (0x2 << 6)
 242 #define LANE3_MAP_LOGIC_LANE_3                  (0x3 << 6)
 243 #define LANE2_MAP_LOGIC_LANE_0                  (0x0 << 4)
 244 #define LANE2_MAP_LOGIC_LANE_1                  (0x1 << 4)
 245 #define LANE2_MAP_LOGIC_LANE_2                  (0x2 << 4)
 246 #define LANE2_MAP_LOGIC_LANE_3                  (0x3 << 4)
 247 #define LANE1_MAP_LOGIC_LANE_0                  (0x0 << 2)
 248 #define LANE1_MAP_LOGIC_LANE_1                  (0x1 << 2)
 249 #define LANE1_MAP_LOGIC_LANE_2                  (0x2 << 2)
 250 #define LANE1_MAP_LOGIC_LANE_3                  (0x3 << 2)
 251 #define LANE0_MAP_LOGIC_LANE_0                  (0x0 << 0)
 252 #define LANE0_MAP_LOGIC_LANE_1                  (0x1 << 0)
 253 #define LANE0_MAP_LOGIC_LANE_2                  (0x2 << 0)
 254 #define LANE0_MAP_LOGIC_LANE_3                  (0x3 << 0)
 255
 256 /* analog_ctl_2 */
 257 #define SEL_24M                                 (0x1 << 3)
 258
 259 /* common_int_sta_1 */
 260 #define VSYNC_DET                               (0x1 << 7)
 261 #define PLL_LOCK_CHG                            (0x1 << 6)
 262 #define SPDIF_ERR                               (0x1 << 5)
 263 #define SPDIF_UNSTBL                            (0x1 << 4)
 264 #define VID_FORMAT_CHG                          (0x1 << 3)
 265 #define AUD_CLK_CHG                             (0x1 << 2)
 266 #define VID_CLK_CHG                             (0x1 << 1)
 267 #define SW_INT                                  (0x1 << 0)
 268
 269 /* common_int_sta_2 */
 270 #define ENC_EN_CHG                              (0x1 << 6)
 271 #define HW_BKSV_RDY                             (0x1 << 3)
 272 #define HW_SHA_DONE                             (0x1 << 2)
 273 #define HW_AUTH_STATE_CHG                       (0x1 << 1)
 274 #define HW_AUTH_DONE                            (0x1 << 0)
 275
 276 /* common_int_sta_3 */
 277 #define AFIFO_UNDER                             (0x1 << 7)
 278 #define AFIFO_OVER                              (0x1 << 6)
 279 #define R0_CHK_FLAG                             (0x1 << 5)
 280
 281 /* common_int_sta_4 */
 282 #define PSR_ACTIVE                              (0x1 << 7)
 283 #define PSR_INACTIVE                            (0x1 << 6)
 284 #define SPDIF_BI_PHASE_ERR                      (0x1 << 5)
 285 #define HOTPLUG_CHG                             (0x1 << 2)
 286 #define HPD_LOST                                (0x1 << 1)
 287 #define PLUG                                    (0x1 << 0)
 288
 289 /* dp_int_sta */
 290 #define INT_HPD                                 (0x1 << 6)
 291 #define HW_LT_DONE                              (0x1 << 5)
 292 #define SINK_LOST                               (0x1 << 3)
 293 #define LINK_LOST                               (0x1 << 2)
 294 #define RPLY_RECEIV                             (0x1 << 1)
 295 #define AUX_ERR                                 (0x1 << 0)
 296
 297 /* int_ctl */
 298 #define SOFT_INT_CTRL                           (0x1 << 2)
 299 #define INT_POL                                 (0x1 << 0)
 300
 301 /* sys_ctl_1 */
 302 #define DET_STA                                 (0x1 << 2)
 303 #define FORCE_DET                               (0x1 << 1)
 304 #define DET_CTRL                                (0x1 << 0)
 305
 306 /* sys_ctl_2 */
 307 #define CHA_CRI(x)                              (((x) & 0xf) << 4)
 308 #define CHA_STA                                 (0x1 << 2)
 309 #define FORCE_CHA                               (0x1 << 1)
 310 #define CHA_CTRL                                (0x1 << 0)
 311
 312 /* sys_ctl_3 */
 313 #define HPD_STATUS                              (0x1 << 6)
 314 #define F_HPD                                   (0x1 << 5)
 315 #define HPD_CTRL                                (0x1 << 4)
 316 #define HDCP_RDY                                (0x1 << 3)
 317 #define STRM_VALID                              (0x1 << 2)
 318 #define F_VALID                                 (0x1 << 1)
 319 #define VALID_CTRL                              (0x1 << 0)
 320
 321 /* sys_ctl_4 */
 322 #define FIX_M_AUD                               (0x1 << 4)
 323 #define ENHANCED                                (0x1 << 3)
 324 #define FIX_M_VID                               (0x1 << 2)
 325 #define M_VID_UPDATE_CTRL                       (0x3 << 0)
 326
 327 /* pll_reg_2 */
 328 #define LDO_OUTPUT_V_SEL_145                    (2 << 6)
 329 #define KVCO_DEFALUT                            (1 << 4)
 330 #define CHG_PUMP_CUR_SEL_5US                    (1 << 2)
 331 #define V2L_CUR_SEL_1MA                         (1 << 0)
 332
 333 /* pll_reg_3 */
 334 #define LOCK_DET_CNT_SEL_256                    (2 << 5)
 335 #define LOOP_FILTER_RESET                       (0 << 4)
 336 #define PALL_SSC_RESET                          (0 << 3)
 337 #define LOCK_DET_BYPASS                         (0 << 2)
 338 #define PLL_LOCK_DET_MODE                       (0 << 1)
 339 #define PLL_LOCK_DET_FORCE                      (0 << 0)
 340
 341 /* pll_reg_5 */
 342 #define REGULATOR_V_SEL_950MV                   (2 << 4)
 343 #define STANDBY_CUR_SEL                         (0 << 3)
 344 #define CHG_PUMP_INOUT_CTRL_1200MV              (1 << 1)
 345 #define CHG_PUMP_INPUT_CTRL_OP                  (0 << 0)
 346
 347 /* ssc_reg */
 348 #define SSC_OFFSET                              (0 << 6)
 349 #define SSC_MODE                                (1 << 4)
 350 #define SSC_DEPTH                               (9 << 0)
 351
 352 /* tx_common */
 353 #define TX_SWING_PRE_EMP_MODE                   (1 << 7)
 354 #define PRE_DRIVER_PW_CTRL1                     (0 << 5)
 355 #define LP_MODE_CLK_REGULATOR                   (0 << 4)
 356 #define RESISTOR_MSB_CTRL                       (0 << 3)
 357 #define RESISTOR_CTRL                           (7 << 0)
 358
 359 /* dp_aux */
 360 #define DP_AUX_COMMON_MODE                      (0 << 4)
 361 #define DP_AUX_EN                               (0 << 3)
 362 #define AUX_TERM_50OHM                          (3 << 0)
 363
 364 /* dp_bias */
 365 #define DP_BG_OUT_SEL                           (4 << 4)
 366 #define DP_DB_CUR_CTRL                          (0 << 3)
 367 #define DP_BG_SEL                               (1 << 2)
 368 #define DP_RESISTOR_TUNE_BG                     (2 << 0)
 369
 370 /* dp_reserv2 */
 371 #define CH1_CH3_SWING_EMP_CTRL                  (5 << 4)
 372 #define CH0_CH2_SWING_EMP_CTRL                  (5 << 0)
 373
 374 /* dp_training_ptn_set */
 375 #define SCRAMBLING_DISABLE                      (0x1 << 5)
 376 #define SCRAMBLING_ENABLE                       (0x0 << 5)
 377 #define LINK_QUAL_PATTERN_SET_MASK              (0x7 << 2)
 378 #define LINK_QUAL_PATTERN_SET_HBR2              (0x5 << 2)
 379 #define LINK_QUAL_PATTERN_SET_80BIT             (0x4 << 2)
 380 #define LINK_QUAL_PATTERN_SET_PRBS7             (0x3 << 2)
 381 #define LINK_QUAL_PATTERN_SET_D10_2             (0x1 << 2)
 382 #define LINK_QUAL_PATTERN_SET_DISABLE           (0x0 << 2)
 383 #define SW_TRAINING_PATTERN_SET_MASK            (0x3 << 0)
 384 #define SW_TRAINING_PATTERN_SET_PTN2            (0x2 << 0)
 385 #define SW_TRAINING_PATTERN_SET_PTN1            (0x1 << 0)
 386 #define SW_TRAINING_PATTERN_SET_DISABLE         (0x0 << 0)
 387
 388 /* dp_hw_link_training_ctl */
 389 #define HW_LT_ERR_CODE_MASK                     0x70
 390 #define HW_LT_ERR_CODE_SHIFT                    4
 391 #define HW_LT_EN                                (0x1 << 0)
 392
 393 /* dp_debug_ctl */
 394 #define PLL_LOCK                                (0x1 << 4)
 395 #define F_PLL_LOCK                              (0x1 << 3)
 396 #define PLL_LOCK_CTRL                           (0x1 << 2)
 397 #define POLL_EN                                 (0x1 << 1)
 398 #define PN_INV                                  (0x1 << 0)
 399
 400 /* aux_ch_sta */
 401 #define AUX_BUSY                                (0x1 << 4)
 402 #define AUX_STATUS_MASK                         (0xf << 0)
 403
 404 /* aux_ch_defer_ctl */
 405 #define DEFER_CTRL_EN                           (0x1 << 7)
 406 #define DEFER_COUNT(x)                          (((x) & 0x7f) << 0)
 407
 408 /* aux_rx_comm */
 409 #define AUX_RX_COMM_I2C_DEFER                   (0x2 << 2)
 410 #define AUX_RX_COMM_AUX_DEFER                   (0x2 << 0)
 411
 412 /* buffer_data_ctl */
 413 #define BUF_CLR                                 (0x1 << 7)
 414 #define BUF_HAVE_DATA                           (0x1 << 4)
 415 #define BUF_DATA_COUNT(x)                       (((x) & 0xf) << 0)
 416
 417 /* aux_ch_ctl_1 */
 418 #define AUX_LENGTH(x)                           (((x - 1) & 0xf) << 4)
 419 #define AUX_TX_COMM_MASK                        (0xf << 0)
 420 #define AUX_TX_COMM_DP_TRANSACTION              (0x1 << 3)
 421 #define AUX_TX_COMM_I2C_TRANSACTION             (0x0 << 3)
 422 #define AUX_TX_COMM_MOT                         (0x1 << 2)
 423 #define AUX_TX_COMM_WRITE                       (0x0 << 0)
 424 #define AUX_TX_COMM_READ                        (0x1 << 0)
 425
 426 /* aux_ch_ctl_2 */
 427 #define PD_AUX_IDLE                             (0x1 << 3)
 428 #define ADDR_ONLY                               (0x1 << 1)
 429 #define AUX_EN                                  (0x1 << 0)
 430
 431 /* tx_sw_reset */
 432 #define RST_DP_TX                               (0x1 << 0)
 433
 434 /* analog_ctl_1 */
 435 #define TX_TERMINAL_CTRL_50_OHM                 (0x1 << 4)
 436
 437 /* analog_ctl_3 */
 438 #define DRIVE_DVDD_BIT_1_0625V                  (0x4 << 5)
 439 #define VCO_BIT_600_MICRO                       (0x5 << 0)
 440
 441 /* pll_filter_ctl_1 */
 442 #define PD_RING_OSC                             (0x1 << 6)
 443 #define AUX_TERMINAL_CTRL_37_5_OHM              (0x0 << 4)
 444 #define AUX_TERMINAL_CTRL_45_OHM                (0x1 << 4)
 445 #define AUX_TERMINAL_CTRL_50_OHM                (0x2 << 4)
 446 #define AUX_TERMINAL_CTRL_65_OHM                (0x3 << 4)
 447 #define TX_CUR1_2X                              (0x1 << 2)
 448 #define TX_CUR_16_MA                            (0x3 << 0)
 449
 450 /* Definition for DPCD Register */
 451 #define DPCD_DPCD_REV                           (0x0000)
 452 #define DPCD_MAX_LINK_RATE                      (0x0001)
 453 #define DPCD_MAX_LANE_COUNT                     (0x0002)
 454 #define DP_MAX_LANE_COUNT_MASK                  0x1f
 455 #define DP_TPS3_SUPPORTED                       (1 << 6)
 456 #define DP_ENHANCED_FRAME_CAP                   (1 << 7)
 457
 458 #define DPCD_LINK_BW_SET                        (0x0100)
 459 #define DPCD_LANE_COUNT_SET                     (0x0101)
 460
 461 #define DPCD_TRAINING_PATTERN_SET               (0x0102)
 462 #define DP_TRAINING_PATTERN_DISABLE             0
 463 #define DP_TRAINING_PATTERN_1                   1
 464 #define DP_TRAINING_PATTERN_2                   2
 465 #define DP_TRAINING_PATTERN_3                   3
 466 #define DP_TRAINING_PATTERN_MASK                0x3
 467
 468 #define DPCD_TRAINING_LANE0_SET                 (0x0103)
 469 #define DP_TRAIN_VOLTAGE_SWING_MASK             0x3
 470 #define DP_TRAIN_VOLTAGE_SWING_SHIFT            0
 471 #define DP_TRAIN_MAX_SWING_REACHED              (1 << 2)
 472 #define DP_TRAIN_VOLTAGE_SWING_400              (0 << 0)
 473 #define DP_TRAIN_VOLTAGE_SWING_600              (1 << 0)
 474 #define DP_TRAIN_VOLTAGE_SWING_800              (2 << 0)
 475 #define DP_TRAIN_VOLTAGE_SWING_1200             (3 << 0)
 476
 477 #define DP_TRAIN_PRE_EMPHASIS_MASK              (3 << 3)
 478 #define DP_TRAIN_PRE_EMPHASIS_0                 (0 << 3)
 479 #define DP_TRAIN_PRE_EMPHASIS_3_5               (1 << 3)
 480 #define DP_TRAIN_PRE_EMPHASIS_6                 (2 << 3)
 481 #define DP_TRAIN_PRE_EMPHASIS_9_5               (3 << 3)
 482
 483 #define DP_TRAIN_PRE_EMPHASIS_SHIFT             3
 484 #define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED       (1 << 5)
 485
 486 #define DPCD_LANE0_1_STATUS                     (0x0202)
 487 #define DPCD_LANE2_3_STATUS                     (0x0203)
 488 #define DP_LANE_CR_DONE                         (1 << 0)
 489 #define DP_LANE_CHANNEL_EQ_DONE                 (1 << 1)
 490 #define DP_LANE_SYMBOL_LOCKED                   (1 << 2)
 491 #define DP_CHANNEL_EQ_BITS                      (DP_LANE_CR_DONE |\
 492                                                 DP_LANE_CHANNEL_EQ_DONE |\
 493                                                 DP_LANE_SYMBOL_LOCKED)
 494
 495 #define DPCD_LANE_ALIGN_STATUS_UPDATED          (0x0204)
 496 #define DP_INTERLANE_ALIGN_DONE                 (1 << 0)
 497 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED       (1 << 6)
 498 #define DP_LINK_STATUS_UPDATED                  (1 << 7)
 499
 500 #define DPCD_ADJUST_REQUEST_LANE0_1             (0x0206)
 501 #define DPCD_ADJUST_REQUEST_LANE2_3             (0x0207)
 502 #define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK      0x03
 503 #define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT     0
 504 #define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK       0x0c
 505 #define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT      2
 506 #define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK      0x30
 507 #define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT     4
 508 #define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK       0xc0
 509 #define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT      6
 510
 511 #define DPCD_TEST_REQUEST                       (0x0218)
 512 #define DPCD_TEST_RESPONSE                      (0x0260)
 513 #define DPCD_TEST_EDID_CHECKSUM                 (0x0261)
 514 #define DPCD_LINK_POWER_STATE                   (0x0600)
 515 #define DP_SET_POWER_D0                         0x1
 516 #define DP_SET_POWER_D3                         0x2
 517 #define DP_SET_POWER_MASK                       0x3
 518
 519 #define AUX_ADDR_7_0(x)                         (((x) >> 0) & 0xff)
 520 #define AUX_ADDR_15_8(x)                        (((x) >> 8) & 0xff)
 521 #define AUX_ADDR_19_16(x)                       (((x) >> 16) & 0x0f)
 522
 523 #define STREAM_ON_TIMEOUT 100
 524 #define PLL_LOCK_TIMEOUT 10
 525 #define DP_INIT_TRIES 10
 526
 527 #define EDID_ADDR                               0x50
 528 #define EDID_LENGTH                             0x80
 529 #define EDID_HEADER                             0x00
 530 #define EDID_EXTENSION_FLAG                     0x7e
 531
 532
 533 enum dpcd_request {
 534         DPCD_READ,
 535         DPCD_WRITE,
 536 };
 537
 538 enum dp_irq_type {
 539         DP_IRQ_TYPE_HP_CABLE_IN,
 540         DP_IRQ_TYPE_HP_CABLE_OUT,
 541         DP_IRQ_TYPE_HP_CHANGE,
 542         DP_IRQ_TYPE_UNKNOWN,
 543 };
 544
 545 enum color_coefficient {
 546         COLOR_YCBCR601,
 547         COLOR_YCBCR709
 548 };
 549
 550 enum dynamic_range {
 551         VESA,
 552         CEA
 553 };
 554
 555 enum clock_recovery_m_value_type {
 556         CALCULATED_M,
 557         REGISTER_M
 558 };
 559
 560 enum video_timing_recognition_type {
 561         VIDEO_TIMING_FROM_CAPTURE,
 562         VIDEO_TIMING_FROM_REGISTER
 563 };
 564
 565 enum pattern_set {
 566         PRBS7,
 567         D10_2,
 568         TRAINING_PTN1,
 569         TRAINING_PTN2,
 570         DP_NONE
 571 };
 572
 573 enum color_space {
 574         CS_RGB,
 575         CS_YCBCR422,
 576         CS_YCBCR444
 577 };
 578
 579 enum color_depth {
 580         COLOR_6,
 581         COLOR_8,
 582         COLOR_10,
 583         COLOR_12
 584 };
 585
 586 enum link_rate_type {
 587         LINK_RATE_1_62GBPS = 0x06,
 588         LINK_RATE_2_70GBPS = 0x0a
 589 };
 590
 591 enum link_lane_count_type {
 592         LANE_CNT1 = 1,
 593         LANE_CNT2 = 2,
 594         LANE_CNT4 = 4
 595 };
 596
 597 enum link_training_state {
 598         LT_START,
 599         LT_CLK_RECOVERY,
 600         LT_EQ_TRAINING,
 601         FINISHED,
 602         FAILED
 603 };
 604
 605 enum voltage_swing_level {
 606         VOLTAGE_LEVEL_0,
 607         VOLTAGE_LEVEL_1,
 608         VOLTAGE_LEVEL_2,
 609         VOLTAGE_LEVEL_3,
 610 };
 611
 612 enum pre_emphasis_level {
 613         PRE_EMPHASIS_LEVEL_0,
 614         PRE_EMPHASIS_LEVEL_1,
 615         PRE_EMPHASIS_LEVEL_2,
 616         PRE_EMPHASIS_LEVEL_3,
 617 };
 618
 619 enum analog_power_block {
 620         AUX_BLOCK,
 621         CH0_BLOCK,
 622         CH1_BLOCK,
 623         CH2_BLOCK,
 624         CH3_BLOCK,
 625         ANALOG_TOTAL,
 626         POWER_ALL
 627 };
 628
 629 struct link_train {
 630         unsigned char revision;
 631         u8 link_rate;
 632         u8 lane_count;
 633 };
 634
 635 #endif