arch/arm/include/asm/arch-rockchip/cru_rk3288.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2015 Google, Inc
   4  *
   5  * (C) Copyright 2008-2014 Rockchip Electronics
   6  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
   7  */
   8 #ifndef _ASM_ARCH_CRU_RK3288_H
   9 #define _ASM_ARCH_CRU_RK3288_H
  10
  11 #define OSC_HZ          (24 * 1000 * 1000)
  12
  13 #define APLL_HZ         (1800 * 1000000)
  14 #define GPLL_HZ         (594 * 1000000)
  15 #define CPLL_HZ         (384 * 1000000)
  16 #define NPLL_HZ         (384 * 1000000)
  17
  18 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
  19 #define PD_BUS_ACLK_HZ  297000000
  20 #define PD_BUS_HCLK_HZ  148500000
  21 #define PD_BUS_PCLK_HZ  74250000
  22
  23 #define PERI_ACLK_HZ    148500000
  24 #define PERI_HCLK_HZ    148500000
  25 #define PERI_PCLK_HZ    74250000
  26
  27 /* Private data for the clock driver - used by rockchip_get_cru() */
  28 struct rk3288_clk_priv {
  29         struct rk3288_grf *grf;
  30         struct rockchip_cru *cru;
  31         ulong rate;
  32 };
  33
  34 struct rockchip_cru {
  35         struct rk3288_pll {
  36                 u32 con0;
  37                 u32 con1;
  38                 u32 con2;
  39                 u32 con3;
  40         } pll[5];
  41         u32 cru_mode_con;
  42         u32 reserved0[3];
  43         u32 cru_clksel_con[43];
  44         u32 reserved1[21];
  45         u32 cru_clkgate_con[19];
  46         u32 reserved2;
  47         u32 cru_glb_srst_fst_value;
  48         u32 cru_glb_srst_snd_value;
  49         u32 cru_softrst_con[12];
  50         u32 cru_misc_con;
  51         u32 cru_glb_cnt_th;
  52         u32 cru_glb_rst_con;
  53         u32 reserved3;
  54         u32 glb_rst_st;
  55         u32 reserved4;
  56         u32 cru_sdmmc_con[2];
  57         u32 cru_sdio0_con[2];
  58         u32 cru_sdio1_con[2];
  59         u32 cru_emmc_con[2];
  60 };
  61 check_member(rockchip_cru, cru_emmc_con[1], 0x021c);
  62
  63 /* CRU_CLKSEL11_CON */
  64 enum {
  65         HSICPHY_DIV_SHIFT       = 8,
  66         HSICPHY_DIV_MASK        = 0x3f << HSICPHY_DIV_SHIFT,
  67
  68         MMC0_PLL_SHIFT          = 6,
  69         MMC0_PLL_MASK           = 3 << MMC0_PLL_SHIFT,
  70         MMC0_PLL_SELECT_CODEC   = 0,
  71         MMC0_PLL_SELECT_GENERAL,
  72         MMC0_PLL_SELECT_24MHZ,
  73
  74         MMC0_DIV_SHIFT          = 0,
  75         MMC0_DIV_MASK           = 0x3f << MMC0_DIV_SHIFT,
  76 };
  77
  78 /* CRU_CLKSEL8_CON */
  79 enum {
  80         I2S0_FRAC_DENOM_SHIFT   = 0,
  81         I2S0_FRAC_DENOM_MASK    = 0xffff << I2S0_FRAC_DENOM_SHIFT,
  82         I2S0_FRAC_NUMER_SHIFT   = 16,
  83         I2S0_FRAC_NUMER_MASK    = 0xffffu << I2S0_FRAC_NUMER_SHIFT,
  84 };
  85
  86 /* CRU_CLKSEL12_CON */
  87 enum {
  88         EMMC_PLL_SHIFT          = 0xe,
  89         EMMC_PLL_MASK           = 3 << EMMC_PLL_SHIFT,
  90         EMMC_PLL_SELECT_CODEC   = 0,
  91         EMMC_PLL_SELECT_GENERAL,
  92         EMMC_PLL_SELECT_24MHZ,
  93
  94         EMMC_DIV_SHIFT          = 8,
  95         EMMC_DIV_MASK           = 0x3f << EMMC_DIV_SHIFT,
  96
  97         SDIO0_PLL_SHIFT         = 6,
  98         SDIO0_PLL_MASK          = 3 << SDIO0_PLL_SHIFT,
  99         SDIO0_PLL_SELECT_CODEC  = 0,
 100         SDIO0_PLL_SELECT_GENERAL,
 101         SDIO0_PLL_SELECT_24MHZ,
 102
 103         SDIO0_DIV_SHIFT         = 0,
 104         SDIO0_DIV_MASK          = 0x3f << SDIO0_DIV_SHIFT,
 105 };
 106
 107 /* CRU_CLKSEL21_CON */
 108 enum {
 109         MAC_DIV_CON_SHIFT       = 0xf,
 110         MAC_DIV_CON_MASK        = 0x1f << MAC_DIV_CON_SHIFT,
 111
 112         RMII_EXTCLK_SHIFT       = 4,
 113         RMII_EXTCLK_MASK        = 1 << RMII_EXTCLK_SHIFT,
 114         RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
 115         RMII_EXTCLK_SELECT_EXT_CLK = 1,
 116
 117         EMAC_PLL_SHIFT          = 0,
 118         EMAC_PLL_MASK           = 0x3 << EMAC_PLL_SHIFT,
 119         EMAC_PLL_SELECT_NEW     = 0x0,
 120         EMAC_PLL_SELECT_CODEC   = 0x1,
 121         EMAC_PLL_SELECT_GENERAL = 0x2,
 122 };
 123
 124 /* CRU_CLKSEL25_CON */
 125 enum {
 126         SPI1_PLL_SHIFT          = 0xf,
 127         SPI1_PLL_MASK           = 1 << SPI1_PLL_SHIFT,
 128         SPI1_PLL_SELECT_CODEC   = 0,
 129         SPI1_PLL_SELECT_GENERAL,
 130
 131         SPI1_DIV_SHIFT          = 8,
 132         SPI1_DIV_MASK           = 0x7f << SPI1_DIV_SHIFT,
 133
 134         SPI0_PLL_SHIFT          = 7,
 135         SPI0_PLL_MASK           = 1 << SPI0_PLL_SHIFT,
 136         SPI0_PLL_SELECT_CODEC   = 0,
 137         SPI0_PLL_SELECT_GENERAL,
 138
 139         SPI0_DIV_SHIFT          = 0,
 140         SPI0_DIV_MASK           = 0x7f << SPI0_DIV_SHIFT,
 141 };
 142
 143 /* CRU_CLKSEL37_CON */
 144 enum {
 145         PCLK_CORE_DBG_DIV_SHIFT = 9,
 146         PCLK_CORE_DBG_DIV_MASK  = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
 147
 148         ATCLK_CORE_DIV_CON_SHIFT = 4,
 149         ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
 150
 151         CLK_L2RAM_DIV_SHIFT     = 0,
 152         CLK_L2RAM_DIV_MASK      = 7 << CLK_L2RAM_DIV_SHIFT,
 153 };
 154
 155 /* CRU_CLKSEL39_CON */
 156 enum {
 157         ACLK_HEVC_PLL_SHIFT     = 0xe,
 158         ACLK_HEVC_PLL_MASK      = 3 << ACLK_HEVC_PLL_SHIFT,
 159         ACLK_HEVC_PLL_SELECT_CODEC = 0,
 160         ACLK_HEVC_PLL_SELECT_GENERAL,
 161         ACLK_HEVC_PLL_SELECT_NEW,
 162
 163         ACLK_HEVC_DIV_SHIFT     = 8,
 164         ACLK_HEVC_DIV_MASK      = 0x1f << ACLK_HEVC_DIV_SHIFT,
 165
 166         SPI2_PLL_SHIFT          = 7,
 167         SPI2_PLL_MASK           = 1 << SPI2_PLL_SHIFT,
 168         SPI2_PLL_SELECT_CODEC   = 0,
 169         SPI2_PLL_SELECT_GENERAL,
 170
 171         SPI2_DIV_SHIFT          = 0,
 172         SPI2_DIV_MASK           = 0x7f << SPI2_DIV_SHIFT,
 173 };
 174
 175 /* CRU_MODE_CON */
 176 enum {
 177         CRU_MODE_MASK           = 3,
 178
 179         NPLL_MODE_SHIFT         = 0xe,
 180         NPLL_MODE_MASK          = CRU_MODE_MASK << NPLL_MODE_SHIFT,
 181         NPLL_MODE_SLOW          = 0,
 182         NPLL_MODE_NORMAL,
 183         NPLL_MODE_DEEP,
 184
 185         GPLL_MODE_SHIFT         = 0xc,
 186         GPLL_MODE_MASK          = CRU_MODE_MASK << GPLL_MODE_SHIFT,
 187         GPLL_MODE_SLOW          = 0,
 188         GPLL_MODE_NORMAL,
 189         GPLL_MODE_DEEP,
 190
 191         CPLL_MODE_SHIFT         = 8,
 192         CPLL_MODE_MASK          = CRU_MODE_MASK << CPLL_MODE_SHIFT,
 193         CPLL_MODE_SLOW          = 0,
 194         CPLL_MODE_NORMAL,
 195         CPLL_MODE_DEEP,
 196
 197         DPLL_MODE_SHIFT         = 4,
 198         DPLL_MODE_MASK          = CRU_MODE_MASK << DPLL_MODE_SHIFT,
 199         DPLL_MODE_SLOW          = 0,
 200         DPLL_MODE_NORMAL,
 201         DPLL_MODE_DEEP,
 202
 203         APLL_MODE_SHIFT         = 0,
 204         APLL_MODE_MASK          = CRU_MODE_MASK << APLL_MODE_SHIFT,
 205         APLL_MODE_SLOW          = 0,
 206         APLL_MODE_NORMAL,
 207         APLL_MODE_DEEP,
 208 };
 209
 210 /* CRU_APLL_CON0 */
 211 enum {
 212         CLKR_SHIFT              = 8,
 213         CLKR_MASK               = 0x3f << CLKR_SHIFT,
 214
 215         CLKOD_SHIFT             = 0,
 216         CLKOD_MASK              = 0xf << CLKOD_SHIFT,
 217 };
 218
 219 /* CRU_APLL_CON1 */
 220 enum {
 221         LOCK_SHIFT              = 0x1f,
 222         LOCK_MASK               = 1 << LOCK_SHIFT,
 223         LOCK_UNLOCK             = 0,
 224         LOCK_LOCK,
 225
 226         CLKF_SHIFT              = 0,
 227         CLKF_MASK               = 0x1fff << CLKF_SHIFT,
 228 };
 229
 230 #endif