arch/arm/include/asm/arch-rockchip/cru_rk3066.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2021 Paweł Jarosz <paweljarosz3691@gmail.com>
   4  */
   5
   6 #ifndef _ASM_ARCH_CRU_RK3066_H
   7 #define _ASM_ARCH_CRU_RK3066_H
   8
   9 #include <linux/bitops.h>
  10 #include <linux/bitfield.h>
  11
  12 #define REG(name, h, l) \
  13         name##_MASK = GENMASK(h, l), \
  14         name##_SHIFT = __bf_shf(name##_MASK)
  15
  16 #define OSC_HZ          (24 * 1000 * 1000)
  17
  18 #define APLL_HZ         (1416 * 1000000)
  19 #define APLL_SAFE_HZ    (600 * 1000000)
  20 #define GPLL_HZ         (594 * 1000000)
  21 #define CPLL_HZ         (384 * 1000000)
  22
  23 /* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
  24 #define CPU_ACLK_HZ     297000000
  25 #define CPU_HCLK_HZ     148500000
  26 #define CPU_PCLK_HZ     74250000
  27 #define CPU_H2P_HZ      74250000
  28
  29 #define PERI_ACLK_HZ    148500000
  30 #define PERI_HCLK_HZ    148500000
  31 #define PERI_PCLK_HZ    74250000
  32
  33 /* Private data for the clock driver - used by rockchip_get_cru() */
  34 struct rk3066_clk_priv {
  35         struct rk3066_grf *grf;
  36         struct rk3066_cru *cru;
  37         ulong rate;
  38         bool has_bwadj;
  39 };
  40
  41 struct rk3066_cru {
  42         struct rk3066_pll {
  43                 u32 con0;
  44                 u32 con1;
  45                 u32 con2;
  46                 u32 con3;
  47         } pll[4];
  48         u32 cru_mode_con;
  49         u32 cru_clksel_con[35];
  50         u32 cru_clkgate_con[10];
  51         u32 reserved1[2];
  52         u32 cru_glb_srst_fst_value;
  53         u32 cru_glb_srst_snd_value;
  54         u32 reserved2[2];
  55         u32 cru_softrst_con[9];
  56         u32 cru_misc_con;
  57         u32 reserved3[2];
  58         u32 cru_glb_cnt_th;
  59 };
  60
  61 check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
  62
  63 /* CRU_CLKSEL0_CON */
  64 enum {
  65         REG(CPU_ACLK_PLL, 8, 8),
  66         CPU_ACLK_PLL_SELECT_APLL        = 0,
  67         CPU_ACLK_PLL_SELECT_GPLL,
  68
  69         REG(CORE_PERI_DIV, 7, 6),
  70
  71         REG(A9_CORE_DIV, 4, 0),
  72 };
  73
  74 /* CRU_CLKSEL1_CON */
  75 enum {
  76         REG(AHB2APB_DIV, 15, 14),
  77
  78         REG(CPU_PCLK_DIV, 13, 12),
  79
  80         REG(CPU_HCLK_DIV, 9, 8),
  81
  82         REG(CPU_ACLK_DIV, 2, 0),
  83 };
  84
  85 /* CRU_CLKSEL10_CON */
  86 enum {
  87         REG(PERI_SEL_PLL, 15, 15),
  88         PERI_SEL_CPLL           = 0,
  89         PERI_SEL_GPLL,
  90
  91         REG(PERI_PCLK_DIV, 13, 12),
  92
  93         REG(PERI_HCLK_DIV, 9, 8),
  94
  95         REG(PERI_ACLK_DIV, 4, 0),
  96 };
  97
  98 /* CRU_CLKSEL11_CON */
  99 enum {
 100         REG(MMC0_DIV, 5, 0),
 101 };
 102
 103 /* CRU_CLKSEL12_CON */
 104 enum {
 105         REG(UART_PLL, 15, 15),
 106         UART_PLL_SELECT_GENERAL = 0,
 107         UART_PLL_SELECT_CODEC,
 108
 109         REG(EMMC_DIV, 13, 8),
 110
 111         REG(SDIO_DIV, 5, 0),
 112 };
 113
 114 /* CRU_CLKSEL24_CON */
 115 enum {
 116         REG(SARADC_DIV, 15, 8),
 117 };
 118
 119 /* CRU_CLKSEL25_CON */
 120 enum {
 121         REG(SPI1_DIV, 14, 8),
 122
 123         REG(SPI0_DIV, 6, 0),
 124 };
 125
 126 /* CRU_CLKSEL34_CON */
 127 enum {
 128         REG(TSADC_DIV, 15, 0),
 129 };
 130
 131 /* CRU_MODE_CON */
 132 enum {
 133         REG(GPLL_MODE, 13, 12),
 134
 135         REG(CPLL_MODE, 9, 8),
 136
 137         REG(DPLL_MODE, 5, 4),
 138
 139         REG(APLL_MODE, 1, 0),
 140         PLL_MODE_SLOW           = 0,
 141         PLL_MODE_NORMAL,
 142         PLL_MODE_DEEP,
 143 };
 144
 145 /* CRU_APLL_CON0 */
 146 enum {
 147         REG(CLKR, 13, 8),
 148
 149         REG(CLKOD, 3, 0),
 150 };
 151
 152 /* CRU_APLL_CON1 */
 153 enum {
 154         REG(CLKF, 12, 0),
 155 };
 156
 157 #endif