arch/arm/include/asm/arch-rockchip/cru_rk3036.h

   1 /*
   2  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_CRU_RK3036_H
   7 #define _ASM_ARCH_CRU_RK3036_H
   8
   9 #include <common.h>
  10
  11 #define OSC_HZ          (24 * 1000 * 1000)
  12
  13 #define APLL_HZ         (600 * 1000000)
  14 #define GPLL_HZ         (594 * 1000000)
  15
  16 #define CORE_PERI_HZ    150000000
  17 #define CORE_ACLK_HZ    300000000
  18
  19 #define BUS_ACLK_HZ     148500000
  20 #define BUS_HCLK_HZ     148500000
  21 #define BUS_PCLK_HZ     74250000
  22
  23 #define PERI_ACLK_HZ    148500000
  24 #define PERI_HCLK_HZ    148500000
  25 #define PERI_PCLK_HZ    74250000
  26
  27 /* Private data for the clock driver - used by rockchip_get_cru() */
  28 struct rk3036_clk_priv {
  29         struct rk3036_cru *cru;
  30         ulong rate;
  31 };
  32
  33 struct rk3036_cru {
  34         struct rk3036_pll {
  35                 unsigned int con0;
  36                 unsigned int con1;
  37                 unsigned int con2;
  38                 unsigned int con3;
  39         } pll[4];
  40         unsigned int cru_mode_con;
  41         unsigned int cru_clksel_con[35];
  42         unsigned int cru_clkgate_con[11];
  43         unsigned int reserved;
  44         unsigned int cru_glb_srst_fst_value;
  45         unsigned int cru_glb_srst_snd_value;
  46         unsigned int reserved1[2];
  47         unsigned int cru_softrst_con[9];
  48         unsigned int cru_misc_con;
  49         unsigned int reserved2[2];
  50         unsigned int cru_glb_cnt_th;
  51         unsigned int cru_sdmmc_con[2];
  52         unsigned int cru_sdio_con[2];
  53         unsigned int cru_emmc_con[2];
  54         unsigned int reserved3;
  55         unsigned int cru_rst_st;
  56         unsigned int reserved4[0x23];
  57         unsigned int cru_pll_mask_con;
  58 };
  59 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
  60
  61 struct pll_div {
  62         u32 refdiv;
  63         u32 fbdiv;
  64         u32 postdiv1;
  65         u32 postdiv2;
  66         u32 frac;
  67 };
  68
  69 enum {
  70         /* PLLCON0*/
  71         PLL_POSTDIV1_SHIFT      = 12,
  72         PLL_POSTDIV1_MASK       = 7 << PLL_POSTDIV1_SHIFT,
  73         PLL_FBDIV_SHIFT         = 0,
  74         PLL_FBDIV_MASK          = 0xfff,
  75
  76         /* PLLCON1 */
  77         PLL_RST_SHIFT           = 14,
  78         PLL_DSMPD_SHIFT         = 12,
  79         PLL_DSMPD_MASK          = 1 << PLL_DSMPD_SHIFT,
  80         PLL_LOCK_STATUS_SHIFT   = 10,
  81         PLL_LOCK_STATUS_MASK    = 1 << PLL_LOCK_STATUS_SHIFT,
  82         PLL_POSTDIV2_SHIFT      = 6,
  83         PLL_POSTDIV2_MASK       = 7 << PLL_POSTDIV2_SHIFT,
  84         PLL_REFDIV_SHIFT        = 0,
  85         PLL_REFDIV_MASK         = 0x3f,
  86
  87         /* CRU_MODE */
  88         GPLL_MODE_SHIFT         = 12,
  89         GPLL_MODE_MASK          = 3 << GPLL_MODE_SHIFT,
  90         GPLL_MODE_SLOW          = 0,
  91         GPLL_MODE_NORM,
  92         GPLL_MODE_DEEP,
  93         DPLL_MODE_SHIFT         = 4,
  94         DPLL_MODE_MASK          = 1 << DPLL_MODE_SHIFT,
  95         DPLL_MODE_SLOW          = 0,
  96         DPLL_MODE_NORM,
  97         APLL_MODE_SHIFT         = 0,
  98         APLL_MODE_MASK          = 1 << APLL_MODE_SHIFT,
  99         APLL_MODE_SLOW          = 0,
 100         APLL_MODE_NORM,
 101
 102         /* CRU_CLK_SEL0_CON */
 103         BUS_ACLK_PLL_SEL_SHIFT  = 14,
 104         BUS_ACLK_PLL_SEL_MASK   = 3 << BUS_ACLK_PLL_SEL_SHIFT,
 105         BUS_ACLK_PLL_SEL_APLL   = 0,
 106         BUS_ACLK_PLL_SEL_DPLL,
 107         BUS_ACLK_PLL_SEL_GPLL,
 108         BUS_ACLK_DIV_SHIFT      = 8,
 109         BUS_ACLK_DIV_MASK       = 0x1f << BUS_ACLK_DIV_SHIFT,
 110         CORE_CLK_PLL_SEL_SHIFT  = 7,
 111         CORE_CLK_PLL_SEL_MASK   = 1 << CORE_CLK_PLL_SEL_SHIFT,
 112         CORE_CLK_PLL_SEL_APLL   = 0,
 113         CORE_CLK_PLL_SEL_GPLL,
 114         CORE_DIV_CON_SHIFT      = 0,
 115         CORE_DIV_CON_MASK       = 0x1f << CORE_DIV_CON_SHIFT,
 116
 117         /* CRU_CLK_SEL1_CON */
 118         BUS_PCLK_DIV_SHIFT      = 12,
 119         BUS_PCLK_DIV_MASK       = 7 << BUS_PCLK_DIV_SHIFT,
 120         BUS_HCLK_DIV_SHIFT      = 8,
 121         BUS_HCLK_DIV_MASK       = 3 << BUS_HCLK_DIV_SHIFT,
 122         CORE_ACLK_DIV_SHIFT     = 4,
 123         CORE_ACLK_DIV_MASK      = 7 << CORE_ACLK_DIV_SHIFT,
 124         CORE_PERI_DIV_SHIFT     = 0,
 125         CORE_PERI_DIV_MASK      = 0xf << CORE_PERI_DIV_SHIFT,
 126
 127         /* CRU_CLKSEL10_CON */
 128         PERI_PLL_SEL_SHIFT      = 14,
 129         PERI_PLL_SEL_MASK       = 3 << PERI_PLL_SEL_SHIFT,
 130         PERI_PLL_APLL           = 0,
 131         PERI_PLL_DPLL,
 132         PERI_PLL_GPLL,
 133         PERI_PCLK_DIV_SHIFT     = 12,
 134         PERI_PCLK_DIV_MASK      = 3 << PERI_PCLK_DIV_SHIFT,
 135         PERI_HCLK_DIV_SHIFT     = 8,
 136         PERI_HCLK_DIV_MASK      = 3 << PERI_HCLK_DIV_SHIFT,
 137         PERI_ACLK_DIV_SHIFT     = 0,
 138         PERI_ACLK_DIV_MASK      = 0x1f << PERI_ACLK_DIV_SHIFT,
 139
 140         /* CRU_CLKSEL11_CON */
 141         SDIO_DIV_SHIFT          = 8,
 142         SDIO_DIV_MASK           = 0x7f << SDIO_DIV_SHIFT,
 143         MMC0_DIV_SHIFT          = 0,
 144         MMC0_DIV_MASK           = 0x7f << MMC0_DIV_SHIFT,
 145
 146         /* CRU_CLKSEL12_CON */
 147         EMMC_PLL_SHIFT          = 12,
 148         EMMC_PLL_MASK           = 3 << EMMC_PLL_SHIFT,
 149         EMMC_SEL_APLL           = 0,
 150         EMMC_SEL_DPLL,
 151         EMMC_SEL_GPLL,
 152         EMMC_SEL_24M,
 153         SDIO_PLL_SHIFT          = 10,
 154         SDIO_PLL_MASK           = 3 << SDIO_PLL_SHIFT,
 155         SDIO_SEL_APLL           = 0,
 156         SDIO_SEL_DPLL,
 157         SDIO_SEL_GPLL,
 158         SDIO_SEL_24M,
 159         MMC0_PLL_SHIFT          = 8,
 160         MMC0_PLL_MASK           = 3 << MMC0_PLL_SHIFT,
 161         MMC0_SEL_APLL           = 0,
 162         MMC0_SEL_DPLL,
 163         MMC0_SEL_GPLL,
 164         MMC0_SEL_24M,
 165         EMMC_DIV_SHIFT          = 0,
 166         EMMC_DIV_MASK           = 0x7f << EMMC_DIV_SHIFT,
 167
 168         /* CRU_SOFTRST5_CON */
 169         DDRCTRL_PSRST_SHIFT     = 11,
 170         DDRCTRL_SRST_SHIFT      = 10,
 171         DDRPHY_PSRST_SHIFT      = 9,
 172         DDRPHY_SRST_SHIFT       = 8,
 173 };
 174 #endif