2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
14 * Added include for hardware.h (for __REG definition)
22 /* FIXME hack so that SA-1111.h will work [cb] */
25 typedef unsigned short Word16 ;
26 typedef unsigned int Word32 ;
28 typedef Word Quad [4] ;
29 typedef void *Address ;
30 typedef void (*ExcpHndlr) (void) ;
36 #ifdef CONFIG_CPU_MONAHANS
37 #define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */
38 #define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */
39 #define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */
40 #define PXA_CS2_PHYS 0x10000000 /* (64MB) */
41 #define PXA_CS3_PHYS 0x14000000 /* (64MB) */
42 #define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */
44 #define PXA_CS0_PHYS 0x00000000
45 #define PXA_CS1_PHYS 0x04000000
46 #define PXA_CS2_PHYS 0x08000000
47 #define PXA_CS3_PHYS 0x0C000000
48 #define PXA_CS4_PHYS 0x10000000
49 #define PXA_CS5_PHYS 0x14000000
50 #endif /* CONFIG_CPU_MONAHANS */
53 * Personal Computer Memory Card International Association (PCMCIA) sockets
55 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
56 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
57 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
58 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
59 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
61 #ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
62 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
63 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
64 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
65 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
68 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
69 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
70 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
71 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
73 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
74 (0x20000000 + (Nb)*PCMCIASp)
75 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
76 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
77 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
78 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
79 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
81 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
82 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
83 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
84 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
86 #ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
87 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
88 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
89 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
90 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
96 #define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
102 #define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */
103 #define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */
104 #define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */
105 #define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */
106 #define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */
107 #define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */
108 #define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */
109 #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
110 #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
111 #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
112 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
113 #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
114 #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
115 #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
116 #define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */
117 #define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */
118 #define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */
119 #define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */
120 #define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */
121 #define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */
122 #define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */
123 #define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */
124 #define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */
125 #define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */
126 #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
127 #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
128 #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
129 #endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
131 #define DCSR(x) (0x40000000 | ((x) << 2))
133 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
135 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
137 #if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
138 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
139 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
140 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
141 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
142 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
143 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
144 #define DCSR_ENRINTR (1 << 9) /* The end of Receive */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
149 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
150 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
151 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
153 #define DINT 0x400000f0 /* DMA Interrupt Register */
155 #define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */
156 #define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */
157 #define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */
158 #define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */
159 #define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */
160 #define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */
161 #define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */
162 #define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */
163 #define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */
164 #define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */
165 #define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */
166 #define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */
167 #define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */
168 #define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */
169 #define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */
170 #define DRCMR15 0x4000013c /* Reserved */
171 #define DRCMR16 0x40000140 /* Reserved */
172 #define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */
173 #define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */
174 #define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */
175 #define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */
176 #define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */
177 #define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */
178 #define DRCMR23 0x4000015c /* Reserved */
179 #define DRCMR24 0x40000160 /* Reserved */
180 #define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */
181 #define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */
182 #define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */
183 #define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */
184 #define DRCMR29 0x40000174 /* Reserved */
185 #define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */
186 #define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */
187 #define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */
188 #define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */
189 #define DRCMR34 0x40000188 /* Reserved */
190 #define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */
191 #define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */
192 #define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */
193 #define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */
194 #define DRCMR39 0x4000019C /* Reserved */
196 #define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */
197 #define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */
198 #define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */
200 #define DRCMRRXSADR DRCMR2
201 #define DRCMRTXSADR DRCMR3
202 #define DRCMRRXBTRBR DRCMR4
203 #define DRCMRTXBTTHR DRCMR5
204 #define DRCMRRXFFRBR DRCMR6
205 #define DRCMRTXFFTHR DRCMR7
206 #define DRCMRRXMCDR DRCMR8
207 #define DRCMRRXMODR DRCMR9
208 #define DRCMRTXMODR DRCMR10
209 #define DRCMRRXPCDR DRCMR11
210 #define DRCMRTXPCDR DRCMR12
211 #define DRCMRRXSSDR DRCMR13
212 #define DRCMRTXSSDR DRCMR14
213 #define DRCMRRXICDR DRCMR17
214 #define DRCMRTXICDR DRCMR18
215 #define DRCMRRXSTRBR DRCMR19
216 #define DRCMRTXSTTHR DRCMR20
217 #define DRCMRRXMMC DRCMR21
218 #define DRCMRTXMMC DRCMR22
220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
221 #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
223 #define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */
224 #define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */
225 #define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */
226 #define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */
227 #define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */
228 #define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */
229 #define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */
230 #define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */
231 #define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */
232 #define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */
233 #define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */
234 #define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */
235 #define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */
236 #define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */
237 #define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */
238 #define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */
239 #define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */
240 #define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */
241 #define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */
242 #define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */
243 #define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */
244 #define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */
245 #define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */
246 #define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */
247 #define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */
248 #define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */
249 #define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */
250 #define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */
251 #define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */
252 #define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */
253 #define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */
254 #define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */
255 #define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */
256 #define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */
257 #define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */
258 #define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */
259 #define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */
260 #define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */
261 #define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */
262 #define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */
263 #define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */
264 #define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */
265 #define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */
266 #define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */
267 #define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */
268 #define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */
269 #define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */
270 #define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */
271 #define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */
272 #define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */
273 #define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */
274 #define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */
275 #define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */
276 #define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */
277 #define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */
278 #define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */
279 #define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */
280 #define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */
281 #define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */
282 #define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */
283 #define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */
284 #define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */
285 #define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */
286 #define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */
288 #define DDADR(x) (0x40000200 | ((x) << 4))
289 #define DSADR(x) (0x40000204 | ((x) << 4))
290 #define DTADR(x) (0x40000208 | ((x) << 4))
291 #define DCMD(x) (0x4000020c | ((x) << 4))
293 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
294 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
296 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
297 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
299 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
300 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
301 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
303 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
304 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
305 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
306 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
307 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
308 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
311 /* default combinations */
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
314 #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
316 /******************************************************************************/
320 /* Full Function UART (FFUART) */
322 #define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
323 #define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
324 #define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
325 #define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
326 #define FFFCR 0x40100008 /* FIFO Control Register (write only) */
327 #define FFLCR 0x4010000C /* Line Control Register (read/write) */
328 #define FFMCR 0x40100010 /* Modem Control Register (read/write) */
329 #define FFLSR 0x40100014 /* Line Status Register (read only) */
330 #define FFMSR 0x40100018 /* Modem Status Register (read only) */
331 #define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
332 #define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
333 #define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
334 #define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
336 /* Bluetooth UART (BTUART) */
338 #define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
339 #define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
340 #define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
341 #define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
342 #define BTFCR 0x40200008 /* FIFO Control Register (write only) */
343 #define BTLCR 0x4020000C /* Line Control Register (read/write) */
344 #define BTMCR 0x40200010 /* Modem Control Register (read/write) */
345 #define BTLSR 0x40200014 /* Line Status Register (read only) */
346 #define BTMSR 0x40200018 /* Modem Status Register (read only) */
347 #define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
348 #define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
349 #define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
350 #define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
352 /* Standard UART (STUART) */
354 #define STRBR 0x40700000 /* Receive Buffer Register (read only) */
355 #define STTHR 0x40700000 /* Transmit Holding Register (write only) */
356 #define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
357 #define STIIR 0x40700008 /* Interrupt ID Register (read only) */
358 #define STFCR 0x40700008 /* FIFO Control Register (write only) */
359 #define STLCR 0x4070000C /* Line Control Register (read/write) */
360 #define STMCR 0x40700010 /* Modem Control Register (read/write) */
361 #define STLSR 0x40700014 /* Line Status Register (read only) */
362 #define STMSR 0x40700018 /* Reserved */
363 #define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
364 #define STISR 0x40700020 /* Infrared Selection Register (read/write) */
365 #define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
366 #define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
368 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
369 #define IER_UUE (1 << 6) /* UART Unit Enable */
370 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
371 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
372 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
373 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
374 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
375 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
377 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
378 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
379 #define IIR_TOD (1 << 3) /* Time Out Detected */
380 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
381 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
382 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
384 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
385 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
386 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
387 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
388 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
389 #define FCR_ITL_1 (0)
390 #define FCR_ITL_8 (FCR_ITL1)
391 #define FCR_ITL_16 (FCR_ITL2)
392 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
394 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
395 #define LCR_SB (1 << 6) /* Set Break */
396 #define LCR_STKYP (1 << 5) /* Sticky Parity */
397 #define LCR_EPS (1 << 4) /* Even Parity Select */
398 #define LCR_PEN (1 << 3) /* Parity Enable */
399 #define LCR_STB (1 << 2) /* Stop Bit */
400 #define LCR_WLS1 (1 << 1) /* Word Length Select */
401 #define LCR_WLS0 (1 << 0) /* Word Length Select */
403 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
404 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
405 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
406 #define LSR_BI (1 << 4) /* Break Interrupt */
407 #define LSR_FE (1 << 3) /* Framing Error */
408 #define LSR_PE (1 << 2) /* Parity Error */
409 #define LSR_OE (1 << 1) /* Overrun Error */
410 #define LSR_DR (1 << 0) /* Data Ready */
412 #define MCR_LOOP (1 << 4) /* */
413 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
414 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
415 #define MCR_RTS (1 << 1) /* Request to Send */
416 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
418 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
419 #define MSR_RI (1 << 6) /* Ring Indicator */
420 #define MSR_DSR (1 << 5) /* Data Set Ready */
421 #define MSR_CTS (1 << 4) /* Clear To Send */
422 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
423 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
424 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
425 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
427 /******************************************************************************/
429 * IrSR (Infrared Selection Register)
431 #define IrSR_OFFSET 0x20
433 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
434 #define IrSR_RXPL_POS_IS_ZERO 0x0
435 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
436 #define IrSR_TXPL_POS_IS_ZERO 0x0
437 #define IrSR_XMODE_PULSE_1_6 (1<<2)
438 #define IrSR_XMODE_PULSE_3_16 0x0
439 #define IrSR_RCVEIR_IR_MODE (1<<1)
440 #define IrSR_RCVEIR_UART_MODE 0x0
441 #define IrSR_XMITIR_IR_MODE (1<<0)
442 #define IrSR_XMITIR_UART_MODE 0x0
444 #define IrSR_IR_RECEIVE_ON (\
445 IrSR_RXPL_NEG_IS_ZERO | \
446 IrSR_TXPL_POS_IS_ZERO | \
447 IrSR_XMODE_PULSE_3_16 | \
448 IrSR_RCVEIR_IR_MODE | \
449 IrSR_XMITIR_UART_MODE)
451 #define IrSR_IR_TRANSMIT_ON (\
452 IrSR_RXPL_NEG_IS_ZERO | \
453 IrSR_TXPL_POS_IS_ZERO | \
454 IrSR_XMODE_PULSE_3_16 | \
455 IrSR_RCVEIR_UART_MODE | \
459 * Serial Audio Controller
461 /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
462 * short defines because there is too much chance of namespace collision
464 #define SACR0 0x40400000 /* Global Control Register */
465 #define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */
466 #define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
467 #define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */
468 #define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */
469 #define SADIV 0x40400060 /* Audio Clock Divider Register. */
470 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */
473 * AC97 Controller registers
475 #define POCR 0x40500000 /* PCM Out Control Register */
476 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
478 #define PICR 0x40500004 /* PCM In Control Register */
479 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
481 #define MCCR 0x40500008 /* Mic In Control Register */
482 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
484 #define GCR 0x4050000C /* Global Control Register */
485 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
486 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
487 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
488 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
489 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
490 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
491 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
492 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
493 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
494 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
496 #define POSR 0x40500010 /* PCM Out Status Register */
497 #define POSR_FIFOE (1 << 4) /* FIFO error */
499 #define PISR 0x40500014 /* PCM In Status Register */
500 #define PISR_FIFOE (1 << 4) /* FIFO error */
502 #define MCSR 0x40500018 /* Mic In Status Register */
503 #define MCSR_FIFOE (1 << 4) /* FIFO error */
505 #define GSR 0x4050001C /* Global Status Register */
506 #define GSR_CDONE (1 << 19) /* Command Done */
507 #define GSR_SDONE (1 << 18) /* Status Done */
508 #define GSR_RDCS (1 << 15) /* Read Completion Status */
509 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
510 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
511 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
512 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
513 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
514 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
515 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
516 #define GSR_MINT (1 << 7) /* Mic In Interrupt */
517 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
518 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
519 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
520 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
521 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
523 #define CAR 0x40500020 /* CODEC Access Register */
524 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
526 #define PCDR 0x40500040 /* PCM FIFO Data Register */
527 #define MCDR 0x40500060 /* Mic-in FIFO Data Register */
529 #define MOCR 0x40500100 /* Modem Out Control Register */
530 #define MOCR_FEIE (1 << 3) /* FIFO Error */
532 #define MICR 0x40500108 /* Modem In Control Register */
533 #define MICR_FEIE (1 << 3) /* FIFO Error */
535 #define MOSR 0x40500110 /* Modem Out Status Register */
536 #define MOSR_FIFOE (1 << 4) /* FIFO error */
538 #define MISR 0x40500118 /* Modem In Status Register */
539 #define MISR_FIFOE (1 << 4) /* FIFO error */
541 #define MODR 0x40500140 /* Modem FIFO Data Register */
543 #define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */
544 #define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */
545 #define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */
546 #define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */
550 * USB Device Controller
552 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
554 #define UDCCR 0x40600000 /* UDC Control Register */
555 #define UDCCR_UDE (1 << 0) /* UDC enable */
556 #define UDCCR_UDA (1 << 1) /* UDC active */
557 #define UDCCR_RSM (1 << 2) /* Device resume */
558 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */
559 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */
560 #define UDCCR_RESIR (1 << 29) /* Resume interrupt request */
561 #define UDCCR_SUSIR (1 << 28) /* Suspend interrupt request */
562 #define UDCCR_SM (1 << 28) /* Suspend interrupt mask */
563 #define UDCCR_RSTIR (1 << 27) /* Reset interrupt request */
564 #define UDCCR_REM (1 << 27) /* Reset interrupt mask */
565 #define UDCCR_RM (1 << 29) /* resume interrupt mask */
566 #define UDCCR_SRM (UDCCR_SM|UDCCR_RM)
567 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
568 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */
569 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */
570 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */
571 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
572 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
573 #define UDCCR_ACN_S 11
574 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
575 #define UDCCR_AIN_S 8
576 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */
577 #define UDCCR_AAISN_S 5
579 #define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */
580 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
581 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
582 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
583 #define UDCCS0_DRWF (1 << 16) /* Device remote wakeup feature */
584 #define UDCCS0_SST (1 << 4) /* Sent stall */
585 #define UDCCS0_FST (1 << 5) /* Force stall */
586 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
587 #define UDCCS0_SA (1 << 7) /* Setup active */
589 /* Bulk IN - Endpoint 1,6,11 */
590 #define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */
591 #define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */
592 #define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */
594 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
595 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
596 #define UDCCS_BI_FTF (1 << 8) /* Flush Tx FIFO */
597 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
598 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
599 #define UDCCS_BI_FST (1 << 5) /* Force stall */
600 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
602 /* Bulk OUT - Endpoint 2,7,12 */
603 #define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */
604 #define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */
605 #define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */
607 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
608 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
609 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
610 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
611 #define UDCCS_BO_FST (1 << 5) /* Force stall */
612 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
613 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
615 /* Isochronous IN - Endpoint 3,8,13 */
616 #define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */
617 #define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */
618 #define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */
620 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
621 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
622 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
623 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
624 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
626 /* Isochronous OUT - Endpoint 4,9,14 */
627 #define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */
628 #define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */
629 #define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */
631 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
632 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
633 #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
634 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
635 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
636 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
638 /* Interrupt IN - Endpoint 5,10,15 */
639 #define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
640 #define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
641 #define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */
643 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
644 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
645 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
646 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
647 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
648 #define UDCCS_INT_FST (1 << 5) /* Force stall */
649 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
651 #define UFNRH 0x40600060 /* UDC Frame Number Register High */
652 #define UFNRL 0x40600014 /* UDC Frame Number Register Low */
653 #define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */
654 #define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */
655 #define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */
656 #define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */
657 #define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */
658 #define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */
659 #define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */
660 #define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */
661 #define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */
662 #define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */
663 #define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */
664 #define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */
665 #define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */
666 #define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */
667 #define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */
668 #define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */
669 #define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */
670 #define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */
671 #define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */
672 #define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */
673 #define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */
674 #define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */
676 #define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */
678 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
679 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
680 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
681 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
682 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
683 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
684 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
685 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
687 #define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */
689 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
690 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
691 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
692 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
693 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
694 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
695 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
696 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
698 #define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */
700 #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
701 #define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */
702 #define USIR0_IR2 (1 << 4) /* Interrup request ep 2 */
703 #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
704 #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
705 #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
706 #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
707 #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
709 #define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */
711 #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
712 #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
713 #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
714 #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
715 #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
716 #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
717 #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
718 #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
721 #define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */
722 #define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */
723 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
724 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
726 #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
727 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
728 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
729 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
730 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
731 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
733 #define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */
734 #define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */
735 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
736 #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
737 #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
738 #define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
739 #define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
740 #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
743 #define UDCFNR 0x40600014 /* UDC Frame Number Register */
744 #define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */
745 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
746 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */
747 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */
748 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
749 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
750 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */
751 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
752 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */
753 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */
754 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
755 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */
756 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */
757 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
759 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
760 #define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
762 #define UDCCSR0_SA (1 << 7) /* Setup Active */
763 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
764 #define UDCCSR0_FST (1 << 5) /* Force Stall */
765 #define UDCCSR0_SST (1 << 4) /* Sent Stall */
766 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
767 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
768 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
769 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
771 #define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */
772 #define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */
773 #define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */
774 #define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */
775 #define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */
776 #define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */
777 #define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */
778 #define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */
779 #define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */
780 #define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */
781 #define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */
782 #define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */
783 #define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */
784 #define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */
785 #define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */
786 #define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */
787 #define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */
788 #define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */
789 #define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */
790 #define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */
791 #define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */
792 #define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */
793 #define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */
795 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
796 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
797 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
798 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
799 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
800 #define UDCCSR_FST (1 << 5) /* Force STALL */
801 #define UDCCSR_SST (1 << 4) /* Sent STALL */
802 #define UDCCSR_DME (1 << 3) /* DMA Enable */
803 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
804 #define UDCCSR_PC (1 << 1) /* Packet Complete */
805 #define UDCCSR_FS (1 << 0) /* FIFO needs service */
807 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
808 #define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
809 #define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
810 #define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
811 #define UDCBCRC 0x4060020C /* Byte Count Register - EPC */
812 #define UDCBCRD 0x40600210 /* Byte Count Register - EPD */
813 #define UDCBCRE 0x40600214 /* Byte Count Register - EPE */
814 #define UDCBCRF 0x40600218 /* Byte Count Register - EPF */
815 #define UDCBCRG 0x4060021C /* Byte Count Register - EPG */
816 #define UDCBCRH 0x40600220 /* Byte Count Register - EPH */
817 #define UDCBCRI 0x40600224 /* Byte Count Register - EPI */
818 #define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */
819 #define UDCBCRK 0x4060022C /* Byte Count Register - EPK */
820 #define UDCBCRL 0x40600230 /* Byte Count Register - EPL */
821 #define UDCBCRM 0x40600234 /* Byte Count Register - EPM */
822 #define UDCBCRN 0x40600238 /* Byte Count Register - EPN */
823 #define UDCBCRP 0x4060023C /* Byte Count Register - EPP */
824 #define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */
825 #define UDCBCRR 0x40600244 /* Byte Count Register - EPR */
826 #define UDCBCRS 0x40600248 /* Byte Count Register - EPS */
827 #define UDCBCRT 0x4060024C /* Byte Count Register - EPT */
828 #define UDCBCRU 0x40600250 /* Byte Count Register - EPU */
829 #define UDCBCRV 0x40600254 /* Byte Count Register - EPV */
830 #define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
831 #define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
833 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
834 #define UDCDR0 0x40600300 /* Data Register - EP0 */
835 #define UDCDRA 0x40600304 /* Data Register - EPA */
836 #define UDCDRB 0x40600308 /* Data Register - EPB */
837 #define UDCDRC 0x4060030C /* Data Register - EPC */
838 #define UDCDRD 0x40600310 /* Data Register - EPD */
839 #define UDCDRE 0x40600314 /* Data Register - EPE */
840 #define UDCDRF 0x40600318 /* Data Register - EPF */
841 #define UDCDRG 0x4060031C /* Data Register - EPG */
842 #define UDCDRH 0x40600320 /* Data Register - EPH */
843 #define UDCDRI 0x40600324 /* Data Register - EPI */
844 #define UDCDRJ 0x40600328 /* Data Register - EPJ */
845 #define UDCDRK 0x4060032C /* Data Register - EPK */
846 #define UDCDRL 0x40600330 /* Data Register - EPL */
847 #define UDCDRM 0x40600334 /* Data Register - EPM */
848 #define UDCDRN 0x40600338 /* Data Register - EPN */
849 #define UDCDRP 0x4060033C /* Data Register - EPP */
850 #define UDCDRQ 0x40600340 /* Data Register - EPQ */
851 #define UDCDRR 0x40600344 /* Data Register - EPR */
852 #define UDCDRS 0x40600348 /* Data Register - EPS */
853 #define UDCDRT 0x4060034C /* Data Register - EPT */
854 #define UDCDRU 0x40600350 /* Data Register - EPU */
855 #define UDCDRV 0x40600354 /* Data Register - EPV */
856 #define UDCDRW 0x40600358 /* Data Register - EPW */
857 #define UDCDRX 0x4060035C /* Data Register - EPX */
859 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
860 #define UDCCRA 0x40600404 /* Configuration register EPA */
861 #define UDCCRB 0x40600408 /* Configuration register EPB */
862 #define UDCCRC 0x4060040C /* Configuration register EPC */
863 #define UDCCRD 0x40600410 /* Configuration register EPD */
864 #define UDCCRE 0x40600414 /* Configuration register EPE */
865 #define UDCCRF 0x40600418 /* Configuration register EPF */
866 #define UDCCRG 0x4060041C /* Configuration register EPG */
867 #define UDCCRH 0x40600420 /* Configuration register EPH */
868 #define UDCCRI 0x40600424 /* Configuration register EPI */
869 #define UDCCRJ 0x40600428 /* Configuration register EPJ */
870 #define UDCCRK 0x4060042C /* Configuration register EPK */
871 #define UDCCRL 0x40600430 /* Configuration register EPL */
872 #define UDCCRM 0x40600434 /* Configuration register EPM */
873 #define UDCCRN 0x40600438 /* Configuration register EPN */
874 #define UDCCRP 0x4060043C /* Configuration register EPP */
875 #define UDCCRQ 0x40600440 /* Configuration register EPQ */
876 #define UDCCRR 0x40600444 /* Configuration register EPR */
877 #define UDCCRS 0x40600448 /* Configuration register EPS */
878 #define UDCCRT 0x4060044C /* Configuration register EPT */
879 #define UDCCRU 0x40600450 /* Configuration register EPU */
880 #define UDCCRV 0x40600454 /* Configuration register EPV */
881 #define UDCCRW 0x40600458 /* Configuration register EPW */
882 #define UDCCRX 0x4060045C /* Configuration register EPX */
884 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */
885 #define UDCCONR_CN_S (25)
886 #define UDCCONR_IN (0x07 << 22) /* Interface Number */
887 #define UDCCONR_IN_S (22)
888 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
889 #define UDCCONR_AISN_S (19)
890 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
891 #define UDCCONR_EN_S (15)
892 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
893 #define UDCCONR_ET_S (13)
894 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
895 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
896 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
897 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */
898 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */
899 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
900 #define UDCCONR_MPS_S (2)
901 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
902 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
905 #define UDC_INT_FIFOERROR (0x2)
906 #define UDC_INT_PACKETCMP (0x1)
907 #define UDC_FNR_MASK (0x7ff)
908 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
909 #define UDC_BCR_MASK (0x3ff)
911 #endif /* CONFIG_PXA27X */
913 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
915 /******************************************************************************/
917 * USB Host Controller
919 #define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
920 #define UHCREV 0x4C000000
921 #define UHCHCON 0x4C000004
922 #define UHCCOMS 0x4C000008
923 #define UHCINTS 0x4C00000C
924 #define UHCINTE 0x4C000010
925 #define UHCINTD 0x4C000014
926 #define UHCHCCA 0x4C000018
927 #define UHCPCED 0x4C00001C
928 #define UHCCHED 0x4C000020
929 #define UHCCCED 0x4C000024
930 #define UHCBHED 0x4C000028
931 #define UHCBCED 0x4C00002C
932 #define UHCDHEAD 0x4C000030
933 #define UHCFMI 0x4C000034
934 #define UHCFMR 0x4C000038
935 #define UHCFMN 0x4C00003C
936 #define UHCPERS 0x4C000040
937 #define UHCLST 0x4C000044
938 #define UHCRHDA 0x4C000048
939 #define UHCRHDB 0x4C00004C
940 #define UHCRHS 0x4C000050
941 #define UHCRHPS1 0x4C000054
942 #define UHCRHPS2 0x4C000058
943 #define UHCRHPS3 0x4C00005C
944 #define UHCSTAT 0x4C000060
945 #define UHCHR 0x4C000064
946 #define UHCHIE 0x4C000068
947 #define UHCHIT 0x4C00006C
949 #define UHCHR_FSBIR (1<<0)
950 #define UHCHR_FHR (1<<1)
951 #define UHCHR_CGR (1<<2)
952 #define UHCHR_SSDC (1<<3)
953 #define UHCHR_UIT (1<<4)
954 #define UHCHR_SSE (1<<5)
955 #define UHCHR_PSPL (1<<6)
956 #define UHCHR_PCPL (1<<7)
957 #define UHCHR_SSEP0 (1<<9)
958 #define UHCHR_SSEP1 (1<<10)
959 #define UHCHR_SSEP2 (1<<11)
961 #define UHCHIE_UPRIE (1<<13)
962 #define UHCHIE_UPS2IE (1<<12)
963 #define UHCHIE_UPS1IE (1<<11)
964 #define UHCHIE_TAIE (1<<10)
965 #define UHCHIE_HBAIE (1<<8)
966 #define UHCHIE_RWIE (1<<7)
968 #define UP2OCR 0x40600020
970 #define UP2OCR_HXOE (1<<17)
971 #define UP2OCR_HXS (1<<16)
972 #define UP2OCR_IDON (1<<10)
973 #define UP2OCR_EXSUS (1<<9)
974 #define UP2OCR_EXSP (1<<8)
975 #define UP2OCR_DMSTATE (1<<7)
976 #define UP2OCR_VPM (1<<6)
977 #define UP2OCR_DPSTATE (1<<5)
978 #define UP2OCR_DPPUE (1<<4)
979 #define UP2OCR_DMPDE (1<<3)
980 #define UP2OCR_DPPDE (1<<2)
981 #define UP2OCR_CPVPE (1<<1)
982 #define UP2OCR_CPVEN (1<<0)
984 #endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
986 /******************************************************************************/
988 * Fast Infrared Communication Port
990 #define ICCR0 0x40800000 /* ICP Control Register 0 */
991 #define ICCR1 0x40800004 /* ICP Control Register 1 */
992 #define ICCR2 0x40800008 /* ICP Control Register 2 */
993 #define ICDR 0x4080000c /* ICP Data Register */
994 #define ICSR0 0x40800014 /* ICP Status Register 0 */
995 #define ICSR1 0x40800018 /* ICP Status Register 1 */
1000 #define RCNR 0x40900000 /* RTC Count Register */
1001 #define RTAR 0x40900004 /* RTC Alarm Register */
1002 #define RTSR 0x40900008 /* RTC Status Register */
1003 #define RTTR 0x4090000C /* RTC Timer Trim Register */
1004 #define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */
1005 #define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */
1006 #define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */
1007 #define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */
1008 #define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */
1009 #define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */
1010 #define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */
1011 #define RDCR 0x40900010 /* RTC Day Count Register. */
1012 #define RYCR 0x40900014 /* RTC Year Count Register. */
1013 #define SWCR 0x40900028 /* Stopwatch Count Register */
1014 #define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */
1016 #define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
1017 #define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
1018 #define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
1019 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
1020 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
1021 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1022 #define RTSR_AL (1 << 0) /* RTC alarm detected */
1024 /******************************************************************************/
1026 * OS Timer & Match Registers
1028 #define OSMR0 0x40A00000 /* OS Timer Match Register 0 */
1029 #define OSMR1 0x40A00004 /* OS Timer Match Register 1 */
1030 #define OSMR2 0x40A00008 /* OS Timer Match Register 2 */
1031 #define OSMR3 0x40A0000C /* OS Timer Match Register 3 */
1032 #define OSCR 0x40A00010 /* OS Timer Counter Register */
1033 #define OSSR 0x40A00014 /* OS Timer Status Register */
1034 #define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */
1035 #define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */
1037 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1038 #define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */
1039 #define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */
1040 #define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */
1041 #define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */
1042 #define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */
1043 #define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */
1044 #define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */
1045 #define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */
1047 #define OSMR4 0x40A00080 /* OS Timer Match Register 4 */
1048 #define OSMR5 0x40A00084 /* OS Timer Match Register 5 */
1049 #define OSMR6 0x40A00088 /* OS Timer Match Register 6 */
1050 #define OSMR7 0x40A0008C /* OS Timer Match Register 7 */
1051 #define OSMR8 0x40A00090 /* OS Timer Match Register 8 */
1052 #define OSMR9 0x40A00094 /* OS Timer Match Register 9 */
1053 #define OSMR10 0x40A00098 /* OS Timer Match Register 10 */
1054 #define OSMR11 0x40A0009C /* OS Timer Match Register 11 */
1056 #define OMCR4 0x40A000C0 /* OS Match Control Register 4 */
1057 #define OMCR5 0x40A000C4 /* OS Match Control Register 5 */
1058 #define OMCR6 0x40A000C8 /* OS Match Control Register 6 */
1059 #define OMCR7 0x40A000CC /* OS Match Control Register 7 */
1060 #define OMCR8 0x40A000D0 /* OS Match Control Register 8 */
1061 #define OMCR9 0x40A000D4 /* OS Match Control Register 9 */
1062 #define OMCR10 0x40A000D8 /* OS Match Control Register 10 */
1063 #define OMCR11 0x40A000DC /* OS Match Control Register 11 */
1065 #endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
1067 #define OSSR_M4 (1 << 4) /* Match status channel 4 */
1068 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
1069 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
1070 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
1071 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
1073 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
1075 #define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */
1076 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
1077 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
1078 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
1079 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1081 #define OSCR_CLK_FREQ 3250
1083 /******************************************************************************/
1088 #if defined(CONFIG_CPU_MONAHANS)
1089 #define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */
1090 #define ACSR 0x41340004 /* Application Subsystem Clock Status Register */
1091 #define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */
1092 #define CKENA 0x4134000C /* A Clock Enable Register */
1093 #define CKENB 0x41340010 /* B Clock Enable Register */
1094 #define AC97_DIV 0x41340014 /* AC97 clock divisor value register */
1096 #define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
1097 #define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
1098 #define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
1099 #define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
1100 #define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
1101 #define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1102 #define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
1103 #define ACCR_XPDIS (1 << 31)
1104 #define ACCR_SPDIS (1 << 30)
1105 #define ACCR_13MEND1 (1 << 27)
1106 #define ACCR_D0CS (1 << 26)
1107 #define ACCR_13MEND2 (1 << 21)
1108 #define ACCR_PCCE (1 << 11)
1110 #define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
1111 #define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
1112 #define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
1113 #define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
1114 #define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
1115 #define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
1116 #define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
1117 #define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
1118 #define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
1119 #define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
1120 #define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
1121 #define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
1122 #define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
1123 #define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
1124 #define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
1125 #define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
1126 #define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
1127 #define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
1128 #define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
1129 #define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
1130 #define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
1131 #define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
1132 #define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
1133 #define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
1134 #define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
1135 #define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
1136 #define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
1137 #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
1139 #define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
1140 #define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
1141 #define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
1142 #define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
1143 #define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
1144 #define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
1145 #define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
1147 #else /* if defined CONFIG_CPU_MONAHANS */
1149 #define CCCR 0x41300000 /* Core Clock Configuration Register */
1150 #define CKEN 0x41300004 /* Clock Enable Register */
1151 #define OSCC 0x41300008 /* Oscillator Configuration Register */
1152 #define CCSR 0x4130000C /* Core Clock Status Register */
1154 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1155 #define CKEN22_MEMC (1 << 22) /* Memory Controler */
1156 #define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
1157 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1158 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1159 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1160 #define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
1161 #define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
1162 #define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
1163 #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1165 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1166 #if !defined(CONFIG_PXA27X)
1167 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1169 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1171 #define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
1172 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1173 #define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
1174 #define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
1175 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1176 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1177 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1178 #define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
1179 #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
1180 #define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
1181 #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
1182 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1183 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1184 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1185 #if defined(CONFIG_PXA27X)
1186 #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1187 #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
1189 #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
1190 #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1191 #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1192 #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1193 #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1194 #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
1195 #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
1196 #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
1198 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1199 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1201 #if !defined(CONFIG_PXA27X)
1202 #define CCCR_L09 (0x1F)
1203 #define CCCR_L27 (0x1)
1204 #define CCCR_L32 (0x2)
1205 #define CCCR_L36 (0x3)
1206 #define CCCR_L40 (0x4)
1207 #define CCCR_L45 (0x5)
1209 #define CCCR_M1 (0x1 << 5)
1210 #define CCCR_M2 (0x2 << 5)
1211 #define CCCR_M4 (0x3 << 5)
1213 #define CCCR_N10 (0x2 << 7)
1214 #define CCCR_N15 (0x3 << 7)
1215 #define CCCR_N20 (0x4 << 7)
1216 #define CCCR_N25 (0x5 << 7)
1217 #define CCCR_N30 (0x6 << 7)
1220 #endif /* CONFIG_CPU_MONAHANS */
1222 /******************************************************************************/
1224 * Pulse Width Modulator
1226 #define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */
1227 #define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */
1228 #define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */
1230 #define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */
1231 #define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */
1232 #define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */
1234 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1235 #define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */
1236 #define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */
1237 #define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */
1239 #define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */
1240 #define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */
1241 #define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */
1242 #endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
1245 * Interrupt Controller
1247 #define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */
1248 #define ICMR 0x40D00004 /* Interrupt Controller Mask Register */
1249 #define ICLR 0x40D00008 /* Interrupt Controller Level Register */
1250 #define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */
1251 #define ICPR 0x40D00010 /* Interrupt Controller Pending Register */
1252 #define ICCR 0x40D00014 /* Interrupt Controller Control Register */
1254 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1255 #define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */
1256 #define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */
1257 #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
1258 #define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */
1259 #define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */
1260 #define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */
1261 #endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
1263 /******************************************************************************/
1265 * General Purpose I/O
1267 #define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */
1268 #define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */
1269 #define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */
1271 #define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */
1272 #define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */
1273 #define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */
1275 #define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */
1276 #define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */
1277 #define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */
1279 #define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */
1280 #define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */
1281 #define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */
1283 #define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1284 #define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1285 #define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1287 #define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1288 #define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1289 #define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1291 #define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */
1292 #define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */
1293 #define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */
1295 #define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */
1296 #define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */
1297 #define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */
1298 #define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */
1299 #define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */
1300 #define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */
1302 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1303 #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
1304 #define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */
1305 #define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */
1306 #define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */
1307 #define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1308 #define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1309 #define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */
1310 #define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */
1311 #define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */
1312 #endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
1314 #ifdef CONFIG_CPU_MONAHANS
1315 #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
1316 #define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */
1317 #define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */
1318 #define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */
1320 #define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
1321 #define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
1322 #define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
1323 #define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
1325 #define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
1326 #define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
1327 #define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
1328 #define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
1330 #define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
1331 #define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
1332 #define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
1333 #define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
1335 #define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
1336 #define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
1337 #define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
1338 #define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
1340 #define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
1341 #define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
1342 #define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
1343 #define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
1345 #define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3)
1346 #define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3)
1349 #define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3))
1350 #define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3))
1351 #define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3))
1352 #define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3))
1353 #define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3))
1354 #define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3))
1355 #define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3))
1356 #define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2))
1358 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1359 #define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
1360 #define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
1361 #define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
1362 #define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
1363 #define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
1364 #define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
1365 #define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
1366 #define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \
1367 ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
1369 #define GPLR(x) _GPLR(x)
1370 #define GPDR(x) _GPDR(x)
1371 #define GPSR(x) _GPSR(x)
1372 #define GPCR(x) _GPCR(x)
1373 #define GRER(x) _GRER(x)
1374 #define GFER(x) _GFER(x)
1375 #define GEDR(x) _GEDR(x)
1376 #define GAFR(x) _GAFR(x)
1379 #define GPIO_bit(x) (1 << ((x) & 0x1f))
1381 /******************************************************************************/
1383 * Multi-function Pin Registers:
1386 #if defined(CONFIG_CPU_PXA320)
1387 #define DF_IO0 0x40e1024c
1388 #define DF_IO1 0x40e10254
1389 #define DF_IO2 0x40e1025c
1390 #define DF_IO3 0x40e10264
1391 #define DF_IO4 0x40e1026c
1392 #define DF_IO5 0x40e10274
1393 #define DF_IO6 0x40e1027c
1394 #define DF_IO7 0x40e10284
1395 #define DF_IO8 0x40e10250
1396 #define DF_IO9 0x40e10258
1397 #define DF_IO10 0x40e10260
1398 #define DF_IO11 0x40e10268
1399 #define DF_IO12 0x40e10270
1400 #define DF_IO13 0x40e10278
1401 #define DF_IO14 0x40e10280
1402 #define DF_IO15 0x40e10288
1403 #define DF_CLE_nOE 0x40e10204
1404 #define DF_ALE_nWE1 0x40e10208
1405 #define DF_ALE_nWE2 0x40e1021c
1406 #define DF_SCLK_E 0x40e10210
1407 #define DF_nCS0 0x40e10224
1408 #define DF_nCS1 0x40e10228
1409 #define nBE0 0x40e10214
1410 #define nBE1 0x40e10218
1411 #define nLUA 0x40e10234
1412 #define nLLA 0x40e10238
1413 #define DF_ADDR0 0x40e1023c
1414 #define DF_ADDR1 0x40e10240
1415 #define DF_ADDR2 0x40e10244
1416 #define DF_ADDR3 0x40e10248
1417 #define DF_INT_RnB 0x40e10220
1418 #define DF_nCS0 0x40e10224
1419 #define DF_nCS1 0x40e10228
1420 #define DF_nWE 0x40e1022c
1421 #define DF_nRE 0x40e10230
1423 #define nXCVREN 0x40e10138
1425 #define GPIO0 0x40e10124
1426 #define GPIO1 0x40e10128
1427 #define GPIO2 0x40e1012c
1428 #define GPIO3 0x40e10130
1429 #define GPIO4 0x40e10134
1430 #define GPIO5 0x40e1028c
1431 #define GPIO6 0x40e10290
1432 #define GPIO7 0x40e10294
1433 #define GPIO8 0x40e10298
1434 #define GPIO9 0x40e1029c
1435 #define GPIO10 0x40e10458
1436 #define GPIO11 0x40e102a0
1437 #define GPIO12 0x40e102a4
1438 #define GPIO13 0x40e102a8
1439 #define GPIO14 0x40e102ac
1440 #define GPIO15 0x40e102b0
1441 #define GPIO16 0x40e102b4
1442 #define GPIO17 0x40e102b8
1443 #define GPIO18 0x40e102bc
1444 #define GPIO19 0x40e102c0
1445 #define GPIO20 0x40e102c4
1446 #define GPIO21 0x40e102c8
1447 #define GPIO22 0x40e102cc
1448 #define GPIO23 0x40e102d0
1449 #define GPIO24 0x40e102d4
1450 #define GPIO25 0x40e102d8
1451 #define GPIO26 0x40e102dc
1453 #define GPIO27 0x40e10400
1454 #define GPIO28 0x40e10404
1455 #define GPIO29 0x40e10408
1456 #define GPIO30 0x40e1040c
1457 #define GPIO31 0x40e10410
1458 #define GPIO32 0x40e10414
1459 #define GPIO33 0x40e10418
1460 #define GPIO34 0x40e1041c
1461 #define GPIO35 0x40e10420
1462 #define GPIO36 0x40e10424
1463 #define GPIO37 0x40e10428
1464 #define GPIO38 0x40e1042c
1465 #define GPIO39 0x40e10430
1466 #define GPIO40 0x40e10434
1467 #define GPIO41 0x40e10438
1468 #define GPIO42 0x40e1043c
1469 #define GPIO43 0x40e10440
1470 #define GPIO44 0x40e10444
1471 #define GPIO45 0x40e10448
1472 #define GPIO46 0x40e1044c
1473 #define GPIO47 0x40e10450
1474 #define GPIO48 0x40e10454
1475 #define GPIO49 0x40e1045c
1476 #define GPIO50 0x40e10460
1477 #define GPIO51 0x40e10464
1478 #define GPIO52 0x40e10468
1479 #define GPIO53 0x40e1046c
1480 #define GPIO54 0x40e10470
1481 #define GPIO55 0x40e10474
1482 #define GPIO56 0x40e10478
1483 #define GPIO57 0x40e1047c
1484 #define GPIO58 0x40e10480
1485 #define GPIO59 0x40e10484
1486 #define GPIO60 0x40e10488
1487 #define GPIO61 0x40e1048c
1488 #define GPIO62 0x40e10490
1490 #define GPIO6_2 0x40e10494
1491 #define GPIO7_2 0x40e10498
1492 #define GPIO8_2 0x40e1049c
1493 #define GPIO9_2 0x40e104a0
1494 #define GPIO10_2 0x40e104a4
1495 #define GPIO11_2 0x40e104a8
1496 #define GPIO12_2 0x40e104ac
1497 #define GPIO13_2 0x40e104b0
1499 #define GPIO63 0x40e104b4
1500 #define GPIO64 0x40e104b8
1501 #define GPIO65 0x40e104bc
1502 #define GPIO66 0x40e104c0
1503 #define GPIO67 0x40e104c4
1504 #define GPIO68 0x40e104c8
1505 #define GPIO69 0x40e104cc
1506 #define GPIO70 0x40e104d0
1507 #define GPIO71 0x40e104d4
1508 #define GPIO72 0x40e104d8
1509 #define GPIO73 0x40e104dc
1511 #define GPIO14_2 0x40e104e0
1512 #define GPIO15_2 0x40e104e4
1513 #define GPIO16_2 0x40e104e8
1514 #define GPIO17_2 0x40e104ec
1516 #define GPIO74 0x40e104f0
1517 #define GPIO75 0x40e104f4
1518 #define GPIO76 0x40e104f8
1519 #define GPIO77 0x40e104fc
1520 #define GPIO78 0x40e10500
1521 #define GPIO79 0x40e10504
1522 #define GPIO80 0x40e10508
1523 #define GPIO81 0x40e1050c
1524 #define GPIO82 0x40e10510
1525 #define GPIO83 0x40e10514
1526 #define GPIO84 0x40e10518
1527 #define GPIO85 0x40e1051c
1528 #define GPIO86 0x40e10520
1529 #define GPIO87 0x40e10524
1530 #define GPIO88 0x40e10528
1531 #define GPIO89 0x40e1052c
1532 #define GPIO90 0x40e10530
1533 #define GPIO91 0x40e10534
1534 #define GPIO92 0x40e10538
1535 #define GPIO93 0x40e1053c
1536 #define GPIO94 0x40e10540
1537 #define GPIO95 0x40e10544
1538 #define GPIO96 0x40e10548
1539 #define GPIO97 0x40e1054c
1540 #define GPIO98 0x40e10550
1542 #define GPIO99 0x40e10600
1543 #define GPIO100 0x40e10604
1544 #define GPIO101 0x40e10608
1545 #define GPIO102 0x40e1060c
1546 #define GPIO103 0x40e10610
1547 #define GPIO104 0x40e10614
1548 #define GPIO105 0x40e10618
1549 #define GPIO106 0x40e1061c
1550 #define GPIO107 0x40e10620
1551 #define GPIO108 0x40e10624
1552 #define GPIO109 0x40e10628
1553 #define GPIO110 0x40e1062c
1554 #define GPIO111 0x40e10630
1555 #define GPIO112 0x40e10634
1557 #define GPIO113 0x40e10638
1558 #define GPIO114 0x40e1063c
1559 #define GPIO115 0x40e10640
1560 #define GPIO116 0x40e10644
1561 #define GPIO117 0x40e10648
1562 #define GPIO118 0x40e1064c
1563 #define GPIO119 0x40e10650
1564 #define GPIO120 0x40e10654
1565 #define GPIO121 0x40e10658
1566 #define GPIO122 0x40e1065c
1567 #define GPIO123 0x40e10660
1568 #define GPIO124 0x40e10664
1569 #define GPIO125 0x40e10668
1570 #define GPIO126 0x40e1066c
1571 #define GPIO127 0x40e10670
1573 #define GPIO0_2 0x40e10674
1574 #define GPIO1_2 0x40e10678
1575 #define GPIO2_2 0x40e1067c
1576 #define GPIO3_2 0x40e10680
1577 #define GPIO4_2 0x40e10684
1578 #define GPIO5_2 0x40e10688
1580 /* PXA300 and PXA310 */
1581 #elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
1582 #define DF_IO0 0x40e10220
1583 #define DF_IO1 0x40e10228
1584 #define DF_IO2 0x40e10230
1585 #define DF_IO3 0x40e10238
1586 #define DF_IO4 0x40e10258
1587 #define DF_IO5 0x40e10260
1588 #define DF_IO7 0x40e10270
1589 #define DF_IO6 0x40e10268
1590 #define DF_IO8 0x40e10224
1591 #define DF_IO9 0x40e1022c
1592 #define DF_IO10 0x40e10234
1593 #define DF_IO11 0x40e1023c
1594 #define DF_IO12 0x40e1025c
1595 #define DF_IO13 0x40e10264
1596 #define DF_IO14 0x40e1026c
1597 #define DF_IO15 0x40e10274
1598 #define DF_CLE_NOE 0x40e10240
1599 #define DF_ALE_nWE 0x40e1020c
1600 #define DF_SCLK_E 0x40e10250
1601 #define nCS0 0x40e100c4
1602 #define nCS1 0x40e100c0
1603 #define nBE0 0x40e10204
1604 #define nBE1 0x40e10208
1605 #define nLUA 0x40e10244
1606 #define nLLA 0x40e10254
1607 #define DF_ADDR0 0x40e10210
1608 #define DF_ADDR1 0x40e10214
1609 #define DF_ADDR2 0x40e10218
1610 #define DF_ADDR3 0x40e1021c
1611 #define DF_INT_RnB 0x40e100c8
1612 #define DF_nCS0 0x40e10248
1613 #define DF_nCS1 0x40e10278
1614 #define DF_nWE 0x40e100cc
1615 #define DF_nRE 0x40e10200
1617 #define GPIO0 0x40e100b4
1618 #define GPIO1 0x40e100b8
1619 #define GPIO2 0x40e100bc
1620 #define GPIO3 0x40e1027c
1621 #define GPIO4 0x40e10280
1623 #define GPIO5 0x40e10284
1624 #define GPIO6 0x40e10288
1625 #define GPIO7 0x40e1028c
1626 #define GPIO8 0x40e10290
1627 #define GPIO9 0x40e10294
1628 #define GPIO10 0x40e10298
1629 #define GPIO11 0x40e1029c
1630 #define GPIO12 0x40e102a0
1631 #define GPIO13 0x40e102a4
1632 #define GPIO14 0x40e102a8
1633 #define GPIO15 0x40e102ac
1634 #define GPIO16 0x40e102b0
1635 #define GPIO17 0x40e102b4
1636 #define GPIO18 0x40e102b8
1637 #define GPIO19 0x40e102bc
1638 #define GPIO20 0x40e102c0
1639 #define GPIO21 0x40e102c4
1640 #define GPIO22 0x40e102c8
1641 #define GPIO23 0x40e102cc
1642 #define GPIO24 0x40e102d0
1643 #define GPIO25 0x40e102d4
1644 #define GPIO26 0x40e102d8
1646 #define GPIO27 0x40e10400
1647 #define GPIO28 0x40e10404
1648 #define GPIO29 0x40e10408
1649 #define ULPI_STP 0x40e1040c
1650 #define ULPI_NXT 0x40e10410
1651 #define ULPI_DIR 0x40e10414
1652 #define GPIO30 0x40e10418
1653 #define GPIO31 0x40e1041c
1654 #define GPIO32 0x40e10420
1655 #define GPIO33 0x40e10424
1656 #define GPIO34 0x40e10428
1657 #define GPIO35 0x40e1042c
1658 #define GPIO36 0x40e10430
1659 #define GPIO37 0x40e10434
1660 #define GPIO38 0x40e10438
1661 #define GPIO39 0x40e1043c
1662 #define GPIO40 0x40e10440
1663 #define GPIO41 0x40e10444
1664 #define GPIO42 0x40e10448
1665 #define GPIO43 0x40e1044c
1666 #define GPIO44 0x40e10450
1667 #define GPIO45 0x40e10454
1668 #define GPIO46 0x40e10458
1669 #define GPIO47 0x40e1045c
1670 #define GPIO48 0x40e10460
1672 #define GPIO49 0x40e10464
1673 #define GPIO50 0x40e10468
1674 #define GPIO51 0x40e1046c
1675 #define GPIO52 0x40e10470
1676 #define GPIO53 0x40e10474
1677 #define GPIO54 0x40e10478
1678 #define GPIO55 0x40e1047c
1679 #define GPIO56 0x40e10480
1680 #define GPIO57 0x40e10484
1681 #define GPIO58 0x40e10488
1682 #define GPIO59 0x40e1048c
1683 #define GPIO60 0x40e10490
1684 #define GPIO61 0x40e10494
1685 #define GPIO62 0x40e10498
1686 #define GPIO63 0x40e1049c
1687 #define GPIO64 0x40e104a0
1688 #define GPIO65 0x40e104a4
1689 #define GPIO66 0x40e104a8
1690 #define GPIO67 0x40e104ac
1691 #define GPIO68 0x40e104b0
1692 #define GPIO69 0x40e104b4
1693 #define GPIO70 0x40e104b8
1694 #define GPIO71 0x40e104bc
1695 #define GPIO72 0x40e104c0
1696 #define GPIO73 0x40e104c4
1697 #define GPIO74 0x40e104c8
1698 #define GPIO75 0x40e104cc
1699 #define GPIO76 0x40e104d0
1700 #define GPIO77 0x40e104d4
1701 #define GPIO78 0x40e104d8
1702 #define GPIO79 0x40e104dc
1703 #define GPIO80 0x40e104e0
1704 #define GPIO81 0x40e104e4
1705 #define GPIO82 0x40e104e8
1706 #define GPIO83 0x40e104ec
1707 #define GPIO84 0x40e104f0
1708 #define GPIO85 0x40e104f4
1709 #define GPIO86 0x40e104f8
1710 #define GPIO87 0x40e104fc
1711 #define GPIO88 0x40e10500
1712 #define GPIO89 0x40e10504
1713 #define GPIO90 0x40e10508
1714 #define GPIO91 0x40e1050c
1715 #define GPIO92 0x40e10510
1716 #define GPIO93 0x40e10514
1717 #define GPIO94 0x40e10518
1718 #define GPIO95 0x40e1051c
1719 #define GPIO96 0x40e10520
1720 #define GPIO97 0x40e10524
1721 #define GPIO98 0x40e10528
1723 #define GPIO99 0x40e10600
1724 #define GPIO100 0x40e10604
1725 #define GPIO101 0x40e10608
1726 #define GPIO102 0x40e1060c
1727 #define GPIO103 0x40e10610
1728 #define GPIO104 0x40e10614
1729 #define GPIO105 0x40e10618
1730 #define GPIO106 0x40e1061c
1731 #define GPIO107 0x40e10620
1732 #define GPIO108 0x40e10624
1733 #define GPIO109 0x40e10628
1734 #define GPIO110 0x40e1062c
1735 #define GPIO111 0x40e10630
1736 #define GPIO112 0x40e10634
1738 #define GPIO113 0x40e10638
1739 #define GPIO114 0x40e1063c
1740 #define GPIO115 0x40e10640
1741 #define GPIO116 0x40e10644
1742 #define GPIO117 0x40e10648
1743 #define GPIO118 0x40e1064c
1744 #define GPIO119 0x40e10650
1745 #define GPIO120 0x40e10654
1746 #define GPIO121 0x40e10658
1747 #define GPIO122 0x40e1065c
1748 #define GPIO123 0x40e10660
1749 #define GPIO124 0x40e10664
1750 #define GPIO125 0x40e10668
1751 #define GPIO126 0x40e1066c
1752 #define GPIO127 0x40e10670
1754 #define GPIO0_2 0x40e10674
1755 #define GPIO1_2 0x40e10678
1756 #define GPIO2_2 0x40e102dc
1757 #define GPIO3_2 0x40e102e0
1758 #define GPIO4_2 0x40e102e4
1759 #define GPIO5_2 0x40e102e8
1760 #define GPIO6_2 0x40e102ec
1762 #ifndef CONFIG_CPU_PXA300 /* PXA310 only */
1763 #define GPIO7_2 0x40e1052c
1764 #define GPIO8_2 0x40e10530
1765 #define GPIO9_2 0x40e10534
1766 #define GPIO10_2 0x40e10538
1770 #ifdef CONFIG_CPU_MONAHANS
1771 /* MFPR Bit Definitions, see 4-10, Vol. 1 */
1772 #define PULL_SEL 0x8000
1773 #define PULLUP_EN 0x4000
1774 #define PULLDOWN_EN 0x2000
1776 #define DRIVE_FAST_1mA 0x0
1777 #define DRIVE_FAST_2mA 0x400
1778 #define DRIVE_FAST_3mA 0x800
1779 #define DRIVE_FAST_4mA 0xC00
1780 #define DRIVE_SLOW_6mA 0x1000
1781 #define DRIVE_FAST_6mA 0x1400
1782 #define DRIVE_SLOW_10mA 0x1800
1783 #define DRIVE_FAST_10mA 0x1C00
1785 #define SLEEP_SEL 0x200
1786 #define SLEEP_DATA 0x100
1787 #define SLEEP_OE_N 0x80
1788 #define EDGE_CLEAR 0x40
1789 #define EDGE_FALL_EN 0x20
1790 #define EDGE_RISE_EN 0x10
1792 #define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */
1793 #define AF_SEL_1 0x1 /* Alternate function 1 */
1794 #define AF_SEL_2 0x2 /* Alternate function 2 */
1795 #define AF_SEL_3 0x3 /* Alternate function 3 */
1796 #define AF_SEL_4 0x4 /* Alternate function 4 */
1797 #define AF_SEL_5 0x5 /* Alternate function 5 */
1798 #define AF_SEL_6 0x6 /* Alternate function 6 */
1799 #define AF_SEL_7 0x7 /* Alternate function 7 */
1801 #endif /* CONFIG_CPU_MONAHANS */
1803 /* GPIO alternate function assignments */
1805 #define GPIO1_RST 1 /* reset */
1806 #define GPIO6_MMCCLK 6 /* MMC Clock */
1807 #define GPIO8_48MHz 7 /* 48 MHz clock output */
1808 #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
1809 #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
1810 #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
1811 #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
1812 #define GPIO12_32KHz 12 /* 32 kHz out */
1813 #define GPIO13_MBGNT 13 /* memory controller grant */
1814 #define GPIO14_MBREQ 14 /* alternate bus master request */
1815 #define GPIO15_nCS_1 15 /* chip select 1 */
1816 #define GPIO16_PWM0 16 /* PWM0 output */
1817 #define GPIO17_PWM1 17 /* PWM1 output */
1818 #define GPIO18_RDY 18 /* Ext. Bus Ready */
1819 #define GPIO19_DREQ1 19 /* External DMA Request */
1820 #define GPIO20_DREQ0 20 /* External DMA Request */
1821 #define GPIO23_SCLK 23 /* SSP clock */
1822 #define GPIO24_SFRM 24 /* SSP Frame */
1823 #define GPIO25_STXD 25 /* SSP transmit */
1824 #define GPIO26_SRXD 26 /* SSP receive */
1825 #define GPIO27_SEXTCLK 27 /* SSP ext_clk */
1826 #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
1827 #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
1828 #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
1829 #define GPIO31_SYNC 31 /* AC97/I2S sync */
1830 #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
1831 #define GPIO33_nCS_5 33 /* chip select 5 */
1832 #define GPIO34_FFRXD 34 /* FFUART receive */
1833 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
1834 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
1835 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
1836 #define GPIO37_FFDSR 37 /* FFUART data set ready */
1837 #define GPIO38_FFRI 38 /* FFUART Ring Indicator */
1838 #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
1839 #define GPIO39_FFTXD 39 /* FFUART transmit data */
1840 #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
1841 #define GPIO41_FFRTS 41 /* FFUART request to send */
1842 #define GPIO42_BTRXD 42 /* BTUART receive data */
1843 #define GPIO43_BTTXD 43 /* BTUART transmit data */
1844 #define GPIO44_BTCTS 44 /* BTUART clear to send */
1845 #define GPIO45_BTRTS 45 /* BTUART request to send */
1846 #define GPIO46_ICPRXD 46 /* ICP receive data */
1847 #define GPIO46_STRXD 46 /* STD_UART receive data */
1848 #define GPIO47_ICPTXD 47 /* ICP transmit data */
1849 #define GPIO47_STTXD 47 /* STD_UART transmit data */
1850 #define GPIO48_nPOE 48 /* Output Enable for Card Space */
1851 #define GPIO49_nPWE 49 /* Write Enable for Card Space */
1852 #define GPIO50_nPIOR 50 /* I/O Read for Card Space */
1853 #define GPIO51_nPIOW 51 /* I/O Write for Card Space */
1854 #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
1855 #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
1856 #define GPIO53_MMCCLK 53 /* MMC Clock */
1857 #define GPIO54_MMCCLK 54 /* MMC Clock */
1858 #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
1859 #define GPIO55_nPREG 55 /* Card Address bit 26 */
1860 #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
1861 #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
1862 #define GPIO58_LDD_0 58 /* LCD data pin 0 */
1863 #define GPIO59_LDD_1 59 /* LCD data pin 1 */
1864 #define GPIO60_LDD_2 60 /* LCD data pin 2 */
1865 #define GPIO61_LDD_3 61 /* LCD data pin 3 */
1866 #define GPIO62_LDD_4 62 /* LCD data pin 4 */
1867 #define GPIO63_LDD_5 63 /* LCD data pin 5 */
1868 #define GPIO64_LDD_6 64 /* LCD data pin 6 */
1869 #define GPIO65_LDD_7 65 /* LCD data pin 7 */
1870 #define GPIO66_LDD_8 66 /* LCD data pin 8 */
1871 #define GPIO66_MBREQ 66 /* alternate bus master req */
1872 #define GPIO67_LDD_9 67 /* LCD data pin 9 */
1873 #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
1874 #define GPIO68_LDD_10 68 /* LCD data pin 10 */
1875 #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
1876 #define GPIO69_LDD_11 69 /* LCD data pin 11 */
1877 #define GPIO69_MMCCLK 69 /* MMC_CLK */
1878 #define GPIO70_LDD_12 70 /* LCD data pin 12 */
1879 #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
1880 #define GPIO71_LDD_13 71 /* LCD data pin 13 */
1881 #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
1882 #define GPIO72_LDD_14 72 /* LCD data pin 14 */
1883 #define GPIO72_32kHz 72 /* 32 kHz clock */
1884 #define GPIO73_LDD_15 73 /* LCD data pin 15 */
1885 #define GPIO73_MBGNT 73 /* Memory controller grant */
1886 #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
1887 #define GPIO75_LCD_LCLK 75 /* LCD line clock */
1888 #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
1889 #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
1890 #define GPIO78_nCS_2 78 /* chip select 2 */
1891 #define GPIO79_nCS_3 79 /* chip select 3 */
1892 #define GPIO80_nCS_4 80 /* chip select 4 */
1894 /* GPIO alternate function mode & direction */
1896 #define GPIO_IN 0x000
1897 #define GPIO_OUT 0x080
1898 #define GPIO_ALT_FN_1_IN 0x100
1899 #define GPIO_ALT_FN_1_OUT 0x180
1900 #define GPIO_ALT_FN_2_IN 0x200
1901 #define GPIO_ALT_FN_2_OUT 0x280
1902 #define GPIO_ALT_FN_3_IN 0x300
1903 #define GPIO_ALT_FN_3_OUT 0x380
1904 #define GPIO_MD_MASK_NR 0x07f
1905 #define GPIO_MD_MASK_DIR 0x080
1906 #define GPIO_MD_MASK_FN 0x300
1908 #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
1909 #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
1910 #define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT)
1911 #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
1912 #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
1913 #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
1914 #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
1915 #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
1916 #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
1917 #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
1918 #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
1919 #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
1920 #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
1921 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
1922 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
1923 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
1924 #define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
1925 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
1926 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
1927 #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
1928 #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
1929 #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
1930 #define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN)
1931 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1932 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
1933 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
1934 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1935 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
1936 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
1937 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
1938 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
1939 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
1940 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
1941 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
1942 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
1943 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
1944 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
1945 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
1946 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
1947 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1948 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1949 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1950 #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1951 #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1952 #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1953 #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1954 #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1955 #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1956 #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1957 #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1958 #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1959 #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1960 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1961 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1962 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
1963 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
1964 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
1965 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
1966 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
1967 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
1968 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
1969 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
1970 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
1971 #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
1972 #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
1973 #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
1974 #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
1975 #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
1976 #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
1977 #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
1978 #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
1979 #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
1980 #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
1981 #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
1982 #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
1983 #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
1984 #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
1985 #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
1986 #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
1987 #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
1988 #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
1989 #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
1990 #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
1991 #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
1992 #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
1993 #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
1994 #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
1995 #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
1996 #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
1997 #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
1998 #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
1999 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
2001 #define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
2002 #define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
2007 #ifdef CONFIG_CPU_MONAHANS
2009 #define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */
2010 #define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */
2011 #define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */
2012 #define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */
2013 #define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */
2014 #define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */
2015 #define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */
2016 #define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */
2017 #define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */
2018 #define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */
2019 #define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */
2020 #define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */
2021 #define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */
2022 #define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */
2024 #define PMCR 0x40F50000 /* Power Manager Control Register */
2025 #define PSR 0x40F50004 /* Power Manager S2 Status Register */
2026 #define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */
2027 #define PCFR 0x40F5000C /* Power Manager General Configuration Register */
2028 #define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */
2029 #define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */
2030 #define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */
2031 #define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */
2032 #define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */
2033 #define PCMD(x) (0x40F50110 + x*4)
2034 #define PCMD0 (0x40F50110 + 0 * 4)
2035 #define PCMD1 (0x40F50110 + 1 * 4)
2036 #define PCMD2 (0x40F50110 + 2 * 4)
2037 #define PCMD3 (0x40F50110 + 3 * 4)
2038 #define PCMD4 (0x40F50110 + 4 * 4)
2039 #define PCMD5 (0x40F50110 + 5 * 4)
2040 #define PCMD6 (0x40F50110 + 6 * 4)
2041 #define PCMD7 (0x40F50110 + 7 * 4)
2042 #define PCMD8 (0x40F50110 + 8 * 4)
2043 #define PCMD9 (0x40F50110 + 9 * 4)
2044 #define PCMD10 (0x40F50110 + 10 * 4)
2045 #define PCMD11 (0x40F50110 + 11 * 4)
2046 #define PCMD12 (0x40F50110 + 12 * 4)
2047 #define PCMD13 (0x40F50110 + 13 * 4)
2048 #define PCMD14 (0x40F50110 + 14 * 4)
2049 #define PCMD15 (0x40F50110 + 15 * 4)
2050 #define PCMD16 (0x40F50110 + 16 * 4)
2051 #define PCMD17 (0x40F50110 + 17 * 4)
2052 #define PCMD18 (0x40F50110 + 18 * 4)
2053 #define PCMD19 (0x40F50110 + 19 * 4)
2054 #define PCMD20 (0x40F50110 + 20 * 4)
2055 #define PCMD21 (0x40F50110 + 21 * 4)
2056 #define PCMD22 (0x40F50110 + 22 * 4)
2057 #define PCMD23 (0x40F50110 + 23 * 4)
2058 #define PCMD24 (0x40F50110 + 24 * 4)
2059 #define PCMD25 (0x40F50110 + 25 * 4)
2060 #define PCMD26 (0x40F50110 + 26 * 4)
2061 #define PCMD27 (0x40F50110 + 27 * 4)
2062 #define PCMD28 (0x40F50110 + 28 * 4)
2063 #define PCMD29 (0x40F50110 + 29 * 4)
2064 #define PCMD30 (0x40F50110 + 30 * 4)
2065 #define PCMD31 (0x40F50110 + 31 * 4)
2067 #define PCMD_MBC (1<<12)
2068 #define PCMD_DCE (1<<11)
2069 #define PCMD_LC (1<<10)
2070 #define PCMD_SQC (3<<8) /* only 00 and 01 are valid */
2072 #define PVCR_FVC (0x1 << 28)
2073 #define PVCR_VCSA (0x1<<14)
2074 #define PVCR_CommandDelay (0xf80)
2075 #define PVCR_ReadPointer 0x01f00000
2076 #define PVCR_SlaveAddress (0x7f)
2078 #else /* ifdef CONFIG_CPU_MONAHANS */
2080 #define PMCR 0x40F00000 /* Power Manager Control Register */
2081 #define PSSR 0x40F00004 /* Power Manager Sleep Status Register */
2082 #define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */
2083 #define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */
2084 #define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */
2085 #define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */
2086 #define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */
2087 #define PCFR 0x40F0001C /* Power Manager General Configuration Register */
2088 #define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */
2089 #define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */
2090 #define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */
2091 #define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */
2092 #define RCSR 0x40F00030 /* Reset Controller Status Register */
2094 #define PSLR 0x40F00034 /* Power Manager Sleep Config Register */
2095 #define PSTR 0x40F00038 /* Power Manager Standby Config Register */
2096 #define PSNR 0x40F0003C /* Power Manager Sense Config Register */
2097 #define PVCR 0x40F00040 /* Power Manager VoltageControl Register */
2098 #define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */
2099 #define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */
2100 #define PCMD(x) (0x40F00080 + x*4)
2101 #define PCMD0 (0x40F00080 + 0 * 4)
2102 #define PCMD1 (0x40F00080 + 1 * 4)
2103 #define PCMD2 (0x40F00080 + 2 * 4)
2104 #define PCMD3 (0x40F00080 + 3 * 4)
2105 #define PCMD4 (0x40F00080 + 4 * 4)
2106 #define PCMD5 (0x40F00080 + 5 * 4)
2107 #define PCMD6 (0x40F00080 + 6 * 4)
2108 #define PCMD7 (0x40F00080 + 7 * 4)
2109 #define PCMD8 (0x40F00080 + 8 * 4)
2110 #define PCMD9 (0x40F00080 + 9 * 4)
2111 #define PCMD10 (0x40F00080 + 10 * 4)
2112 #define PCMD11 (0x40F00080 + 11 * 4)
2113 #define PCMD12 (0x40F00080 + 12 * 4)
2114 #define PCMD13 (0x40F00080 + 13 * 4)
2115 #define PCMD14 (0x40F00080 + 14 * 4)
2116 #define PCMD15 (0x40F00080 + 15 * 4)
2117 #define PCMD16 (0x40F00080 + 16 * 4)
2118 #define PCMD17 (0x40F00080 + 17 * 4)
2119 #define PCMD18 (0x40F00080 + 18 * 4)
2120 #define PCMD19 (0x40F00080 + 19 * 4)
2121 #define PCMD20 (0x40F00080 + 20 * 4)
2122 #define PCMD21 (0x40F00080 + 21 * 4)
2123 #define PCMD22 (0x40F00080 + 22 * 4)
2124 #define PCMD23 (0x40F00080 + 23 * 4)
2125 #define PCMD24 (0x40F00080 + 24 * 4)
2126 #define PCMD25 (0x40F00080 + 25 * 4)
2127 #define PCMD26 (0x40F00080 + 26 * 4)
2128 #define PCMD27 (0x40F00080 + 27 * 4)
2129 #define PCMD28 (0x40F00080 + 28 * 4)
2130 #define PCMD29 (0x40F00080 + 29 * 4)
2131 #define PCMD30 (0x40F00080 + 30 * 4)
2132 #define PCMD31 (0x40F00080 + 31 * 4)
2134 #define PCMD_MBC (1<<12)
2135 #define PCMD_DCE (1<<11)
2136 #define PCMD_LC (1<<10)
2137 /* FIXME: PCMD_SQC need be checked. */
2138 #define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */
2139 /* bit 9 should be 0 all day. */
2140 #define PVCR_VCSA (0x1<<14)
2141 #define PVCR_CommandDelay (0xf80)
2142 /* define MACRO for Power Manager General Configuration Register (PCFR) */
2143 #define PCFR_FVC (0x1 << 10)
2144 #define PCFR_PI2C_EN (0x1 << 6)
2146 #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
2147 #define PSSR_RDH (1 << 5) /* Read Disable Hold */
2148 #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
2149 #define PSSR_VFS (1 << 2) /* VDD Fault Status */
2150 #define PSSR_BFS (1 << 1) /* Battery Fault Status */
2151 #define PSSR_SSS (1 << 0) /* Software Sleep Status */
2153 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
2154 #define PCFR_FS (1 << 2) /* Float Static Chip Selects */
2155 #define PCFR_FP (1 << 1) /* Float PCMCIA controls */
2156 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
2158 #define RCSR_GPR (1 << 3) /* GPIO Reset */
2159 #define RCSR_SMR (1 << 2) /* Sleep Mode */
2160 #define RCSR_WDR (1 << 1) /* Watchdog Reset */
2161 #define RCSR_HWR (1 << 0) /* Hardware Reset */
2163 #endif /* CONFIG_CPU_MONAHANS */
2166 * SSP Serial Port Registers
2168 #define SSCR0 0x41000000 /* SSP Control Register 0 */
2169 #define SSCR1 0x41000004 /* SSP Control Register 1 */
2170 #define SSSR 0x41000008 /* SSP Status Register */
2171 #define SSITR 0x4100000C /* SSP Interrupt Test Register */
2172 #define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
2175 * MultiMediaCard (MMC) controller
2177 #define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */
2178 #define MMC_STAT 0x41100004 /* MMC Status Register (read only) */
2179 #define MMC_CLKRT 0x41100008 /* MMC clock rate */
2180 #define MMC_SPI 0x4110000c /* SPI mode control bits */
2181 #define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */
2182 #define MMC_RESTO 0x41100014 /* Expected response time out */
2183 #define MMC_RDTO 0x41100018 /* Expected data read time out */
2184 #define MMC_BLKLEN 0x4110001c /* Block length of data transaction */
2185 #define MMC_NOB 0x41100020 /* Number of blocks, for block mode */
2186 #define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */
2187 #define MMC_I_MASK 0x41100028 /* Interrupt Mask */
2188 #define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */
2189 #define MMC_CMD 0x41100030 /* Index of current command */
2190 #define MMC_ARGH 0x41100034 /* MSW part of the current command argument */
2191 #define MMC_ARGL 0x41100038 /* LSW part of the current command argument */
2192 #define MMC_RES 0x4110003c /* Response FIFO (read only) */
2193 #define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */
2194 #define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */
2200 #define LCCR0 0x44000000 /* LCD Controller Control Register 0 */
2201 #define LCCR1 0x44000004 /* LCD Controller Control Register 1 */
2202 #define LCCR2 0x44000008 /* LCD Controller Control Register 2 */
2203 #define LCCR3 0x4400000C /* LCD Controller Control Register 3 */
2204 #define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
2205 #define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
2206 #define LCSR0 0x44000038 /* LCD Controller Status Register */
2207 #define LCSR1 0x44000034 /* LCD Controller Status Register */
2208 #define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */
2209 #define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */
2210 #define TMEDCR 0x44000044 /* TMED Control Register */
2212 #define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */
2213 #define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */
2214 #define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */
2215 #define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */
2216 #define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */
2217 #define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */
2218 #define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */
2219 #define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */
2221 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
2222 #define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
2223 #define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */
2224 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
2225 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
2226 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
2227 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
2228 #define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */
2229 #define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */
2230 #define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
2231 #define LCCR0_DIS (1 << 10) /* LCD Disable */
2232 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
2233 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
2234 #define LCCR0_PDD_S 12
2235 #define LCCR0_BM (1 << 20) /* Branch mask */
2236 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
2237 #if defined(CONFIG_PXA27X)
2238 #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
2239 #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
2240 #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
2243 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2244 #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
2245 (((Pixel) - 1) << FShft (LCCR1_PPL))
2247 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2248 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
2249 /* pulse Width [1..64 Tpix] */ \
2250 (((Tpix) - 1) << FShft (LCCR1_HSW))
2252 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2253 /* count - 1 [Tpix] */
2254 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2255 /* [1..256 Tpix] */ \
2256 (((Tpix) - 1) << FShft (LCCR1_ELW))
2258 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2259 /* Wait count - 1 [Tpix] */
2260 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2261 /* [1..256 Tpix] */ \
2262 (((Tpix) - 1) << FShft (LCCR1_BLW))
2265 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2266 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
2267 (((Line) - 1) << FShft (LCCR2_LPP))
2269 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2270 /* Width - 1 [Tln] (L_FCLK) */
2271 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
2272 /* Width [1..64 Tln] */ \
2273 (((Tln) - 1) << FShft (LCCR2_VSW))
2275 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2277 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2278 /* [0..255 Tln] */ \
2279 ((Tln) << FShft (LCCR2_EFW))
2281 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2282 /* Wait count [Tln] */
2283 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2284 /* [0..255 Tln] */ \
2285 ((Tln) << FShft (LCCR2_BFW))
2287 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
2288 #define LCCR3_API_S 16
2289 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
2290 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
2291 #define LCCR3_PCP (1 << 22) /* pixel clock polarity */
2292 #define LCCR3_OEP (1 << 23) /* output enable polarity */
2293 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
2295 #define LCCR3_PDFOR_0 (0 << 30)
2296 #define LCCR3_PDFOR_1 (1 << 30)
2297 #define LCCR3_PDFOR_2 (2 << 30)
2298 #define LCCR3_PDFOR_3 (3 << 30)
2301 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
2302 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
2303 (((Div) << FShft (LCCR3_PCD)))
2306 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
2307 #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
2308 ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
2310 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
2311 #define LCCR3_Acb(Acb) /* BAC Bias */ \
2312 (((Acb) << FShft (LCCR3_ACB)))
2314 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
2315 /* pulse active High */
2316 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
2318 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2320 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
2323 #define LCSR0_LDD (1 << 0) /* LCD Disable Done */
2324 #define LCSR0_SOF (1 << 1) /* Start of frame */
2325 #define LCSR0_BER (1 << 2) /* Bus error */
2326 #define LCSR0_ABC (1 << 3) /* AC Bias count */
2327 #define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */
2328 #define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */
2329 #define LCSR0_OU (1 << 6) /* output FIFO underrun */
2330 #define LCSR0_QD (1 << 7) /* quick disable */
2331 #define LCSR0_EOF0 (1 << 8) /* end of frame */
2332 #define LCSR0_BS (1 << 9) /* branch status */
2333 #define LCSR0_SINT (1 << 10) /* subsequent interrupt */
2335 #define LCSR1_SOF1 (1 << 0)
2336 #define LCSR1_SOF2 (1 << 1)
2337 #define LCSR1_SOF3 (1 << 2)
2338 #define LCSR1_SOF4 (1 << 3)
2339 #define LCSR1_SOF5 (1 << 4)
2340 #define LCSR1_SOF6 (1 << 5)
2342 #define LCSR1_EOF1 (1 << 8)
2343 #define LCSR1_EOF2 (1 << 9)
2344 #define LCSR1_EOF3 (1 << 10)
2345 #define LCSR1_EOF4 (1 << 11)
2346 #define LCSR1_EOF5 (1 << 12)
2347 #define LCSR1_EOF6 (1 << 13)
2349 #define LCSR1_BS1 (1 << 16)
2350 #define LCSR1_BS2 (1 << 17)
2351 #define LCSR1_BS3 (1 << 18)
2352 #define LCSR1_BS4 (1 << 19)
2353 #define LCSR1_BS5 (1 << 20)
2354 #define LCSR1_BS6 (1 << 21)
2356 #define LCSR1_IU2 (1 << 25)
2357 #define LCSR1_IU3 (1 << 26)
2358 #define LCSR1_IU4 (1 << 27)
2359 #define LCSR1_IU5 (1 << 28)
2360 #define LCSR1_IU6 (1 << 29)
2362 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2363 #if defined(CONFIG_PXA27X)
2364 #define LDCMD_SOFINT (1 << 22)
2365 #define LDCMD_EOFINT (1 << 21)
2372 #ifdef CONFIG_CPU_MONAHANS
2376 /* Static Memory Controller Registers */
2377 #define MSC0 0x4A000008 /* Static Memory Control Register 0 */
2378 #define MSC1 0x4A00000C /* Static Memory Control Register 1 */
2379 #define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2380 #define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */
2381 #define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
2382 #define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
2383 #define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
2384 #define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */
2385 #define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */
2386 #define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */
2387 #define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */
2388 #define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */
2389 #define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */
2390 #define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */
2391 #define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
2392 #define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
2394 /* Dynamic Memory Controller Registers */
2395 #define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */
2396 #define MDREFR 0x48100004 /* SDRAM Refresh Control Register */
2397 #define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
2398 #define MDMRS 0x48100040 /* MRS value to be written to SDRAM */
2399 #define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
2400 #define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
2401 #define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */
2402 #define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */
2403 #define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */
2404 #define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
2405 #define EMPI 0x48100090 /* EMPI Control Register */
2406 #define RCOMP 0x48100100
2407 #define PAD_MA 0x48100110
2408 #define PAD_MDMSB 0x48100114
2409 #define PAD_MDLSB 0x48100118
2410 #define PAD_DMEM 0x4810011c
2411 #define PAD_SDCLK 0x48100120
2412 #define PAD_SDCS 0x48100124
2413 #define PAD_SMEM 0x48100128
2414 #define PAD_SCLK 0x4810012C
2415 #define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */
2417 /* Some frequently used bits */
2418 #define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
2419 #define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
2420 #define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
2421 #define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
2423 #define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
2424 #define MDCNFG_DTC_1 0x100
2425 #define MDCNFG_DTC_2 0x200
2426 #define MDCNFG_DTC_3 0x300
2428 #define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
2429 #define MDCNFG_DRAC_13 0x20
2430 #define MDCNFG_DRAC_14 0x40
2432 #define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
2433 #define MDCNFG_DCAC_10 0x08
2434 #define MDCNFG_DCAC_11 0x10
2436 #define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
2437 #define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
2438 #define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
2441 /* Data Flash Controller Registers */
2443 #define NDCR 0x43100000 /* Data Flash Control register */
2444 #define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
2445 /* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
2446 #define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
2447 /* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
2448 #define NDSR 0x43100014 /* Data Controller Status Register */
2449 #define NDPCR 0x43100018 /* Data Controller Page Count Register */
2450 #define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */
2451 #define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */
2452 #define NDDB 0x43100040 /* Data Controller Data Buffer */
2453 #define NDCB0 0x43100048 /* Data Controller Command Buffer0 */
2454 #define NDCB1 0x4310004C /* Data Controller Command Buffer1 */
2455 #define NDCB2 0x43100050 /* Data Controller Command Buffer2 */
2457 #define NDCR_SPARE_EN (0x1<<31)
2458 #define NDCR_ECC_EN (0x1<<30)
2459 #define NDCR_DMA_EN (0x1<<29)
2460 #define NDCR_ND_RUN (0x1<<28)
2461 #define NDCR_DWIDTH_C (0x1<<27)
2462 #define NDCR_DWIDTH_M (0x1<<26)
2463 #define NDCR_PAGE_SZ (0x3<<24)
2464 #define NDCR_NCSX (0x1<<23)
2465 #define NDCR_ND_STOP (0x1<<22)
2467 * #define NDCR_ND_MODE (0x3<<21)
2468 * #define NDCR_NAND_MODE 0x0 */
2469 #define NDCR_CLR_PG_CNT (0x1<<20)
2470 #define NDCR_CLR_ECC (0x1<<19)
2471 #define NDCR_RD_ID_CNT (0x7<<16)
2472 #define NDCR_RA_START (0x1<<15)
2473 #define NDCR_PG_PER_BLK (0x1<<14)
2474 #define NDCR_ND_ARB_EN (0x1<<12)
2475 #define NDCR_RDYM (0x1<<11)
2476 #define NDCR_CS0_PAGEDM (0x1<<10)
2477 #define NDCR_CS1_PAGEDM (0x1<<9)
2478 #define NDCR_CS0_CMDDM (0x1<<8)
2479 #define NDCR_CS1_CMDDM (0x1<<7)
2480 #define NDCR_CS0_BBDM (0x1<<6)
2481 #define NDCR_CS1_BBDM (0x1<<5)
2482 #define NDCR_DBERRM (0x1<<4)
2483 #define NDCR_SBERRM (0x1<<3)
2484 #define NDCR_WRDREQM (0x1<<2)
2485 #define NDCR_RDDREQM (0x1<<1)
2486 #define NDCR_WRCMDREQM (0x1)
2488 #define NDSR_RDY (0x1<<11)
2489 #define NDSR_CS0_PAGED (0x1<<10)
2490 #define NDSR_CS1_PAGED (0x1<<9)
2491 #define NDSR_CS0_CMDD (0x1<<8)
2492 #define NDSR_CS1_CMDD (0x1<<7)
2493 #define NDSR_CS0_BBD (0x1<<6)
2494 #define NDSR_CS1_BBD (0x1<<5)
2495 #define NDSR_DBERR (0x1<<4)
2496 #define NDSR_SBERR (0x1<<3)
2497 #define NDSR_WRDREQ (0x1<<2)
2498 #define NDSR_RDDREQ (0x1<<1)
2499 #define NDSR_WRCMDREQ (0x1)
2501 #define NDCB0_AUTO_RS (0x1<<25)
2502 #define NDCB0_CSEL (0x1<<24)
2503 #define NDCB0_CMD_TYPE (0x7<<21)
2504 #define NDCB0_NC (0x1<<20)
2505 #define NDCB0_DBC (0x1<<19)
2506 #define NDCB0_ADDR_CYC (0x7<<16)
2507 #define NDCB0_CMD2 (0xff<<8)
2508 #define NDCB0_CMD1 (0xff)
2509 #define MCMEM(s) MCMEM0
2510 #define MCATT(s) MCATT0
2511 #define MCIO(s) MCIO0
2512 #define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
2514 /* Maximum values for NAND Interface Timing Registers in DFC clock
2516 #define DFC_MAX_tCH 7
2517 #define DFC_MAX_tCS 7
2518 #define DFC_MAX_tWH 7
2519 #define DFC_MAX_tWP 7
2520 #define DFC_MAX_tRH 7
2521 #define DFC_MAX_tRP 15
2522 #define DFC_MAX_tR 65535
2523 #define DFC_MAX_tWHR 15
2524 #define DFC_MAX_tAR 15
2526 #define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
2527 #define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
2529 #else /* CONFIG_CPU_MONAHANS */
2533 #define MEMC_BASE 0x48000000 /* Base of Memory Controller */
2534 #define MDCNFG_OFFSET 0x0
2535 #define MDREFR_OFFSET 0x4
2536 #define MSC0_OFFSET 0x8
2537 #define MSC1_OFFSET 0xC
2538 #define MSC2_OFFSET 0x10
2539 #define MECR_OFFSET 0x14
2540 #define SXLCR_OFFSET 0x18
2541 #define SXCNFG_OFFSET 0x1C
2542 #define FLYCNFG_OFFSET 0x20
2543 #define SXMRS_OFFSET 0x24
2544 #define MCMEM0_OFFSET 0x28
2545 #define MCMEM1_OFFSET 0x2C
2546 #define MCATT0_OFFSET 0x30
2547 #define MCATT1_OFFSET 0x34
2548 #define MCIO0_OFFSET 0x38
2549 #define MCIO1_OFFSET 0x3C
2550 #define MDMRS_OFFSET 0x40
2552 #define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */
2553 #define MDCNFG_DE0 0x00000001
2554 #define MDCNFG_DE1 0x00000002
2555 #define MDCNFG_DE2 0x00010000
2556 #define MDCNFG_DE3 0x00020000
2557 #define MDCNFG_DWID0 0x00000004
2559 #define MDREFR 0x48000004 /* SDRAM Refresh Control Register */
2560 #define MSC0 0x48000008 /* Static Memory Control Register 0 */
2561 #define MSC1 0x4800000C /* Static Memory Control Register 1 */
2562 #define MSC2 0x48000010 /* Static Memory Control Register 2 */
2563 #define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2564 #define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2565 #define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */
2566 #define FLYCNFG 0x48000020
2567 #define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */
2568 #define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */
2569 #define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */
2570 #define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
2571 #define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */
2572 #define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */
2573 #define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */
2574 #define MDMRS 0x48000040 /* MRS value to be written to SDRAM */
2575 #define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2577 #define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */
2578 #define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */
2579 #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
2580 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2581 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2582 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2583 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2584 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2585 #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2586 #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2587 #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2588 #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2589 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2590 #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2591 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2592 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2594 #if defined(CONFIG_PXA27X)
2596 #define ARB_CNTRL 0x48000048 /* Arbiter Control Register */
2598 #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
2599 #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
2600 #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
2601 #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
2602 #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
2603 #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
2604 #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
2605 #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2606 #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2608 #endif /* CONFIG_PXA27X */
2611 #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */
2612 #define LCCR5 0x44000014 /* LCD Controller Control Register 5 */
2613 #define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
2614 #define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
2615 #define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */
2616 #define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */
2617 #define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */
2618 #define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */
2619 #define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */
2620 #define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */
2621 #define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */
2622 #define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */
2623 #define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */
2624 #define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */
2625 #define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */
2626 #define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */
2627 #define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */
2628 #define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */
2629 #define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */
2630 #define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */
2631 #define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */
2632 #define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */
2633 #define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */
2635 #define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */
2636 #define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */
2637 #define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */
2638 #define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */
2639 #define CCR 0x44000090 /* Cursor Control Register */
2641 #define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */
2642 #define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */
2644 #define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
2645 #define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
2647 #define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
2648 #define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
2649 #define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
2650 #define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
2651 #define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
2652 #define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
2654 #define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
2655 #define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
2656 #define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
2657 #define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
2658 #define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
2659 #define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
2661 #define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
2662 #define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
2663 #define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
2664 #define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
2665 #define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
2666 #define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
2668 #define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
2669 #define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
2670 #define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
2671 #define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
2672 #define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
2673 #define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
2675 #define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
2676 #define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
2677 #define CCR_CEN (1<<31) /* Enable bit for Cursor */
2679 /* Keypad controller */
2681 #define KPC 0x41500000 /* Keypad Interface Control register */
2682 #define KPDK 0x41500008 /* Keypad Interface Direct Key register */
2683 #define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */
2684 #define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */
2685 #define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */
2686 #define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
2687 #define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
2688 #define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
2689 #define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
2690 #define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */
2692 #define KPC_AS (0x1 << 30) /* Automatic Scan bit */
2693 #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
2694 #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
2695 #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
2696 #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
2697 #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
2698 #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
2699 #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
2700 #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
2701 #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
2702 #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
2703 #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
2704 #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
2705 #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
2706 #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */
2707 #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
2708 #define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */
2709 #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
2710 #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
2712 #define KPDK_DKP (0x1 << 31)
2713 #define KPDK_DK7 (0x1 << 7)
2714 #define KPDK_DK6 (0x1 << 6)
2715 #define KPDK_DK5 (0x1 << 5)
2716 #define KPDK_DK4 (0x1 << 4)
2717 #define KPDK_DK3 (0x1 << 3)
2718 #define KPDK_DK2 (0x1 << 2)
2719 #define KPDK_DK1 (0x1 << 1)
2720 #define KPDK_DK0 (0x1 << 0)
2722 #define KPREC_OF1 (0x1 << 31)
2723 #define kPREC_UF1 (0x1 << 30)
2724 #define KPREC_OF0 (0x1 << 15)
2725 #define KPREC_UF0 (0x1 << 14)
2727 #define KPMK_MKP (0x1 << 31)
2728 #define KPAS_SO (0x1 << 31)
2729 #define KPASMKPx_SO (0x1 << 31)
2731 #define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
2732 #define PSLR 0x40F00034
2733 #define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */
2734 #define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */
2735 #define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */
2736 #define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */
2737 #define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */
2738 #define OSMR4 0x40A00080 /* */
2739 #define OSCR4 0x40A00040 /* OS Timer Counter Register */
2740 #define OMCR4 0x40A000C0 /* */
2742 #endif /* CONFIG_PXA27X */
2744 #endif /* _PXA_REGS_H_ */
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