2 * arch/arm/include/asm/arch-pxa/macro.h
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef __ASM_ARCH_PXA_MACRO_H__
26 #define __ASM_ARCH_PXA_MACRO_H__
29 #include <asm/macro.h>
30 #include <asm/arch/pxa-regs.h>
33 * This macro performs a 32bit write to a memory location and makes sure the
34 * write operation really happened by performing a read back.
36 * Clobbered regs: r4, r5
38 .macro write32rb addr, data
46 * This macro waits according to OSCR incrementation
48 * Clobbered regs: r4, r5, r6
50 .macro pxa_wait_ticks ticks
62 * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
64 * Clobbered regs: r4, r5
67 write32 GPSR0, CONFIG_SYS_GPSR0_VAL
68 write32 GPSR1, CONFIG_SYS_GPSR1_VAL
69 write32 GPSR2, CONFIG_SYS_GPSR2_VAL
70 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
71 write32 GPSR3, CONFIG_SYS_GPSR3_VAL
74 write32 GPCR0, CONFIG_SYS_GPCR0_VAL
75 write32 GPCR1, CONFIG_SYS_GPCR1_VAL
76 write32 GPCR2, CONFIG_SYS_GPCR2_VAL
77 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
78 write32 GPCR3, CONFIG_SYS_GPCR3_VAL
81 write32 GPDR0, CONFIG_SYS_GPDR0_VAL
82 write32 GPDR1, CONFIG_SYS_GPDR1_VAL
83 write32 GPDR2, CONFIG_SYS_GPDR2_VAL
84 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
85 write32 GPDR3, CONFIG_SYS_GPDR3_VAL
88 write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
89 write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
90 write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
91 write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
92 write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
93 write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
94 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
95 write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
96 write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
99 write32 PSSR, CONFIG_SYS_PSSR_VAL
103 * This macro sets up the Memory controller of the PXA2xx CPU
105 * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
106 * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
107 * use this regs for other purpose inside this macro.
109 * Clobbered regs: r3, r4, r5, r6, r7
112 /* This comes handy when setting MDREFR */
116 * 1) Initialize Asynchronous static memory controller
120 write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
122 write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
124 write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
127 * 2) Initialize Card Interface
130 /* MECR: Memory Expansion Card Register */
131 write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
132 /* MCMEM0: Card Interface slot 0 timing */
133 write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
134 /* MCMEM1: Card Interface slot 1 timing */
135 write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
136 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
137 write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
138 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
139 write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
140 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
141 write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
142 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
143 write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
146 * 3) Configure Fly-By DMA register
149 write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
152 * 4) Initialize Timing for Sync Memory (SDCLK0)
156 * Before accessing MDREFR we need a valid DRI field, so we set
157 * this to power on defaults + DRI field.
159 ldr r5, [r3, #MDREFR_OFFSET]
161 bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
163 ldr r4, =CONFIG_SYS_MDREFR_VAL
166 lsr r4, #20 /* Get a valid DRI field */
168 orr r5, r5, r4 /* MDREFR user config with correct DRI */
170 orr r5, #MDREFR_K0RUN
171 orr r5, #MDREFR_SLFRSH
173 bic r5, #MDREFR_E1PIN
175 str r5, [r3, #MDREFR_OFFSET]
176 ldr r4, [r3, #MDREFR_OFFSET]
179 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
182 /* Initialize SXCNFG register. Assert the enable bits.
184 * Write SXMRS to cause an MRS command to all enabled banks of
185 * synchronous static memory. Note that SXLCR need not be written
188 write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
191 * 6) Initialize SDRAM
194 bic r7, #MDREFR_SLFRSH
195 str r7, [r3, #MDREFR_OFFSET]
196 ldr r4, [r3, #MDREFR_OFFSET]
198 orr r7, #MDREFR_E1PIN
199 str r7, [r3, #MDREFR_OFFSET]
200 ldr r4, [r3, #MDREFR_OFFSET]
203 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
204 * but not enable each SDRAM partition pair.
207 /* Fetch platform value of MDCNFG */
208 ldr r4, =CONFIG_SYS_MDCNFG_VAL
209 /* Disable all sdram banks */
210 bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
211 bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
212 /* Write initial value of MDCNFG, w/o enabling sdram banks */
213 str r4, [r3, #MDCNFG_OFFSET]
214 ldr r4, [r3, #MDCNFG_OFFSET]
216 /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
220 * 8) Trigger a number (usually 8) refresh cycles by attempting
221 * non-burst read or write accesses to disabled SDRAM, as commonly
222 * specified in the power up sequence documented in SDRAM data
223 * sheets. The address(es) used for this purpose must not be
227 ldr r4, =CONFIG_SYS_DRAM_BASE
233 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
236 ldr r5, =CONFIG_SYS_MDCNFG_VAL
237 ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
239 ldr r4, [r3, #MDCNFG_OFFSET]
241 str r4, [r3, #MDCNFG_OFFSET]
242 ldr r4, [r3, #MDCNFG_OFFSET]
248 ldr r4, =CONFIG_SYS_MDMRS_VAL
249 str r4, [r3, #MDMRS_OFFSET]
250 ldr r4, [r3, #MDMRS_OFFSET]
256 ldr r4, [r3, #MDREFR_OFFSET]
257 and r7, r7, #MDREFR_APD
259 str r4, [r3, #MDREFR_OFFSET]
260 ldr r4, [r3, #MDREFR_OFFSET]
264 * This macro tests if the CPU woke up from sleep and eventually resumes
266 * Clobbered regs: r4, r5
271 and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
287 * This macro disables all interupts on PXA2xx/PXA3xx CPU
289 * Clobbered regs: r4, r5
291 .macro pxa_intr_setup
294 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
301 * This macro configures clock on PXA2xx/PXA3xx CPU
303 * Clobbered regs: r4, r5
305 .macro pxa_clock_setup
306 /* Disable the peripheral clocks, and set the core clock frequency */
308 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
309 write32 CKEN, CONFIG_SYS_CKEN
312 write32 CCCR, CONFIG_SYS_CCCR
315 /* enable the 32Khz oscillator for RTC and PowerManager */
316 write32 OSCC, #OSCC_OON
319 /* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
327 #endif /* __ASSEMBLY__ */
328 #endif /* __ASM_ARCH_PXA_MACRO_H__ */