3 * Texas Instruments, <www.ti.com>
6 * Aneesh V <aneesh@ti.com>
8 * Derived from OMAP3 work by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
18 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
19 #include <asm/types.h>
20 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
23 * L4 Peripherals - L4 Wakeup and L4 Core now
25 #define OMAP44XX_L4_CORE_BASE 0x4A000000
26 #define OMAP44XX_L4_WKUP_BASE 0x4A300000
27 #define OMAP44XX_L4_PER_BASE 0x48000000
29 #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
30 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
31 #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
32 #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
35 #define CONTROL_ID_CODE 0x4A002204
37 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
38 #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
39 #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
40 #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
41 #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
42 #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
43 #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
44 #define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
47 #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
48 #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
49 #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
51 /* General Purpose Timers */
52 #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
53 #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
54 #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
56 /* Watchdog Timer2 - MPU watchdog */
57 #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
60 #define OMAP44XX_GPMC_BASE 0x50000000
63 * Hardware Register Details
67 #define WD_UNLOCK1 0xAAAA
68 #define WD_UNLOCK2 0x5555
71 #define TCLR_ST (0x1 << 0)
72 #define TCLR_AR (0x1 << 1)
73 #define TCLR_PRE (0x1 << 5)
76 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
77 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
78 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
79 #define CONTROL_EFUSE_2_OVERRIDE 0x99084000
82 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
83 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
84 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
85 #define LPDDR2IO_GR10_WD_MASK (3 << 17)
86 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
89 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
91 #define MMC1_PWRDNZ (1 << 26)
92 #define MMC1_PBIASLITE_PWRDNZ (1 << 22)
93 #define MMC1_PBIASLITE_VMODE (1 << 21)
98 unsigned char res[0x10];
99 unsigned int s32k_cr; /* 0x10 */
102 #define DEVICE_TYPE_SHIFT (0x8)
103 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
104 #define DEVICE_GP 0x3
106 #endif /* __ASSEMBLY__ */
109 * Non-secure SRAM Addresses
110 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
111 * at 0x40304000(EMU base) so that our code works for both EMU and GP
113 #define NON_SECURE_SRAM_START 0x40304000
114 #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
115 #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
116 /* base address for indirect vectors (internal boot mode) */
117 #define SRAM_ROM_VECT_BASE 0x4030D000
120 #define OMAP_ABB_SETTLING_TIME 50
121 #define OMAP_ABB_CLOCK_CYCLES 16
123 /* ABB tranxdone mask */
124 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)