arch/arm/include/asm/arch-omap4/omap.h

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Authors:
   6  *      Aneesh V <aneesh@ti.com>
   7  *
   8  * Derived from OMAP3 work by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef _OMAP4_H_
  16 #define _OMAP4_H_
  17
  18 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  19 #include <asm/types.h>
  20 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  21
  22 /*
  23  * L4 Peripherals - L4 Wakeup and L4 Core now
  24  */
  25 #define OMAP44XX_L4_CORE_BASE   0x4A000000
  26 #define OMAP44XX_L4_WKUP_BASE   0x4A300000
  27 #define OMAP44XX_L4_PER_BASE    0x48000000
  28
  29 #define OMAP44XX_DRAM_ADDR_SPACE_START  0x80000000
  30 #define OMAP44XX_DRAM_ADDR_SPACE_END    0xD0000000
  31 #define DRAM_ADDR_SPACE_START   OMAP44XX_DRAM_ADDR_SPACE_START
  32 #define DRAM_ADDR_SPACE_END     OMAP44XX_DRAM_ADDR_SPACE_END
  33
  34 /* CONTROL_ID_CODE */
  35 #define CONTROL_ID_CODE         0x4A002204
  36 #define STD_FUSE_DIE_ID_0       0x4A002200
  37 #define STD_FUSE_DIE_ID_1       0x4A002208
  38 #define STD_FUSE_DIE_ID_2       0x4A00220c
  39 #define STD_FUSE_DIE_ID_3       0x4A002210
  40
  41 #define OMAP4_CONTROL_ID_CODE_ES1_0     0x0B85202F
  42 #define OMAP4_CONTROL_ID_CODE_ES2_0     0x1B85202F
  43 #define OMAP4_CONTROL_ID_CODE_ES2_1     0x3B95C02F
  44 #define OMAP4_CONTROL_ID_CODE_ES2_2     0x4B95C02F
  45 #define OMAP4_CONTROL_ID_CODE_ES2_3     0x6B95C02F
  46 #define OMAP4460_CONTROL_ID_CODE_ES1_0  0x0B94E02F
  47 #define OMAP4460_CONTROL_ID_CODE_ES1_1  0x2B94E02F
  48 #define OMAP4470_CONTROL_ID_CODE_ES1_0  0x0B97502F
  49
  50 /* UART */
  51 #define UART1_BASE              (OMAP44XX_L4_PER_BASE + 0x6a000)
  52 #define UART2_BASE              (OMAP44XX_L4_PER_BASE + 0x6c000)
  53 #define UART3_BASE              (OMAP44XX_L4_PER_BASE + 0x20000)
  54
  55 /* General Purpose Timers */
  56 #define GPT1_BASE               (OMAP44XX_L4_WKUP_BASE + 0x18000)
  57 #define GPT2_BASE               (OMAP44XX_L4_PER_BASE  + 0x32000)
  58 #define GPT3_BASE               (OMAP44XX_L4_PER_BASE  + 0x34000)
  59
  60 /* Watchdog Timer2 - MPU watchdog */
  61 #define WDT2_BASE               (OMAP44XX_L4_WKUP_BASE + 0x14000)
  62
  63 /* GPMC */
  64 #define OMAP44XX_GPMC_BASE      0x50000000
  65
  66 /*
  67  * Hardware Register Details
  68  */
  69
  70 /* Watchdog Timer */
  71 #define WD_UNLOCK1              0xAAAA
  72 #define WD_UNLOCK2              0x5555
  73
  74 /* GP Timer */
  75 #define TCLR_ST                 (0x1 << 0)
  76 #define TCLR_AR                 (0x1 << 1)
  77 #define TCLR_PRE                (0x1 << 5)
  78
  79 /* Control Module */
  80 #define LDOSRAM_ACTMODE_VSET_IN_MASK    (0x1F << 5)
  81 #define LDOSRAM_VOLT_CTRL_OVERRIDE      0x0401040f
  82 #define CONTROL_EFUSE_1_OVERRIDE        0x1C4D0110
  83 #define CONTROL_EFUSE_2_OVERRIDE        0x99084000
  84
  85 /* LPDDR2 IO regs */
  86 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN      0x1C1C1C1C
  87 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER    0x9E9E9E9E
  88 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN     0x7C7C7C7C
  89 #define LPDDR2IO_GR10_WD_MASK                           (3 << 17)
  90 #define CONTROL_LPDDR2IO_3_VAL          0xA0888C0F
  91
  92 /* CONTROL_EFUSE_2 */
  93 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1            0x00ffc000
  94
  95 #define MMC1_PWRDNZ                                     (1 << 26)
  96 #define MMC1_PBIASLITE_PWRDNZ                           (1 << 22)
  97 #define MMC1_PBIASLITE_VMODE                            (1 << 21)
  98
  99 #ifndef __ASSEMBLY__
 100
 101 struct s32ktimer {
 102         unsigned char res[0x10];
 103         unsigned int s32k_cr;   /* 0x10 */
 104 };
 105
 106 #define DEVICE_TYPE_SHIFT (0x8)
 107 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
 108 #define DEVICE_GP 0x3
 109
 110 #endif /* __ASSEMBLY__ */
 111
 112 /*
 113  * Non-secure SRAM Addresses
 114  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
 115  * at 0x40304000(EMU base) so that our code works for both EMU and GP
 116  */
 117 #define NON_SECURE_SRAM_START   0x40304000
 118 #define NON_SECURE_SRAM_END     0x4030E000      /* Not inclusive */
 119 #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
 120 /* base address for indirect vectors (internal boot mode) */
 121 #define SRAM_ROM_VECT_BASE      0x4030D000
 122
 123 /* ABB settings */
 124 #define OMAP_ABB_SETTLING_TIME          50
 125 #define OMAP_ABB_CLOCK_CYCLES           16
 126
 127 /* ABB tranxdone mask */
 128 #define OMAP_ABB_MPU_TXDONE_MASK        (0x1 << 7)
 129
 130 #endif