3 * Texas Instruments, <www.ti.com>
5 * Aneesh V <aneesh@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _CLOCKS_OMAP4_H_
26 #define _CLOCKS_OMAP4_H_
28 #include <asm/omap_common.h>
31 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
32 * loop, allow for a minimum of 2 ms wait (in reality the wait will be
33 * much more than that)
35 #define LDELAY 1000000
37 #define CM_CLKMODE_DPLL_CORE 0x4A004120
38 #define CM_CLKMODE_DPLL_PER 0x4A008140
39 #define CM_CLKMODE_DPLL_MPU 0x4A004160
40 #define CM_CLKSEL_CORE 0x4A004100
42 /* DPLL register offsets */
43 #define CM_CLKMODE_DPLL 0
44 #define CM_IDLEST_DPLL 0x4
45 #define CM_AUTOIDLE_DPLL 0x8
46 #define CM_CLKSEL_DPLL 0xC
47 #define CM_DIV_M2_DPLL 0x10
48 #define CM_DIV_M3_DPLL 0x14
49 #define CM_DIV_M4_DPLL 0x18
50 #define CM_DIV_M5_DPLL 0x1C
51 #define CM_DIV_M6_DPLL 0x20
52 #define CM_DIV_M7_DPLL 0x24
54 #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
57 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0
58 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
59 #define CM_DLL_CTRL_NO_OVERRIDE 0
62 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
63 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
64 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
65 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
66 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
67 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
68 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
69 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
70 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
71 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
72 #define CM_CLKMODE_DPLL_EN_SHIFT 0
73 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
75 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
76 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
78 #define DPLL_EN_STOP 1
79 #define DPLL_EN_MN_BYPASS 4
80 #define DPLL_EN_LOW_POWER_BYPASS 5
81 #define DPLL_EN_FAST_RELOCK_BYPASS 6
82 #define DPLL_EN_LOCK 7
84 /* CM_IDLEST_DPLL fields */
85 #define ST_DPLL_CLK_MASK 1
88 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
89 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
90 #define CM_CLKSEL_DPLL_M_SHIFT 8
91 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
92 #define CM_CLKSEL_DPLL_N_SHIFT 0
93 #define CM_CLKSEL_DPLL_N_MASK 0x7F
94 #define CM_CLKSEL_DCC_EN_SHIFT 22
95 #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
97 #define OMAP4_DPLL_MAX_N 127
100 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
103 #define CLKSEL_CORE_SHIFT 0
104 #define CLKSEL_L3_SHIFT 4
105 #define CLKSEL_L4_SHIFT 8
107 #define CLKSEL_CORE_X2_DIV_1 0
108 #define CLKSEL_L3_CORE_DIV_2 1
109 #define CLKSEL_L4_L3_DIV_2 1
111 /* CM_ABE_PLL_REF_CLKSEL */
112 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
113 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
114 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
115 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
117 /* CM_BYPCLK_DPLL_IVA */
118 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
119 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
121 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
123 /* CM_SHADOW_FREQ_CONFIG1 */
124 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
125 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
126 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
128 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
129 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
131 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
132 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
134 /*CM_<clock_domain>__CLKCTRL */
135 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
136 #define CD_CLKCTRL_CLKTRCTRL_MASK 3
138 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
139 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
140 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
141 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
144 /* CM_<clock_domain>_<module>_CLKCTRL */
145 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
146 #define MODULE_CLKCTRL_MODULEMODE_MASK 3
147 #define MODULE_CLKCTRL_IDLEST_SHIFT 16
148 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
150 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
151 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
152 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
154 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
155 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
156 #define MODULE_CLKCTRL_IDLEST_IDLE 2
157 #define MODULE_CLKCTRL_IDLEST_DISABLED 3
159 /* CM_L4PER_GPIO4_CLKCTRL */
160 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
162 /* CM_L3INIT_HSMMCn_CLKCTRL */
163 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
165 /* CM_WKUP_GPTIMER1_CLKCTRL */
166 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
168 /* CM_CAM_ISS_CLKCTRL */
169 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
171 /* CM_DSS_DSS_CLKCTRL */
172 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
174 /* CM_L3INIT_USBPHY_CLKCTRL */
175 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
177 /* CM_MPU_MPU_CLKCTRL */
178 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
179 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
180 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
181 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
183 /* Clock frequencies */
184 #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
185 #define OMAP_SYS_CLK_IND_38_4_MHZ 6
186 #define OMAP_32K_CLK_FREQ 32768
188 /* PRM_VC_VAL_BYPASS */
189 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
192 #define SMPS_I2C_SLAVE_ADDR 0x12
193 #define SMPS_REG_ADDR_VCORE1 0x55
194 #define SMPS_REG_ADDR_VCORE2 0x5B
195 #define SMPS_REG_ADDR_VCORE3 0x61
197 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
198 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
201 #define TPS62361_I2C_SLAVE_ADDR 0x60
202 #define TPS62361_REG_ADDR_SET0 0x0
203 #define TPS62361_REG_ADDR_SET1 0x1
204 #define TPS62361_REG_ADDR_SET2 0x2
205 #define TPS62361_REG_ADDR_SET3 0x3
206 #define TPS62361_REG_ADDR_CTRL 0x4
207 #define TPS62361_REG_ADDR_TEMP 0x5
208 #define TPS62361_REG_ADDR_RMP_CTRL 0x6
209 #define TPS62361_REG_ADDR_CHIP_ID 0x8
210 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9
212 #define TPS62361_BASE_VOLT_MV 500
213 #define TPS62361_VSEL0_GPIO 7
215 /* AUXCLKx reg fields */
216 #define AUXCLK_ENABLE_MASK (1 << 8)
217 #define AUXCLK_SRCSELECT_SHIFT 1
218 #define AUXCLK_SRCSELECT_MASK (3 << 1)
219 #define AUXCLK_CLKDIV_SHIFT 16
220 #define AUXCLK_CLKDIV_MASK (0xF << 16)
222 #define AUXCLK_SRCSELECT_SYS_CLK 0
223 #define AUXCLK_SRCSELECT_CORE_DPLL 1
224 #define AUXCLK_SRCSELECT_PER_DPLL 2
225 #define AUXCLK_SRCSELECT_ALTERNATE 3
227 #define AUXCLK_CLKDIV_2 1
228 #define AUXCLK_CLKDIV_16 0xF
231 #define ALTCLKSRC_MODE_MASK 3
232 #define ALTCLKSRC_ENABLE_INT_MASK 4
233 #define ALTCLKSRC_ENABLE_EXT_MASK 8
235 #define ALTCLKSRC_MODE_ACTIVE 1
237 /* Defines for DPLL setup */
238 #define DPLL_LOCKED_FREQ_TOLERANCE_0 0
239 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
240 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
242 #define DPLL_NO_LOCK 0
245 struct omap4_scrm_regs {
246 u32 revision; /* 0x0000 */
248 u32 clksetuptime; /* 0x0100 */
249 u32 pmicsetuptime; /* 0x0104 */
251 u32 altclksrc; /* 0x0110 */
253 u32 c2cclkm; /* 0x011c */
255 u32 extclkreq; /* 0x0200 */
256 u32 accclkreq; /* 0x0204 */
257 u32 pwrreq; /* 0x0208 */
259 u32 auxclkreq0; /* 0x0210 */
260 u32 auxclkreq1; /* 0x0214 */
261 u32 auxclkreq2; /* 0x0218 */
262 u32 auxclkreq3; /* 0x021c */
263 u32 auxclkreq4; /* 0x0220 */
264 u32 auxclkreq5; /* 0x0224 */
266 u32 c2cclkreq; /* 0x0234 */
268 u32 auxclk0; /* 0x0310 */
269 u32 auxclk1; /* 0x0314 */
270 u32 auxclk2; /* 0x0318 */
271 u32 auxclk3; /* 0x031c */
272 u32 auxclk4; /* 0x0320 */
273 u32 auxclk5; /* 0x0324 */
275 u32 rsttime_reg; /* 0x0400 */
277 u32 c2crstctrl; /* 0x041c */
278 u32 extpwronrstctrl; /* 0x0420 */
280 u32 extwarmrstst_reg; /* 0x0510 */
281 u32 apewarmrstst_reg; /* 0x0514 */
283 u32 c2cwarmrstst_reg; /* 0x051C */
285 #endif /* _CLOCKS_OMAP4_H_ */