1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Marvell International Ltd.
5 * https://spdx.org/licenses
13 * Configuration and status register (CSR) address and type definitions for
16 * This file is auto generated. Do not edit.
21 * Enumeration nix_af_int_vec_e
23 * NIX Admin Function Interrupt Vector Enumeration Enumerates the NIX AF
24 * MSI-X interrupt vectors.
26 #define NIX_AF_INT_VEC_E_AF_ERR (3)
27 #define NIX_AF_INT_VEC_E_AQ_DONE (2)
28 #define NIX_AF_INT_VEC_E_GEN (1)
29 #define NIX_AF_INT_VEC_E_POISON (4)
30 #define NIX_AF_INT_VEC_E_RVU (0)
33 * Enumeration nix_aq_comp_e
35 * NIX Completion Enumeration Enumerates the values of
36 * NIX_AQ_RES_S[COMPCODE].
38 #define NIX_AQ_COMP_E_CTX_FAULT (4)
39 #define NIX_AQ_COMP_E_CTX_POISON (3)
40 #define NIX_AQ_COMP_E_GOOD (1)
41 #define NIX_AQ_COMP_E_LOCKERR (5)
42 #define NIX_AQ_COMP_E_NOTDONE (0)
43 #define NIX_AQ_COMP_E_SQB_ALLOC_FAIL (6)
44 #define NIX_AQ_COMP_E_SWERR (2)
47 * Enumeration nix_aq_ctype_e
49 * NIX Context Type Enumeration Enumerates NIX_AQ_INST_S[CTYPE] values.
51 #define NIX_AQ_CTYPE_E_CQ (2)
52 #define NIX_AQ_CTYPE_E_DYNO (5)
53 #define NIX_AQ_CTYPE_E_MCE (3)
54 #define NIX_AQ_CTYPE_E_RQ (0)
55 #define NIX_AQ_CTYPE_E_RSS (4)
56 #define NIX_AQ_CTYPE_E_SQ (1)
59 * Enumeration nix_aq_instop_e
61 * NIX Admin Queue Opcode Enumeration Enumerates NIX_AQ_INST_S[OP]
64 #define NIX_AQ_INSTOP_E_INIT (1)
65 #define NIX_AQ_INSTOP_E_LOCK (4)
66 #define NIX_AQ_INSTOP_E_NOP (0)
67 #define NIX_AQ_INSTOP_E_READ (3)
68 #define NIX_AQ_INSTOP_E_UNLOCK (5)
69 #define NIX_AQ_INSTOP_E_WRITE (2)
72 * Enumeration nix_chan_e
74 * NIX Channel Number Enumeration Enumerates the receive and transmit
75 * channels, and values of NIX_RX_PARSE_S[CHAN],
76 * NIX_SQ_CTX_S[DEFAULT_CHAN]. CNXXXX implements a subset of these
77 * channels. Specifically, only channels for links enumerated by
78 * NIX_LINK_E are implemented. Internal: P2X/X2P channel enumeration for
81 #define NIX_CHAN_E_CGXX_LMACX_CHX(a, b, c) \
82 (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
83 #define NIX_CHAN_E_LBKX_CHX(a, b) (0 + 0x100 * (a) + (b))
84 #define NIX_CHAN_E_RX(a) (0 + 0x100 * (a))
85 #define NIX_CHAN_E_SDP_CHX(a) (0x700 + (a))
88 * Enumeration nix_colorresult_e
90 * NIX Color Result Enumeration Enumerates the values of
91 * NIX_MEM_RESULT_S[COLOR], NIX_AF_TL1()_MD_DEBUG1[COLOR] and
92 * NIX_AF_TL1()_MD_DEBUG1[COLOR].
94 #define NIX_COLORRESULT_E_GREEN (0)
95 #define NIX_COLORRESULT_E_RED_DROP (3)
96 #define NIX_COLORRESULT_E_RED_SEND (2)
97 #define NIX_COLORRESULT_E_YELLOW (1)
100 * Enumeration nix_cqerrint_e
102 * NIX Completion Queue Interrupt Enumeration Enumerates the bit index of
103 * NIX_CQ_CTX_S[CQ_ERR_INT,CQ_ERR_INT_ENA].
105 #define NIX_CQERRINT_E_CQE_FAULT (2)
106 #define NIX_CQERRINT_E_DOOR_ERR (0)
107 #define NIX_CQERRINT_E_WR_FULL (1)
110 * Enumeration nix_intf_e
112 * NIX Interface Number Enumeration Enumerates the bit index of
113 * NIX_AF_STATUS[CALIBRATE_STATUS].
115 #define NIX_INTF_E_CGXX(a) (0 + (a))
116 #define NIX_INTF_E_LBKX(a) (3 + (a))
117 #define NIX_INTF_E_SDP (4)
120 * Enumeration nix_lf_int_vec_e
122 * NIX Local Function Interrupt Vector Enumeration Enumerates the NIX
123 * MSI-X interrupt vectors per LF.
125 #define NIX_LF_INT_VEC_E_CINTX(a) (0x40 + (a))
126 #define NIX_LF_INT_VEC_E_ERR_INT (0x81)
127 #define NIX_LF_INT_VEC_E_GINT (0x80)
128 #define NIX_LF_INT_VEC_E_POISON (0x82)
129 #define NIX_LF_INT_VEC_E_QINTX(a) (0 + (a))
132 * Enumeration nix_link_e
134 * NIX Link Number Enumeration Enumerates the receive and transmit links,
135 * and LINK index of NIX_AF_RX_LINK()_CFG, NIX_AF_RX_LINK()_WRR_CFG,
136 * NIX_AF_TX_LINK()_NORM_CREDIT, NIX_AF_TX_LINK()_HW_XOFF and
137 * NIX_AF_TL3_TL2()_LINK()_CFG.
139 #define NIX_LINK_E_CGXX_LMACX(a, b) (0 + 4 * (a) + (b))
140 #define NIX_LINK_E_LBKX(a) (0xc + (a))
141 #define NIX_LINK_E_MC (0xe)
142 #define NIX_LINK_E_SDP (0xd)
145 * Enumeration nix_lsoalg_e
147 * NIX Large Send Offload Algorithm Enumeration Enumerates
148 * NIX_AF_LSO_FORMAT()_FIELD()[ALG] values. Specifies algorithm for
149 * modifying the associated LSO packet field.
151 #define NIX_LSOALG_E_ADD_OFFSET (3)
152 #define NIX_LSOALG_E_ADD_PAYLEN (2)
153 #define NIX_LSOALG_E_ADD_SEGNUM (1)
154 #define NIX_LSOALG_E_NOP (0)
155 #define NIX_LSOALG_E_TCP_FLAGS (4)
158 * Enumeration nix_maxsqesz_e
160 * NIX Maximum SQE Size Enumeration Enumerates the values of
161 * NIX_SQ_CTX_S[MAX_SQE_SIZE].
163 #define NIX_MAXSQESZ_E_W16 (0)
164 #define NIX_MAXSQESZ_E_W8 (1)
167 * Enumeration nix_mdtype_e
169 * NIX Meta Descriptor Type Enumeration Enumerates values of
170 * NIX_AF_MDQ()_MD_DEBUG[MD_TYPE].
172 #define NIX_MDTYPE_E_FLUSH (1)
173 #define NIX_MDTYPE_E_PMD (2)
174 #define NIX_MDTYPE_E_RSVD (0)
177 * Enumeration nix_mnqerr_e
179 * NIX Meta-Descriptor Enqueue Error Enumeration Enumerates
180 * NIX_LF_MNQ_ERR_DBG[ERRCODE] values.
182 #define NIX_MNQERR_E_CQ_QUERY_ERR (6)
183 #define NIX_MNQERR_E_LSO_ERR (5)
184 #define NIX_MNQERR_E_MAXLEN_ERR (8)
185 #define NIX_MNQERR_E_MAX_SQE_SIZE_ERR (7)
186 #define NIX_MNQERR_E_SQB_FAULT (2)
187 #define NIX_MNQERR_E_SQB_POISON (3)
188 #define NIX_MNQERR_E_SQE_SIZEM1_ZERO (9)
189 #define NIX_MNQERR_E_SQ_CTX_FAULT (0)
190 #define NIX_MNQERR_E_SQ_CTX_POISON (1)
191 #define NIX_MNQERR_E_TOTAL_ERR (4)
194 * Enumeration nix_ndc_rx_port_e
196 * NIX Receive NDC Port Enumeration Enumerates NIX receive NDC
197 * (NDC_IDX_E::NIX()_RX) ports and the PORT index of
198 * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC.
200 #define NIX_NDC_RX_PORT_E_AQ (0)
201 #define NIX_NDC_RX_PORT_E_CINT (2)
202 #define NIX_NDC_RX_PORT_E_CQ (1)
203 #define NIX_NDC_RX_PORT_E_MC (3)
204 #define NIX_NDC_RX_PORT_E_PKT (4)
205 #define NIX_NDC_RX_PORT_E_RQ (5)
208 * Enumeration nix_ndc_tx_port_e
210 * NIX Transmit NDC Port Enumeration Enumerates NIX transmit NDC
211 * (NDC_IDX_E::NIX()_TX) ports and the PORT index of
212 * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC.
214 #define NIX_NDC_TX_PORT_E_DEQ (3)
215 #define NIX_NDC_TX_PORT_E_DMA (4)
216 #define NIX_NDC_TX_PORT_E_ENQ (1)
217 #define NIX_NDC_TX_PORT_E_LMT (0)
218 #define NIX_NDC_TX_PORT_E_MNQ (2)
219 #define NIX_NDC_TX_PORT_E_XQE (5)
222 * Enumeration nix_re_opcode_e
224 * NIX Receive Error Opcode Enumeration Enumerates
225 * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] =
228 #define NIX_RE_OPCODE_E_OL2_LENMISM (0x12)
229 #define NIX_RE_OPCODE_E_OVERSIZE (0x11)
230 #define NIX_RE_OPCODE_E_RE_DMAPKT (0xf)
231 #define NIX_RE_OPCODE_E_RE_FCS (7)
232 #define NIX_RE_OPCODE_E_RE_FCS_RCV (8)
233 #define NIX_RE_OPCODE_E_RE_JABBER (2)
234 #define NIX_RE_OPCODE_E_RE_NONE (0)
235 #define NIX_RE_OPCODE_E_RE_PARTIAL (1)
236 #define NIX_RE_OPCODE_E_RE_RX_CTL (0xb)
237 #define NIX_RE_OPCODE_E_RE_SKIP (0xc)
238 #define NIX_RE_OPCODE_E_RE_TERMINATE (9)
239 #define NIX_RE_OPCODE_E_UNDERSIZE (0x10)
242 * Enumeration nix_redalg_e
244 * NIX Red Algorithm Enumeration Enumerates the different algorithms of
245 * NIX_SEND_EXT_S[SHP_RA].
247 #define NIX_REDALG_E_DISCARD (3)
248 #define NIX_REDALG_E_SEND (1)
249 #define NIX_REDALG_E_STALL (2)
250 #define NIX_REDALG_E_STD (0)
253 * Enumeration nix_rqint_e
255 * NIX Receive Queue Interrupt Enumeration Enumerates the bit index of
256 * NIX_RQ_CTX_S[RQ_INT,RQ_INT_ENA].
258 #define NIX_RQINT_E_DROP (0)
259 #define NIX_RQINT_E_RX(a) (0 + (a))
260 #define NIX_RQINT_E_RED (1)
263 * Enumeration nix_rx_actionop_e
265 * NIX Receive Action Opcode Enumeration Enumerates the values of
266 * NIX_RX_ACTION_S[OP].
268 #define NIX_RX_ACTIONOP_E_DROP (0)
269 #define NIX_RX_ACTIONOP_E_MCAST (3)
270 #define NIX_RX_ACTIONOP_E_MIRROR (6)
271 #define NIX_RX_ACTIONOP_E_PF_FUNC_DROP (5)
272 #define NIX_RX_ACTIONOP_E_RSS (4)
273 #define NIX_RX_ACTIONOP_E_UCAST (1)
274 #define NIX_RX_ACTIONOP_E_UCAST_IPSEC (2)
277 * Enumeration nix_rx_mcop_e
279 * NIX Receive Multicast/Mirror Opcode Enumeration Enumerates the values
280 * of NIX_RX_MCE_S[OP].
282 #define NIX_RX_MCOP_E_RQ (0)
283 #define NIX_RX_MCOP_E_RSS (1)
286 * Enumeration nix_rx_perrcode_e
288 * NIX Receive Protocol Error Code Enumeration Enumerates
289 * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] =
292 #define NIX_RX_PERRCODE_E_BUFS_OFLOW (0xa)
293 #define NIX_RX_PERRCODE_E_DATA_FAULT (8)
294 #define NIX_RX_PERRCODE_E_IL3_LEN (0x20)
295 #define NIX_RX_PERRCODE_E_IL4_CHK (0x22)
296 #define NIX_RX_PERRCODE_E_IL4_LEN (0x21)
297 #define NIX_RX_PERRCODE_E_IL4_PORT (0x23)
298 #define NIX_RX_PERRCODE_E_MCAST_FAULT (4)
299 #define NIX_RX_PERRCODE_E_MCAST_POISON (6)
300 #define NIX_RX_PERRCODE_E_MEMOUT (9)
301 #define NIX_RX_PERRCODE_E_MIRROR_FAULT (5)
302 #define NIX_RX_PERRCODE_E_MIRROR_POISON (7)
303 #define NIX_RX_PERRCODE_E_NPC_RESULT_ERR (2)
304 #define NIX_RX_PERRCODE_E_OL3_LEN (0x10)
305 #define NIX_RX_PERRCODE_E_OL4_CHK (0x12)
306 #define NIX_RX_PERRCODE_E_OL4_LEN (0x11)
307 #define NIX_RX_PERRCODE_E_OL4_PORT (0x13)
310 * Enumeration nix_send_status_e
312 * NIX Send Completion Status Enumeration Enumerates values of
313 * NIX_SEND_COMP_S[STATUS] and NIX_LF_SEND_ERR_DBG[ERRCODE].
315 #define NIX_SEND_STATUS_E_DATA_FAULT (0x16)
316 #define NIX_SEND_STATUS_E_DATA_POISON (0x17)
317 #define NIX_SEND_STATUS_E_GOOD (0)
318 #define NIX_SEND_STATUS_E_INVALID_SUBDC (0x14)
319 #define NIX_SEND_STATUS_E_JUMP_FAULT (7)
320 #define NIX_SEND_STATUS_E_JUMP_POISON (8)
321 #define NIX_SEND_STATUS_E_LOCK_VIOL (0x21)
322 #define NIX_SEND_STATUS_E_NPC_DROP_ACTION (0x20)
323 #define NIX_SEND_STATUS_E_NPC_MCAST_ABORT (0x24)
324 #define NIX_SEND_STATUS_E_NPC_MCAST_CHAN_ERR (0x23)
325 #define NIX_SEND_STATUS_E_NPC_UCAST_CHAN_ERR (0x22)
326 #define NIX_SEND_STATUS_E_NPC_VTAG_PTR_ERR (0x25)
327 #define NIX_SEND_STATUS_E_NPC_VTAG_SIZE_ERR (0x26)
328 #define NIX_SEND_STATUS_E_SEND_CRC_ERR (0x10)
329 #define NIX_SEND_STATUS_E_SEND_EXT_ERR (6)
330 #define NIX_SEND_STATUS_E_SEND_HDR_ERR (5)
331 #define NIX_SEND_STATUS_E_SEND_IMM_ERR (0x11)
332 #define NIX_SEND_STATUS_E_SEND_MEM_ERR (0x13)
333 #define NIX_SEND_STATUS_E_SEND_MEM_FAULT (0x27)
334 #define NIX_SEND_STATUS_E_SEND_SG_ERR (0x12)
335 #define NIX_SEND_STATUS_E_SQB_FAULT (3)
336 #define NIX_SEND_STATUS_E_SQB_POISON (4)
337 #define NIX_SEND_STATUS_E_SQ_CTX_FAULT (1)
338 #define NIX_SEND_STATUS_E_SQ_CTX_POISON (2)
339 #define NIX_SEND_STATUS_E_SUBDC_ORDER_ERR (0x15)
342 * Enumeration nix_sendcrcalg_e
344 * NIX Send CRC Algorithm Enumeration Enumerates the CRC algorithm used,
345 * see NIX_SEND_CRC_S[ALG].
347 #define NIX_SENDCRCALG_E_CRC32 (0)
348 #define NIX_SENDCRCALG_E_CRC32C (1)
349 #define NIX_SENDCRCALG_E_ONES16 (2)
352 * Enumeration nix_sendl3type_e
354 * NIX Send Layer 3 Header Type Enumeration Enumerates values of
355 * NIX_SEND_HDR_S[OL3TYPE], NIX_SEND_HDR_S[IL3TYPE]. Internal: Encoding
356 * matches DPDK TX IP types: \<pre\> PKT_TX_IP_CKSUM (1ULL \<\< 54)
357 * PKT_TX_IPV4 (1ULL \<\< 55) PKT_TX_IPV6 (1ULL \<\<
358 * 56) PKT_TX_OUTER_IP_CKSUM(1ULL \<\< 58) PKT_TX_OUTER_IPV4 (1ULL
359 * \<\< 59) PKT_TX_OUTER_IPV6 (1ULL \<\< 60) \</pre\>
361 #define NIX_SENDL3TYPE_E_IP4 (2)
362 #define NIX_SENDL3TYPE_E_IP4_CKSUM (3)
363 #define NIX_SENDL3TYPE_E_IP6 (4)
364 #define NIX_SENDL3TYPE_E_NONE (0)
367 * Enumeration nix_sendl4type_e
369 * NIX Send Layer 4 Header Type Enumeration Enumerates values of
370 * NIX_SEND_HDR_S[OL4TYPE], NIX_SEND_HDR_S[IL4TYPE]. Internal: Encoding
371 * matches DPDK TX L4 types. \<pre\> PKT_TX_L4_NO_CKSUM (0ULL \<\< 52)
372 * // Disable L4 cksum of TX pkt. PKT_TX_TCP_CKSUM (1ULL \<\< 52) //
373 * TCP cksum of TX pkt. computed by nic. PKT_TX_SCTP_CKSUM (2ULL \<\<
374 * 52) // SCTP cksum of TX pkt. computed by nic. PKT_TX_UDP_CKSUM
375 * (3ULL \<\< 52) // UDP cksum of TX pkt. computed by nic. \</pre\>
377 #define NIX_SENDL4TYPE_E_NONE (0)
378 #define NIX_SENDL4TYPE_E_SCTP_CKSUM (2)
379 #define NIX_SENDL4TYPE_E_TCP_CKSUM (1)
380 #define NIX_SENDL4TYPE_E_UDP_CKSUM (3)
383 * Enumeration nix_sendldtype_e
385 * NIX Send Load Type Enumeration Enumerates the load transaction types
386 * for reading segment bytes specified by NIX_SEND_SG_S[LD_TYPE] and
387 * NIX_SEND_JUMP_S[LD_TYPE]. Internal: The hardware implementation
388 * treats undefined encodings as LDD load type.
390 #define NIX_SENDLDTYPE_E_LDD (0)
391 #define NIX_SENDLDTYPE_E_LDT (1)
392 #define NIX_SENDLDTYPE_E_LDWB (2)
395 * Enumeration nix_sendmemalg_e
397 * NIX Memory Modify Algorithm Enumeration Enumerates the different
398 * algorithms for modifying memory; see NIX_SEND_MEM_S[ALG]. mbufs_freed
399 * is the number of gather buffers freed to NPA for the send descriptor.
400 * See NIX_SEND_HDR_S[DF] and NIX_SEND_SG_S[I*].
402 #define NIX_SENDMEMALG_E_ADD (8)
403 #define NIX_SENDMEMALG_E_ADDLEN (0xa)
404 #define NIX_SENDMEMALG_E_ADDMBUF (0xc)
405 #define NIX_SENDMEMALG_E_SET (0)
406 #define NIX_SENDMEMALG_E_SETRSLT (2)
407 #define NIX_SENDMEMALG_E_SETTSTMP (1)
408 #define NIX_SENDMEMALG_E_SUB (9)
409 #define NIX_SENDMEMALG_E_SUBLEN (0xb)
410 #define NIX_SENDMEMALG_E_SUBMBUF (0xd)
413 * Enumeration nix_sendmemdsz_e
415 * NIX Memory Data Size Enumeration Enumerates the datum size for
416 * modifying memory; see NIX_SEND_MEM_S[DSZ].
418 #define NIX_SENDMEMDSZ_E_B16 (2)
419 #define NIX_SENDMEMDSZ_E_B32 (1)
420 #define NIX_SENDMEMDSZ_E_B64 (0)
421 #define NIX_SENDMEMDSZ_E_B8 (3)
424 * Enumeration nix_sqint_e
426 * NIX Send Queue Interrupt Enumeration Enumerates the bit index of
427 * NIX_SQ_CTX_S[SQ_INT,SQ_INT_ENA].
429 #define NIX_SQINT_E_LMT_ERR (0)
430 #define NIX_SQINT_E_MNQ_ERR (1)
431 #define NIX_SQINT_E_SEND_ERR (2)
432 #define NIX_SQINT_E_SQB_ALLOC_FAIL (3)
435 * Enumeration nix_sqoperr_e
437 * NIX SQ Operation Error Enumeration Enumerates
438 * NIX_LF_SQ_OP_ERR_DBG[ERRCODE] values.
440 #define NIX_SQOPERR_E_MAX_SQE_SIZE_ERR (4)
441 #define NIX_SQOPERR_E_SQB_FAULT (7)
442 #define NIX_SQOPERR_E_SQB_NULL (6)
443 #define NIX_SQOPERR_E_SQE_OFLOW (5)
444 #define NIX_SQOPERR_E_SQE_SIZEM1_ZERO (8)
445 #define NIX_SQOPERR_E_SQ_CTX_FAULT (1)
446 #define NIX_SQOPERR_E_SQ_CTX_POISON (2)
447 #define NIX_SQOPERR_E_SQ_DISABLED (3)
448 #define NIX_SQOPERR_E_SQ_OOR (0)
451 * Enumeration nix_stat_lf_rx_e
453 * NIX Local Function Receive Statistics Enumeration Enumerates the last
454 * index of NIX_AF_LF()_RX_STAT() and NIX_LF_RX_STAT().
456 #define NIX_STAT_LF_RX_E_RX_BCAST (2)
457 #define NIX_STAT_LF_RX_E_RX_DROP (4)
458 #define NIX_STAT_LF_RX_E_RX_DROP_OCTS (5)
459 #define NIX_STAT_LF_RX_E_RX_DRP_BCAST (8)
460 #define NIX_STAT_LF_RX_E_RX_DRP_L3BCAST (0xa)
461 #define NIX_STAT_LF_RX_E_RX_DRP_L3MCAST (0xb)
462 #define NIX_STAT_LF_RX_E_RX_DRP_MCAST (9)
463 #define NIX_STAT_LF_RX_E_RX_ERR (7)
464 #define NIX_STAT_LF_RX_E_RX_FCS (6)
465 #define NIX_STAT_LF_RX_E_RX_MCAST (3)
466 #define NIX_STAT_LF_RX_E_RX_OCTS (0)
467 #define NIX_STAT_LF_RX_E_RX_UCAST (1)
470 * Enumeration nix_stat_lf_tx_e
472 * NIX Local Function Transmit Statistics Enumeration Enumerates the
473 * index of NIX_AF_LF()_TX_STAT() and NIX_LF_TX_STAT(). These statistics
474 * do not account for packet replication due to NIX_TX_ACTION_S[OP] =
475 * NIX_TX_ACTIONOP_E::MCAST.
477 #define NIX_STAT_LF_TX_E_TX_BCAST (1)
478 #define NIX_STAT_LF_TX_E_TX_DROP (3)
479 #define NIX_STAT_LF_TX_E_TX_MCAST (2)
480 #define NIX_STAT_LF_TX_E_TX_OCTS (4)
481 #define NIX_STAT_LF_TX_E_TX_UCAST (0)
484 * Enumeration nix_stype_e
486 * NIX SQB Caching Type Enumeration Enumerates the values of
487 * NIX_SQ_CTX_S[SQE_STYPE].
489 #define NIX_STYPE_E_STF (0)
490 #define NIX_STYPE_E_STP (2)
491 #define NIX_STYPE_E_STT (1)
494 * Enumeration nix_subdc_e
496 * NIX Subdescriptor Operation Enumeration Enumerates send and receive
497 * subdescriptor codes. The codes differentiate subdescriptors within a
498 * NIX send or receive descriptor, excluding NIX_SEND_HDR_S for send and
499 * NIX_CQE_HDR_S/NIX_WQE_HDR_S for receive, which are determined by their
500 * position as the first subdescriptor, and NIX_RX_PARSE_S, which is
501 * determined by its position as the second subdescriptor.
503 #define NIX_SUBDC_E_CRC (2)
504 #define NIX_SUBDC_E_EXT (1)
505 #define NIX_SUBDC_E_IMM (3)
506 #define NIX_SUBDC_E_JUMP (6)
507 #define NIX_SUBDC_E_MEM (5)
508 #define NIX_SUBDC_E_NOP (0)
509 #define NIX_SUBDC_E_SG (4)
510 #define NIX_SUBDC_E_SOD (0xf)
511 #define NIX_SUBDC_E_WORK (7)
514 * Enumeration nix_tx_actionop_e
516 * NIX Transmit Action Opcode Enumeration Enumerates the values of
517 * NIX_TX_ACTION_S[OP].
519 #define NIX_TX_ACTIONOP_E_DROP (0)
520 #define NIX_TX_ACTIONOP_E_DROP_VIOL (5)
521 #define NIX_TX_ACTIONOP_E_MCAST (3)
522 #define NIX_TX_ACTIONOP_E_UCAST_CHAN (2)
523 #define NIX_TX_ACTIONOP_E_UCAST_DEFAULT (1)
526 * Enumeration nix_tx_vtagop_e
528 * NIX Transmit Vtag Opcode Enumeration Enumerates the values of
529 * NIX_TX_VTAG_ACTION_S[VTAG0_OP,VTAG1_OP].
531 #define NIX_TX_VTAGOP_E_INSERT (1)
532 #define NIX_TX_VTAGOP_E_NOP (0)
533 #define NIX_TX_VTAGOP_E_REPLACE (2)
536 * Enumeration nix_txlayer_e
538 * NIX Transmit Layer Enumeration Enumerates the values of
539 * NIX_AF_LSO_FORMAT()_FIELD()[LAYER].
541 #define NIX_TXLAYER_E_IL3 (2)
542 #define NIX_TXLAYER_E_IL4 (3)
543 #define NIX_TXLAYER_E_OL3 (0)
544 #define NIX_TXLAYER_E_OL4 (1)
547 * Enumeration nix_vtagsize_e
549 * NIX Vtag Size Enumeration Enumerates the values of
550 * NIX_AF_TX_VTAG_DEF()_CTL[SIZE] and NIX_AF_LF()_RX_VTAG_TYPE()[SIZE].
552 #define NIX_VTAGSIZE_E_T4 (0)
553 #define NIX_VTAGSIZE_E_T8 (1)
556 * Enumeration nix_xqe_type_e
558 * NIX WQE/CQE Type Enumeration Enumerates the values of
559 * NIX_WQE_HDR_S[WQE_TYPE], NIX_CQE_HDR_S[CQE_TYPE].
561 #define NIX_XQE_TYPE_E_INVALID (0)
562 #define NIX_XQE_TYPE_E_RX (1)
563 #define NIX_XQE_TYPE_E_RX_IPSECD (4)
564 #define NIX_XQE_TYPE_E_RX_IPSECH (3)
565 #define NIX_XQE_TYPE_E_RX_IPSECS (2)
566 #define NIX_XQE_TYPE_E_SEND (8)
569 * Enumeration nix_xqesz_e
571 * NIX WQE/CQE Size Enumeration Enumerates the values of
572 * NIX_AF_LF()_CFG[XQE_SIZE].
574 #define NIX_XQESZ_E_W16 (1)
575 #define NIX_XQESZ_E_W64 (0)
578 * Structure nix_aq_inst_s
580 * NIX Admin Queue Instruction Structure This structure specifies the AQ
581 * instruction. Instructions and associated software structures are
582 * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set.
583 * Hardware reads of NIX_AQ_INST_S do not allocate into LLC. Hardware
584 * reads and writes of the context structure selected by [CTYPE], [LF]
585 * and [CINDEX] use the NDC and LLC caching style configured for that
586 * context. For example: * When [CTYPE] = NIX_AQ_CTYPE_E::RQ: use
587 * NIX_AF_LF()_RSS_CFG[CACHING] and NIX_AF_LF()_RSS_CFG[WAY_MASK]. * When
588 * [CTYPE] = NIX_AQ_CTYPE_E::MCE: use NIX_AF_RX_MCAST_CFG[CACHING] and
589 * NIX_AF_RX_MCAST_CFG[WAY_MASK].
591 union nix_aq_inst_s {
593 struct nix_aq_inst_s_s {
597 u64 reserved_15_23 : 9;
599 u64 reserved_44_62 : 19;
603 /* struct nix_aq_inst_s_s cn; */
607 * Structure nix_aq_res_s
609 * NIX Admin Queue Result Structure NIX writes this structure after it
610 * completes the NIX_AQ_INST_S instruction. The result structure is
611 * exactly 16 bytes, and each instruction completion produces exactly one
612 * result structure. Results and associated software structures are
613 * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set.
614 * When [OP] = NIX_AQ_INSTOP_E::INIT, WRITE or READ, this structure is
615 * immediately followed by context read or write data. See
616 * NIX_AQ_INSTOP_E. Hardware writes of NIX_AQ_RES_S and context data
617 * always allocate into LLC. Hardware reads of context data do not
622 struct nix_aq_res_s_s {
627 u64 reserved_17_63 : 47;
628 u64 reserved_64_127 : 64;
630 /* struct nix_aq_res_s_s cn; */
634 * Structure nix_cint_hw_s
636 * NIX Completion Interrupt Context Hardware Structure This structure
637 * contains context state maintained by hardware for each completion
638 * interrupt (CINT) in NDC/LLC/DRAM. Software accesses this structure
639 * with the NIX_LF_CINT()* registers. Hardware maintains a table of
640 * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures per LF
641 * starting at AF IOVA NIX_AF_LF()_CINTS_BASE. Always stored in byte
642 * invariant little-endian format (LE8).
644 union nix_cint_hw_s {
646 struct nix_cint_hw_s_s {
652 u64 reserved_58_63 : 6;
653 u64 ecount_wait : 32;
654 u64 qcount_wait : 16;
656 u64 reserved_120_127 : 8;
658 /* struct nix_cint_hw_s_s cn; */
662 * Structure nix_cq_ctx_s
664 * NIX Completion Queue Context Structure This structure contains context
665 * state maintained by hardware for each CQ in NDC/LLC/DRAM. Software
666 * uses the same structure format to read and write an CQ context with
667 * the NIX admin queue.
671 struct nix_cq_ctx_s_s {
673 u64 reserved_64_67 : 4;
675 u64 reserved_69_71 : 3;
677 u64 reserved_81_83 : 3;
686 u64 update_time : 16;
691 u64 reserved_210_211 : 2;
694 u64 reserved_233_235 : 3;
697 u64 cq_err_int_ena : 8;
699 /* struct nix_cq_ctx_s_s cn; */
703 * Structure nix_cqe_hdr_s
705 * NIX Completion Queue Entry Header Structure This 64-bit structure
706 * defines the first word of every CQE. It is immediately followed by
707 * NIX_RX_PARSE_S in a receive CQE, and by NIX_SEND_COMP_S in a send
708 * completion CQE. Stored in memory as little-endian unless
709 * NIX_AF_LF()_CFG[BE] is set.
711 union nix_cqe_hdr_s {
713 struct nix_cqe_hdr_s_s {
716 u64 reserved_52_57 : 6;
720 /* struct nix_cqe_hdr_s_s cn; */
724 * Structure nix_inst_hdr_s
726 * NIX Instruction Header Structure This structure defines the
727 * instruction header that precedes the packet header supplied to NPC for
728 * packets to be transmitted by NIX.
730 union nix_inst_hdr_s {
732 struct nix_inst_hdr_s_s {
735 u64 reserved_36_63 : 28;
737 /* struct nix_inst_hdr_s_s cn; */
741 * Structure nix_iova_s
743 * NIX I/O Virtual Address Structure
747 struct nix_iova_s_s {
750 /* struct nix_iova_s_s cn; */
754 * Structure nix_ipsec_dyno_s
756 * INTERNAL: NIX IPSEC Dynamic Ordering Counter Structure Internal: Not
757 * used; no IPSEC fast-path.
759 union nix_ipsec_dyno_s {
761 struct nix_ipsec_dyno_s_s {
764 /* struct nix_ipsec_dyno_s_s cn; */
768 * Structure nix_mem_result_s
770 * NIX Memory Value Structure When
771 * NIX_SEND_MEM_S[ALG]=NIX_SENDMEMALG_E::SETRSLT, the value written to
772 * memory is formed with this structure.
774 union nix_mem_result_s {
776 struct nix_mem_result_s_s {
779 u64 reserved_3_63 : 61;
781 /* struct nix_mem_result_s_s cn; */
785 * Structure nix_op_q_wdata_s
787 * NIX Statistics Operation Write Data Structure This structure specifies
788 * the write data format of an atomic 64-bit load-and-add of some
789 * NIX_LF_RQ_OP_*, NIX_LF_SQ_OP* and NIX_LF_CQ_OP* registers.
791 union nix_op_q_wdata_s {
793 struct nix_op_q_wdata_s_s {
794 u64 reserved_0_31 : 32;
796 u64 reserved_52_63 : 12;
798 /* struct nix_op_q_wdata_s_s cn; */
802 * Structure nix_qint_hw_s
804 * NIX Queue Interrupt Context Hardware Structure This structure contains
805 * context state maintained by hardware for each queue interrupt (QINT)
806 * in NDC/LLC/DRAM. Software accesses this structure with the
807 * NIX_LF_QINT()* registers. Hardware maintains a table of
808 * NIX_AF_CONST2[QINTS] contiguous NIX_QINT_HW_S structures per LF
809 * starting at IOVA NIX_AF_LF()_QINTS_BASE. Always stored in byte
810 * invariant little-endian format (LE8).
812 union nix_qint_hw_s {
814 struct nix_qint_hw_s_s {
816 u32 reserved_22_30 : 9;
819 /* struct nix_qint_hw_s_s cn; */
823 * Structure nix_rq_ctx_hw_s
825 * NIX Receive Queue Context Structure This structure contains context
826 * state maintained by hardware for each RQ in NDC/LLC/DRAM. Software
827 * uses the equivalent NIX_RQ_CTX_S structure format to read and write an
828 * RQ context with the NIX admin queue. Always stored in byte invariant
829 * little-endian format (LE8).
831 union nix_rq_ctx_hw_s {
833 struct nix_rq_ctx_hw_s_s {
847 u64 xqe_drop_ena : 1;
848 u64 spb_drop_ena : 1;
849 u64 lpb_drop_ena : 1;
851 u64 reserved_124_127 : 4;
852 u64 reserved_128_139 : 12;
854 u64 reserved_146_150 : 5;
858 u64 reserved_171 : 1;
860 u64 xqe_imm_size : 6;
861 u64 reserved_184_189 : 6;
862 u64 xqe_imm_copy : 1;
863 u64 xqe_hdr_split : 1;
866 u64 wqe_pool_drop : 8;
867 u64 wqe_pool_pass : 8;
868 u64 spb_aura_drop : 8;
869 u64 spb_aura_pass : 8;
870 u64 spb_pool_drop : 8;
871 u64 spb_pool_pass : 8;
872 u64 lpb_aura_drop : 8;
873 u64 lpb_aura_pass : 8;
874 u64 lpb_pool_drop : 8;
875 u64 lpb_pool_pass : 8;
876 u64 reserved_288_319 : 32;
881 u64 reserved_366_383 : 18;
883 u64 reserved_432_447 : 16;
885 u64 reserved_496_511 : 16;
887 u64 reserved_560_575 : 16;
889 u64 reserved_624_639 : 16;
891 u64 reserved_688_702 : 15;
893 u64 reserved_704_739 : 36;
897 u64 reserved_763_767 : 5;
898 u64 reserved_768_831 : 64;
899 u64 reserved_832_895 : 64;
900 u64 reserved_896_959 : 64;
901 u64 reserved_960_1023 : 64;
903 /* struct nix_rq_ctx_hw_s_s cn; */
907 * Structure nix_rq_ctx_s
909 * NIX Receive Queue Context Structure This structure specifies the
910 * format used by software to read and write an RQ context with the NIX
915 struct nix_rq_ctx_s_s {
929 u64 xqe_drop_ena : 1;
930 u64 spb_drop_ena : 1;
931 u64 lpb_drop_ena : 1;
932 u64 reserved_122_127 : 6;
933 u64 reserved_128_139 : 12;
936 u64 reserved_148_150 : 3;
940 u64 reserved_171 : 1;
942 u64 xqe_imm_size : 6;
943 u64 reserved_184_189 : 6;
944 u64 xqe_imm_copy : 1;
945 u64 xqe_hdr_split : 1;
948 u64 wqe_pool_drop : 8;
949 u64 wqe_pool_pass : 8;
950 u64 spb_aura_drop : 8;
951 u64 spb_aura_pass : 8;
952 u64 spb_pool_drop : 8;
953 u64 spb_pool_pass : 8;
954 u64 lpb_aura_drop : 8;
955 u64 lpb_aura_pass : 8;
956 u64 lpb_pool_drop : 8;
957 u64 lpb_pool_pass : 8;
958 u64 reserved_288_291 : 4;
962 u64 reserved_315_319 : 5;
967 u64 reserved_366_383 : 18;
969 u64 reserved_432_447 : 16;
971 u64 reserved_496_511 : 16;
973 u64 reserved_560_575 : 16;
975 u64 reserved_624_639 : 16;
977 u64 reserved_688_703 : 16;
978 u64 reserved_704_767 : 64;
979 u64 reserved_768_831 : 64;
980 u64 reserved_832_895 : 64;
981 u64 reserved_896_959 : 64;
982 u64 reserved_960_1023 : 64;
984 /* struct nix_rq_ctx_s_s cn; */
988 * Structure nix_rsse_s
990 * NIX Receive Side Scaling Entry Structure This structure specifies the
991 * format of each hardware entry in the NIX RSS tables in NDC/LLC/DRAM.
992 * See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP(). Software uses the
993 * same structure format to read and write an RSS table entry with the
998 struct nix_rsse_s_s {
1000 u32 reserved_20_31 : 12;
1002 /* struct nix_rsse_s_s cn; */
1006 * Structure nix_rx_action_s
1008 * NIX Receive Action Structure This structure defines the format of
1009 * NPC_RESULT_S[ACTION] for a receive packet.
1011 union nix_rx_action_s {
1013 struct nix_rx_action_s_s {
1018 u64 flow_key_alg : 5;
1019 u64 reserved_61_63 : 3;
1021 /* struct nix_rx_action_s_s cn; */
1025 * Structure nix_rx_imm_s
1027 * NIX Receive Immediate Subdescriptor Structure The receive immediate
1028 * subdescriptor indicates that bytes immediately following this
1029 * NIX_RX_IMM_S (after skipping [APAD] bytes) were saved from the
1030 * received packet. The next subdescriptor following this NIX_RX_IMM_S
1031 * (when one exists) will follow the immediate bytes, after rounding up
1032 * the address to a multiple of 16 bytes.
1034 union nix_rx_imm_s {
1036 struct nix_rx_imm_s_s {
1039 u64 reserved_19_59 : 41;
1042 /* struct nix_rx_imm_s_s cn; */
1046 * Structure nix_rx_mce_s
1048 * NIX Receive Multicast/Mirror Entry Structure This structure specifies
1049 * the format of entries in the NIX receive multicast/mirror table
1050 * maintained by hardware in NDC/LLC/DRAM. See NIX_AF_RX_MCAST_BASE and
1051 * NIX_AF_RX_MCAST_CFG. Note the table may contain both multicast and
1052 * mirror replication lists. Software uses the same structure format to
1053 * read and write a multicast/mirror table entry with the NIX admin
1056 union nix_rx_mce_s {
1058 struct nix_rx_mce_s_s {
1063 u64 reserved_24_31 : 8;
1067 /* struct nix_rx_mce_s_s cn; */
1071 * Structure nix_rx_parse_s
1073 * NIX Receive Parse Structure This structure contains the receive packet
1074 * parse result. It immediately follows NIX_CQE_HDR_S in a receive CQE,
1075 * or NIX_WQE_HDR_S in a receive WQE. Stored in memory as little-endian
1076 * unless NIX_AF_LF()_CFG[BE] is set. Header layers are always 2-byte
1077 * aligned, so all header pointers in this structure ([EOH_PTR], [LAPTR]
1078 * through [LHPTR], [VTAG*_PTR]) are even.
1080 union nix_rx_parse_s {
1082 struct nix_rx_parse_s_s {
1084 u64 desc_sizem1 : 5;
1103 u64 vtag0_valid : 1;
1105 u64 vtag1_valid : 1;
1108 u64 reserved_94_95 : 2;
1133 u64 flow_key_alg : 5;
1134 u64 reserved_341_383 : 43;
1135 u64 reserved_384_447 : 64;
1137 /* struct nix_rx_parse_s_s cn; */
1141 * Structure nix_rx_sg_s
1143 * NIX Receive Scatter/Gather Subdescriptor Structure The receive
1144 * scatter/gather subdescriptor specifies one to three segments of packet
1145 * data bytes. There may be multiple NIX_RX_SG_Ss in each NIX receive
1146 * descriptor. NIX_RX_SG_S is immediately followed by one NIX_IOVA_S
1147 * word when [SEGS] = 1, three NIX_IOVA_S words when [SEGS] \>= 2. Each
1148 * NIX_IOVA_S word specifies the LF IOVA of first packet data byte in the
1149 * corresponding segment; first NIX_IOVA_S word for segment 1, second
1150 * word for segment 2, third word for segment 3. Note the third word is
1151 * present when [SEGS] \>= 2 but only valid when [SEGS] = 3.
1155 struct nix_rx_sg_s_s {
1160 u64 reserved_50_59 : 10;
1163 /* struct nix_rx_sg_s_s cn; */
1167 * Structure nix_rx_vtag_action_s
1169 * NIX Receive Vtag Action Structure This structure defines the format of
1170 * NPC_RESULT_S[VTAG_ACTION] for a receive packet. It specifies up to two
1171 * Vtags (e.g. C-VLAN/S-VLAN tags, 802.1BR E-TAG) for optional capture
1174 union nix_rx_vtag_action_s {
1176 struct nix_rx_vtag_action_s_s {
1177 u64 vtag0_relptr : 8;
1179 u64 reserved_11 : 1;
1181 u64 vtag0_valid : 1;
1182 u64 reserved_16_31 : 16;
1183 u64 vtag1_relptr : 8;
1185 u64 reserved_43 : 1;
1187 u64 vtag1_valid : 1;
1188 u64 reserved_48_63 : 16;
1190 /* struct nix_rx_vtag_action_s_s cn; */
1194 * Structure nix_send_comp_s
1196 * NIX Send Completion Structure This structure immediately follows
1197 * NIX_CQE_HDR_S in a send completion CQE.
1199 union nix_send_comp_s {
1201 struct nix_send_comp_s_s {
1204 u64 reserved_24_63 : 40;
1206 /* struct nix_send_comp_s_s cn; */
1210 * Structure nix_send_crc_s
1212 * NIX Send CRC Subdescriptor Structure The send CRC subdescriptor
1213 * specifies a CRC calculation be performed during transmission. Ignored
1214 * when present in a send descriptor with NIX_SEND_EXT_S[LSO] set. There
1215 * may be up to two NIX_SEND_CRC_Ss per send descriptor. NIX_SEND_CRC_S
1216 * constraints: * When present, NIX_SEND_CRC_S subdescriptors must
1217 * precede all NIX_SEND_SG_S, NIX_SEND_IMM_S and NIX_SEND_MEM_S
1218 * subdescriptors in the send descriptor. * NIX_SEND_CRC_S subdescriptors
1219 * must follow the same order as their checksum and insert regions in the
1220 * packet, i.e. the checksum and insert regions of a NIX_SEND_CRC_S must
1221 * come after the checksum and insert regions of a preceding
1222 * NIX_SEND_CRC_S. There must be no overlap between any NIX_SEND_CRC_S
1223 * checksum and insert regions. * If either
1224 * NIX_SEND_HDR_S[OL4TYPE,IL4TYPE] = NIX_SENDL4TYPE_E::SCTP_CKSUM, the
1225 * SCTP checksum region and NIX_SEND_CRC_S insert region must not
1226 * overlap, and likewise the NIX_SEND_CRC_S checksum region and SCTP
1227 * insert region must not overlap. * If either
1228 * NIX_SEND_HDR_S[OL3TYPE,IL3TYPE] = NIX_SENDL3TYPE_E::IP4_CKSUM, the
1229 * IPv4 header checksum region and NIX_SEND_CRC_S insert region must not
1230 * overlap. * Any checksums inserted by
1231 * NIX_SEND_HDR_S[OL3TYPE,OL4TYPE,IL3TYPE,IL4TYPE] must be outside of the
1232 * NIX_SEND_CRC_S checksum and insert regions. Hardware adjusts [START],
1233 * [SIZE] and [INSERT] as needed to account for any VLAN inserted by
1234 * NIX_SEND_EXT_S[VLAN*] or Vtag inserted by NIX_TX_VTAG_ACTION_S.
1236 union nix_send_crc_s {
1238 struct nix_send_crc_s_s {
1242 u64 reserved_48_57 : 10;
1246 u64 reserved_96_127 : 32;
1248 /* struct nix_send_crc_s_s cn; */
1252 * Structure nix_send_ext_s
1254 * NIX Send Extended Header Subdescriptor Structure The send extended
1255 * header specifies LSO, VLAN insertion, timestamp and/or scheduling
1256 * services on the packet. If present, it must immediately follow
1257 * NIX_SEND_HDR_S. All fields are assumed to be zero when this
1258 * subdescriptor is not present.
1260 union nix_send_ext_s {
1262 struct nix_send_ext_s_s {
1268 u64 reserved_29_31 : 3;
1276 u64 vlan0_ins_ptr : 8;
1277 u64 vlan0_ins_tci : 16;
1278 u64 vlan1_ins_ptr : 8;
1279 u64 vlan1_ins_tci : 16;
1280 u64 vlan0_ins_ena : 1;
1281 u64 vlan1_ins_ena : 1;
1282 u64 reserved_114_127 : 14;
1284 /* struct nix_send_ext_s_s cn; */
1288 * Structure nix_send_hdr_s
1290 * NIX Send Header Subdescriptor Structure The send header is the first
1291 * subdescriptor of every send descriptor.
1293 union nix_send_hdr_s {
1295 struct nix_send_hdr_s_s {
1297 u64 reserved_18 : 1;
1313 /* struct nix_send_hdr_s_s cn; */
1317 * Structure nix_send_imm_s
1319 * NIX Send Immediate Subdescriptor Structure The send immediate
1320 * subdescriptor requests that bytes immediately following this
1321 * NIX_SEND_IMM_S (after skipping [APAD] bytes) are to be included in the
1322 * packet data. The next subdescriptor following this NIX_SEND_IMM_S
1323 * (when one exists) will follow the immediate bytes, after rounding up
1324 * the address to a multiple of 16 bytes. There may be multiple
1325 * NIX_SEND_IMM_S in one NIX send descriptor. A NIX_SEND_IMM_S is ignored
1326 * in a NIX send descriptor if the sum of all prior
1327 * NIX_SEND_SG_S[SEG*_SIZE]s and NIX_SEND_IMM_S[SIZE]s meets or exceeds
1328 * NIX_SEND_HDR_S[TOTAL]. When NIX_SEND_EXT_S[LSO] is set in the
1329 * descriptor, all NIX_SEND_IMM_S bytes must be included in the first
1330 * NIX_SEND_EXT_S[LSO_SB] bytes of the source packet.
1332 union nix_send_imm_s {
1334 struct nix_send_imm_s_s {
1337 u64 reserved_19_59 : 41;
1340 /* struct nix_send_imm_s_s cn; */
1344 * Structure nix_send_jump_s
1346 * NIX Send Jump Subdescriptor Structure The send jump subdescriptor
1347 * selects a new address for fetching the remaining subdescriptors of a
1348 * send descriptor. This allows software to create a send descriptor
1349 * longer than SQE size selected by NIX_SQ_CTX_S[MAX_SQE_SIZE]. There
1350 * can be only one NIX_SEND_JUMP_S subdescriptor in a send descriptor. If
1351 * present, it must immediately follow NIX_SEND_HDR_S if NIX_SEND_EXT_S
1352 * is not present, else it must immediately follow NIX_SEND_EXT_S. In
1353 * either case, it must terminate the SQE enqueued by software.
1355 union nix_send_jump_s {
1357 struct nix_send_jump_s_s {
1359 u64 reserved_7_13 : 7;
1362 u64 reserved_36_58 : 23;
1367 /* struct nix_send_jump_s_s cn; */
1371 * Structure nix_send_mem_s
1373 * NIX Send Memory Subdescriptor Structure The send memory subdescriptor
1374 * atomically sets, increments or decrements a memory location.
1375 * NIX_SEND_MEM_S subdescriptors must follow all NIX_SEND_SG_S and
1376 * NIX_SEND_IMM_S subdescriptors in the NIX send descriptor. NIX will not
1377 * initiate the memory update for this subdescriptor until after it has
1378 * completed all LLC/DRAM fetches that service all prior NIX_SEND_SG_S
1379 * subdescriptors. The memory update is executed once, even if the packet
1380 * is replicated due to NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST.
1381 * Performance is best if a memory decrement by one is used rather than
1382 * any other memory set/increment/decrement. (Less internal bus bandwidth
1383 * is used with memory decrements by one.) When NIX_SEND_EXT_S[LSO] is
1384 * set in the descriptor, NIX executes the memory update only while
1385 * processing the last LSO segment, after processing prior segments.
1387 union nix_send_mem_s {
1389 struct nix_send_mem_s_s {
1391 u64 reserved_16_52 : 37;
1398 /* struct nix_send_mem_s_s cn; */
1402 * Structure nix_send_sg_s
1404 * NIX Send Scatter/Gather Subdescriptor Structure The send
1405 * scatter/gather subdescriptor requests one to three segments of packet
1406 * data bytes to be transmitted. There may be multiple NIX_SEND_SG_Ss in
1407 * each NIX send descriptor. NIX_SEND_SG_S is immediately followed by
1408 * one NIX_IOVA_S word when [SEGS] = 1, three NIX_IOVA_S words when
1409 * [SEGS] \>= 2. Each NIX_IOVA_S word specifies the LF IOVA of first
1410 * packet data byte in the corresponding segment; first NIX_IOVA_S word
1411 * for segment 1, second word for segment 2, third word for segment 3.
1412 * Note the third word is present when [SEGS] \>= 2 but only valid when
1413 * [SEGS] = 3. If the sum of all prior NIX_SEND_SG_S[SEG*_SIZE]s and
1414 * NIX_SEND_IMM_S[SIZE]s meets or exceeds NIX_SEND_HDR_S[TOTAL], this
1415 * subdescriptor will not contribute any packet data but may free buffers
1416 * to NPA (see [I1]).
1418 union nix_send_sg_s {
1420 struct nix_send_sg_s_s {
1425 u64 reserved_50_54 : 5;
1432 /* struct nix_send_sg_s_s cn; */
1436 * Structure nix_send_work_s
1438 * NIX Send Work Subdescriptor Structure This subdescriptor adds work to
1439 * the SSO. At most one NIX_SEND_WORK_S subdescriptor can exist in the
1440 * NIX send descriptor. If a NIX_SEND_WORK_S exists in the descriptor, it
1441 * must be the last subdescriptor. NIX will not initiate the work add for
1442 * this subdescriptor until after (1) it has completed all LLC/DRAM
1443 * fetches that service all prior NIX_SEND_SG_S subdescriptors, (2) it
1444 * has fetched all subdescriptors in the descriptor, and (3) all
1445 * NIX_SEND_MEM_S[WMEM]=1 LLC/DRAM updates have completed. Provided the
1446 * path of descriptors from the SQ through NIX to an output FIFO is
1447 * unmodified between the descriptors (as should normally be the case,
1448 * but it is possible for software to change the path), NIX also (1) will
1449 * submit the SSO add works from all descriptors in the SQ in order, and
1450 * (2) will not submit an SSO work add until after all prior descriptors
1451 * in the SQ have completed their NIX_SEND_SG_S processing, and (3) will
1452 * not submit an SSO work add until after it has fetched all
1453 * subdescriptors from prior descriptors in the SQ. When
1454 * NIX_SEND_EXT_S[LSO] is set in the descriptor, NIX executes the
1455 * NIX_SEND_WORK_S work add only while processing the last LSO segment,
1456 * after processing prior segments. Hardware ignores NIX_SEND_WORK_S
1457 * when NIX_SQ_CTX_S[SSO_ENA] is clear.
1459 union nix_send_work_s {
1461 struct nix_send_work_s_s {
1465 u64 reserved_44_59 : 16;
1469 /* struct nix_send_work_s_s cn; */
1473 * Structure nix_sq_ctx_hw_s
1475 * NIX SQ Context Hardware Structure This structure contains context
1476 * state maintained by hardware for each SQ in NDC/LLC/DRAM. Software
1477 * uses the equivalent NIX_SQ_CTX_S structure format to read and write an
1478 * SQ context with the NIX admin queue. Always stored in byte invariant
1479 * little-endian format (LE8).
1481 union nix_sq_ctx_hw_s {
1483 struct nix_sq_ctx_hw_s_s {
1486 u64 max_sqe_size : 2;
1487 u64 sqe_way_mask : 16;
1500 u64 head_offset : 6;
1501 u64 sqb_dequeue_count : 16;
1502 u64 default_chan : 12;
1506 u64 sqb_enqueue_count : 16;
1507 u64 tail_offset : 6;
1509 u64 smq_rr_quantum : 24;
1516 u64 smq_next_sq : 20;
1517 u64 smq_next_sq_vld : 1;
1518 u64 scm1_rsvd2 : 32;
1520 u64 smenq_offset : 6;
1522 u64 smq_rr_count : 25;
1523 u64 scm_lso_rem : 18;
1524 u64 scm_dq_rsvd0 : 7;
1525 u64 smq_lso_segnum : 8;
1526 u64 vfi_lso_total : 18;
1527 u64 vfi_lso_sizem1 : 3;
1529 u64 vfi_lso_mps : 14;
1530 u64 vfi_lso_vlan0_ins_ena : 1;
1531 u64 vfi_lso_vlan1_ins_ena : 1;
1532 u64 vfi_lso_vld : 1;
1533 u64 smenq_next_sqb_vld : 1;
1534 u64 scm_dq_rsvd1 : 9;
1535 u64 smenq_next_sqb : 64;
1538 u64 drop_octs_lsw : 16;
1539 u64 drop_octs_msw : 32;
1544 /* struct nix_sq_ctx_hw_s_s cn; */
1548 * Structure nix_sq_ctx_s
1550 * NIX Send Queue Context Structure This structure specifies the format
1551 * used by software with the NIX admin queue to read and write a send
1552 * queue's NIX_SQ_CTX_HW_S structure maintained by hardware in
1553 * NDC/LLC/DRAM. The SQ statistics ([OCTS], [PKTS], [DROP_OCTS],
1554 * [DROP_PKTS]) do not account for packet replication due to
1555 * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST.
1557 union nix_sq_ctx_s {
1559 struct nix_sq_ctx_s_s {
1565 u64 sqe_way_mask : 16;
1570 u64 smq_rr_quantum : 24;
1571 u64 default_chan : 12;
1573 u64 smq_rr_count : 25;
1578 u64 reserved_191 : 1;
1579 u64 max_sqe_size : 2;
1583 u64 smq_next_sq : 20;
1584 u64 smq_lso_segnum : 8;
1585 u64 tail_offset : 6;
1586 u64 smenq_offset : 6;
1587 u64 head_offset : 6;
1588 u64 smenq_next_sqb_vld : 1;
1590 u64 smq_next_sq_vld : 1;
1591 u64 reserved_253_255 : 3;
1595 u64 smenq_next_sqb : 64;
1597 u64 reserved_576_583 : 8;
1598 u64 vfi_lso_total : 18;
1599 u64 vfi_lso_sizem1 : 3;
1601 u64 vfi_lso_mps : 14;
1602 u64 vfi_lso_vlan0_ins_ena : 1;
1603 u64 vfi_lso_vlan1_ins_ena : 1;
1604 u64 vfi_lso_vld : 1;
1605 u64 reserved_630_639 : 10;
1606 u64 scm_lso_rem : 18;
1607 u64 reserved_658_703 : 46;
1609 u64 reserved_752_767 : 16;
1611 u64 reserved_816_831 : 16;
1612 u64 reserved_832_895 : 64;
1614 u64 reserved_944_959 : 16;
1616 u64 reserved_1008_1023 : 16;
1618 /* struct nix_sq_ctx_s_s cn; */
1622 * Structure nix_tx_action_s
1624 * NIX Transmit Action Structure This structure defines the format of
1625 * NPC_RESULT_S[ACTION] for a transmit packet.
1627 union nix_tx_action_s {
1629 struct nix_tx_action_s_s {
1631 u64 reserved_4_11 : 8;
1634 u64 reserved_48_63 : 16;
1636 /* struct nix_tx_action_s_s cn; */
1640 * Structure nix_tx_vtag_action_s
1642 * NIX Transmit Vtag Action Structure This structure defines the format
1643 * of NPC_RESULT_S[VTAG_ACTION] for a transmit packet. It specifies the
1644 * optional insertion or replacement of up to two Vtags (e.g.
1645 * C-VLAN/S-VLAN tags, 802.1BR E-TAG). If two Vtags are specified: * The
1646 * Vtag 0 byte offset from packet start (see [VTAG0_RELPTR]) must be less
1647 * than or equal to the Vtag 1 byte offset. * Hardware executes the Vtag
1648 * 0 action first, Vtag 1 action second. * If Vtag 0 is inserted,
1649 * hardware adjusts the Vtag 1 byte offset accordingly. Thus, if the two
1650 * offsets are equal in the structure, hardware inserts Vtag 1
1651 * immediately after Vtag 0 in the packet. A Vtag must not be inserted
1652 * or replaced within an outer or inner L3/L4 header, but may be inserted
1653 * or replaced within an outer L4 payload.
1655 union nix_tx_vtag_action_s {
1657 struct nix_tx_vtag_action_s_s {
1658 u64 vtag0_relptr : 8;
1660 u64 reserved_11 : 1;
1662 u64 reserved_14_15 : 2;
1664 u64 reserved_26_31 : 6;
1665 u64 vtag1_relptr : 8;
1667 u64 reserved_43 : 1;
1669 u64 reserved_46_47 : 2;
1671 u64 reserved_58_63 : 6;
1673 /* struct nix_tx_vtag_action_s_s cn; */
1677 * Structure nix_wqe_hdr_s
1679 * NIX Work Queue Entry Header Structure This 64-bit structure defines
1680 * the first word of every receive WQE generated by NIX. It is
1681 * immediately followed by NIX_RX_PARSE_S. Stored in memory as little-
1682 * endian unless NIX_AF_LF()_CFG[BE] is set.
1684 union nix_wqe_hdr_s {
1686 struct nix_wqe_hdr_s_s {
1694 /* struct nix_wqe_hdr_s_s cn; */
1698 * Register (RVU_PF_BAR0) nix#_af_aq_base
1700 * NIX AF Admin Queue Base Address Register
1702 union nixx_af_aq_base {
1704 struct nixx_af_aq_base_s {
1705 u64 reserved_0_6 : 7;
1707 u64 reserved_53_63 : 11;
1709 /* struct nixx_af_aq_base_s cn; */
1712 static inline u64 NIXX_AF_AQ_BASE(void)
1713 __attribute__ ((pure, always_inline));
1714 static inline u64 NIXX_AF_AQ_BASE(void)
1720 * Register (RVU_PF_BAR0) nix#_af_aq_cfg
1722 * NIX AF Admin Queue Configuration Register
1724 union nixx_af_aq_cfg {
1726 struct nixx_af_aq_cfg_s {
1728 u64 reserved_4_63 : 60;
1730 /* struct nixx_af_aq_cfg_s cn; */
1733 static inline u64 NIXX_AF_AQ_CFG(void)
1734 __attribute__ ((pure, always_inline));
1735 static inline u64 NIXX_AF_AQ_CFG(void)
1741 * Register (RVU_PF_BAR0) nix#_af_aq_done
1743 * NIX AF Admin Queue Done Count Register
1745 union nixx_af_aq_done {
1747 struct nixx_af_aq_done_s {
1749 u64 reserved_20_63 : 44;
1751 /* struct nixx_af_aq_done_s cn; */
1754 static inline u64 NIXX_AF_AQ_DONE(void)
1755 __attribute__ ((pure, always_inline));
1756 static inline u64 NIXX_AF_AQ_DONE(void)
1762 * Register (RVU_PF_BAR0) nix#_af_aq_done_ack
1764 * NIX AF Admin Queue Done Count Ack Register This register is written by
1765 * software to acknowledge interrupts.
1767 union nixx_af_aq_done_ack {
1769 struct nixx_af_aq_done_ack_s {
1771 u64 reserved_20_63 : 44;
1773 /* struct nixx_af_aq_done_ack_s cn; */
1776 static inline u64 NIXX_AF_AQ_DONE_ACK(void)
1777 __attribute__ ((pure, always_inline));
1778 static inline u64 NIXX_AF_AQ_DONE_ACK(void)
1784 * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1c
1786 * NIX AF Admin Queue Done Interrupt Enable Clear Register
1788 union nixx_af_aq_done_ena_w1c {
1790 struct nixx_af_aq_done_ena_w1c_s {
1792 u64 reserved_1_63 : 63;
1794 /* struct nixx_af_aq_done_ena_w1c_s cn; */
1797 static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void)
1798 __attribute__ ((pure, always_inline));
1799 static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void)
1805 * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1s
1807 * NIX AF Admin Queue Done Interrupt Enable Set Register
1809 union nixx_af_aq_done_ena_w1s {
1811 struct nixx_af_aq_done_ena_w1s_s {
1813 u64 reserved_1_63 : 63;
1815 /* struct nixx_af_aq_done_ena_w1s_s cn; */
1818 static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void)
1819 __attribute__ ((pure, always_inline));
1820 static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void)
1826 * Register (RVU_PF_BAR0) nix#_af_aq_done_int
1828 * INTERNAL: NIX AF Admin Queue Done Interrupt Register
1830 union nixx_af_aq_done_int {
1832 struct nixx_af_aq_done_int_s {
1834 u64 reserved_1_63 : 63;
1836 /* struct nixx_af_aq_done_int_s cn; */
1839 static inline u64 NIXX_AF_AQ_DONE_INT(void)
1840 __attribute__ ((pure, always_inline));
1841 static inline u64 NIXX_AF_AQ_DONE_INT(void)
1847 * Register (RVU_PF_BAR0) nix#_af_aq_done_int_w1s
1849 * INTERNAL: NIX AF Admin Queue Done Interrupt Set Register
1851 union nixx_af_aq_done_int_w1s {
1853 struct nixx_af_aq_done_int_w1s_s {
1855 u64 reserved_1_63 : 63;
1857 /* struct nixx_af_aq_done_int_w1s_s cn; */
1860 static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void)
1861 __attribute__ ((pure, always_inline));
1862 static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void)
1868 * Register (RVU_PF_BAR0) nix#_af_aq_done_timer
1870 * NIX AF Admin Queue Done Interrupt Timer Register
1872 union nixx_af_aq_done_timer {
1874 struct nixx_af_aq_done_timer_s {
1876 u64 reserved_16_63 : 48;
1878 /* struct nixx_af_aq_done_timer_s cn; */
1881 static inline u64 NIXX_AF_AQ_DONE_TIMER(void)
1882 __attribute__ ((pure, always_inline));
1883 static inline u64 NIXX_AF_AQ_DONE_TIMER(void)
1889 * Register (RVU_PF_BAR0) nix#_af_aq_done_wait
1891 * NIX AF Admin Queue Done Interrupt Coalescing Wait Register Specifies
1892 * the queue interrupt coalescing settings.
1894 union nixx_af_aq_done_wait {
1896 struct nixx_af_aq_done_wait_s {
1898 u64 reserved_20_31 : 12;
1900 u64 reserved_48_63 : 16;
1902 /* struct nixx_af_aq_done_wait_s cn; */
1905 static inline u64 NIXX_AF_AQ_DONE_WAIT(void)
1906 __attribute__ ((pure, always_inline));
1907 static inline u64 NIXX_AF_AQ_DONE_WAIT(void)
1913 * Register (RVU_PF_BAR0) nix#_af_aq_door
1915 * NIX AF Admin Queue Doorbell Register Software writes to this register
1916 * to enqueue entries to AQ.
1918 union nixx_af_aq_door {
1920 struct nixx_af_aq_door_s {
1922 u64 reserved_16_63 : 48;
1924 /* struct nixx_af_aq_door_s cn; */
1927 static inline u64 NIXX_AF_AQ_DOOR(void)
1928 __attribute__ ((pure, always_inline));
1929 static inline u64 NIXX_AF_AQ_DOOR(void)
1935 * Register (RVU_PF_BAR0) nix#_af_aq_status
1937 * NIX AF Admin Queue Status Register
1939 union nixx_af_aq_status {
1941 struct nixx_af_aq_status_s {
1942 u64 reserved_0_3 : 4;
1944 u64 reserved_24_35 : 12;
1946 u64 reserved_56_61 : 6;
1950 struct nixx_af_aq_status_cn {
1951 u64 reserved_0_3 : 4;
1953 u64 reserved_24_31 : 8;
1954 u64 reserved_32_35 : 4;
1956 u64 reserved_56_61 : 6;
1962 static inline u64 NIXX_AF_AQ_STATUS(void)
1963 __attribute__ ((pure, always_inline));
1964 static inline u64 NIXX_AF_AQ_STATUS(void)
1970 * Register (RVU_PF_BAR0) nix#_af_avg_delay
1972 * NIX AF Queue Average Delay Register
1974 union nixx_af_avg_delay {
1976 struct nixx_af_avg_delay_s {
1978 u64 reserved_19_23 : 5;
1980 u64 reserved_40_63 : 24;
1982 /* struct nixx_af_avg_delay_s cn; */
1985 static inline u64 NIXX_AF_AVG_DELAY(void)
1986 __attribute__ ((pure, always_inline));
1987 static inline u64 NIXX_AF_AVG_DELAY(void)
1993 * Register (RVU_PF_BAR0) nix#_af_bar2_alias#
1995 * NIX Admin Function BAR2 Alias Registers These registers alias to the
1996 * NIX BAR2 registers for the PF and function selected by
1997 * NIX_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for
2000 union nixx_af_bar2_aliasx {
2002 struct nixx_af_bar2_aliasx_s {
2005 /* struct nixx_af_bar2_aliasx_s cn; */
2008 static inline u64 NIXX_AF_BAR2_ALIASX(u64 a)
2009 __attribute__ ((pure, always_inline));
2010 static inline u64 NIXX_AF_BAR2_ALIASX(u64 a)
2012 return 0x9100000 + 8 * a;
2016 * Register (RVU_PF_BAR0) nix#_af_bar2_sel
2018 * NIX Admin Function BAR2 Select Register This register configures BAR2
2019 * accesses from the NIX_AF_BAR2_ALIAS() registers in BAR0. Internal: Not
2020 * implemented. Placeholder for bug33464.
2022 union nixx_af_bar2_sel {
2024 struct nixx_af_bar2_sel_s {
2025 u64 alias_pf_func : 16;
2027 u64 reserved_17_63 : 47;
2029 /* struct nixx_af_bar2_sel_s cn; */
2032 static inline u64 NIXX_AF_BAR2_SEL(void)
2033 __attribute__ ((pure, always_inline));
2034 static inline u64 NIXX_AF_BAR2_SEL(void)
2040 * Register (RVU_PF_BAR0) nix#_af_blk_rst
2042 * NIX AF Block Reset Register
2044 union nixx_af_blk_rst {
2046 struct nixx_af_blk_rst_s {
2048 u64 reserved_1_62 : 62;
2051 /* struct nixx_af_blk_rst_s cn; */
2054 static inline u64 NIXX_AF_BLK_RST(void)
2055 __attribute__ ((pure, always_inline));
2056 static inline u64 NIXX_AF_BLK_RST(void)
2062 * Register (RVU_PF_BAR0) nix#_af_cfg
2064 * NIX AF General Configuration Register
2068 struct nixx_af_cfg_s {
2069 u64 force_cond_clk_en : 1;
2070 u64 force_rx_gbl_clk_en : 1;
2071 u64 force_rx_strm_clk_en : 1;
2072 u64 force_cqm_clk_en : 1;
2073 u64 force_seb_clk_en : 1;
2074 u64 force_sqm_clk_en : 1;
2075 u64 force_pse_clk_en : 1;
2078 u64 calibrate_x2p : 1;
2079 u64 force_intf_clk_en : 1;
2080 u64 reserved_11_63 : 53;
2082 /* struct nixx_af_cfg_s cn; */
2085 static inline u64 NIXX_AF_CFG(void)
2086 __attribute__ ((pure, always_inline));
2087 static inline u64 NIXX_AF_CFG(void)
2093 * Register (RVU_PF_BAR0) nix#_af_cint_delay
2095 * NIX AF Completion Interrupt Delay Register
2097 union nixx_af_cint_delay {
2099 struct nixx_af_cint_delay_s {
2101 u64 reserved_10_15 : 6;
2102 u64 cint_timer : 16;
2103 u64 reserved_32_63 : 32;
2105 /* struct nixx_af_cint_delay_s cn; */
2108 static inline u64 NIXX_AF_CINT_DELAY(void)
2109 __attribute__ ((pure, always_inline));
2110 static inline u64 NIXX_AF_CINT_DELAY(void)
2116 * Register (RVU_PF_BAR0) nix#_af_cint_timer#
2118 * NIX AF Completion Interrupt Timer Registers
2120 union nixx_af_cint_timerx {
2122 struct nixx_af_cint_timerx_s {
2123 u64 expir_time : 16;
2125 u64 reserved_23 : 1;
2128 u64 reserved_33_63 : 31;
2130 /* struct nixx_af_cint_timerx_s cn; */
2133 static inline u64 NIXX_AF_CINT_TIMERX(u64 a)
2134 __attribute__ ((pure, always_inline));
2135 static inline u64 NIXX_AF_CINT_TIMERX(u64 a)
2137 return 0x1a40 + 0x40000 * a;
2141 * Register (RVU_PF_BAR0) nix#_af_const
2143 * NIX AF Constants Register This register contains constants for
2144 * software discovery.
2146 union nixx_af_const {
2148 struct nixx_af_const_s {
2149 u64 cgx_lmac_channels : 8;
2152 u64 lbk_channels : 8;
2155 u64 reserved_32_47 : 16;
2158 u64 reserved_60_63 : 4;
2160 /* struct nixx_af_const_s cn; */
2163 static inline u64 NIXX_AF_CONST(void)
2164 __attribute__ ((pure, always_inline));
2165 static inline u64 NIXX_AF_CONST(void)
2171 * Register (RVU_PF_BAR0) nix#_af_const1
2173 * NIX AF Constants 1 Register This register contains constants for
2174 * software discovery.
2176 union nixx_af_const1 {
2178 struct nixx_af_const1_s {
2179 u64 sdp_channels : 12;
2181 u64 lf_tx_stats : 8;
2182 u64 lf_rx_stats : 8;
2183 u64 lso_format_fields : 8;
2184 u64 lso_formats : 8;
2185 u64 reserved_56_63 : 8;
2187 /* struct nixx_af_const1_s cn; */
2190 static inline u64 NIXX_AF_CONST1(void)
2191 __attribute__ ((pure, always_inline));
2192 static inline u64 NIXX_AF_CONST1(void)
2198 * Register (RVU_PF_BAR0) nix#_af_const2
2200 * NIX AF Constants 2 Register This register contains constants for
2201 * software discovery.
2203 union nixx_af_const2 {
2205 struct nixx_af_const2_s {
2209 u64 reserved_36_63 : 28;
2211 /* struct nixx_af_const2_s cn; */
2214 static inline u64 NIXX_AF_CONST2(void)
2215 __attribute__ ((pure, always_inline));
2216 static inline u64 NIXX_AF_CONST2(void)
2222 * Register (RVU_PF_BAR0) nix#_af_const3
2224 * NIX AF Constants 2 Register This register contains constants for
2225 * software discovery.
2227 union nixx_af_const3 {
2229 struct nixx_af_const3_s {
2230 u64 sq_ctx_log2bytes : 4;
2231 u64 rq_ctx_log2bytes : 4;
2232 u64 cq_ctx_log2bytes : 4;
2233 u64 rsse_log2bytes : 4;
2234 u64 mce_log2bytes : 4;
2235 u64 qint_log2bytes : 4;
2236 u64 cint_log2bytes : 4;
2237 u64 dyno_log2bytes : 4;
2238 u64 reserved_32_63 : 32;
2240 /* struct nixx_af_const3_s cn; */
2243 static inline u64 NIXX_AF_CONST3(void)
2244 __attribute__ ((pure, always_inline));
2245 static inline u64 NIXX_AF_CONST3(void)
2251 * Register (RVU_PF_BAR0) nix#_af_cq_const
2253 * NIX AF CQ Constants Register This register contains constants for
2254 * software discovery.
2256 union nixx_af_cq_const {
2258 struct nixx_af_cq_const_s {
2259 u64 queues_per_lf : 24;
2260 u64 reserved_24_63 : 40;
2262 /* struct nixx_af_cq_const_s cn; */
2265 static inline u64 NIXX_AF_CQ_CONST(void)
2266 __attribute__ ((pure, always_inline));
2267 static inline u64 NIXX_AF_CQ_CONST(void)
2273 * Register (RVU_PF_BAR0) nix#_af_cqm_bp_test
2275 * INTERNAL: NIX AF CQM Backpressure Test Registers
2277 union nixx_af_cqm_bp_test {
2279 struct nixx_af_cqm_bp_test_s {
2281 u64 reserved_12_15 : 4;
2284 u64 reserved_52_63 : 12;
2286 /* struct nixx_af_cqm_bp_test_s cn; */
2289 static inline u64 NIXX_AF_CQM_BP_TEST(void)
2290 __attribute__ ((pure, always_inline));
2291 static inline u64 NIXX_AF_CQM_BP_TEST(void)
2297 * Register (RVU_PF_BAR0) nix#_af_cqm_eco
2299 * INTERNAL: AF CQM ECO Register
2301 union nixx_af_cqm_eco {
2303 struct nixx_af_cqm_eco_s {
2306 /* struct nixx_af_cqm_eco_s cn; */
2309 static inline u64 NIXX_AF_CQM_ECO(void)
2310 __attribute__ ((pure, always_inline));
2311 static inline u64 NIXX_AF_CQM_ECO(void)
2317 * Register (RVU_PF_BAR0) nix#_af_csi_eco
2319 * INTERNAL: AF CSI ECO Register
2321 union nixx_af_csi_eco {
2323 struct nixx_af_csi_eco_s {
2326 /* struct nixx_af_csi_eco_s cn; */
2329 static inline u64 NIXX_AF_CSI_ECO(void)
2330 __attribute__ ((pure, always_inline));
2331 static inline u64 NIXX_AF_CSI_ECO(void)
2337 * Register (RVU_PF_BAR0) nix#_af_err_int
2339 * NIX Admin Function Error Interrupt Register
2341 union nixx_af_err_int {
2343 struct nixx_af_err_int_s {
2344 u64 rx_mcast_data_fault : 1;
2345 u64 rx_mirror_data_fault : 1;
2346 u64 rx_mcast_wqe_fault : 1;
2347 u64 rx_mirror_wqe_fault : 1;
2348 u64 rx_mce_fault : 1;
2349 u64 rx_mce_list_err : 1;
2350 u64 rx_unmapped_pf_func : 1;
2351 u64 reserved_7_11 : 5;
2352 u64 aq_door_err : 1;
2353 u64 aq_res_fault : 1;
2354 u64 aq_inst_fault : 1;
2355 u64 reserved_15_63 : 49;
2357 /* struct nixx_af_err_int_s cn; */
2360 static inline u64 NIXX_AF_ERR_INT(void)
2361 __attribute__ ((pure, always_inline));
2362 static inline u64 NIXX_AF_ERR_INT(void)
2368 * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1c
2370 * NIX Admin Function Error Interrupt Enable Clear Register This register
2371 * clears interrupt enable bits.
2373 union nixx_af_err_int_ena_w1c {
2375 struct nixx_af_err_int_ena_w1c_s {
2376 u64 rx_mcast_data_fault : 1;
2377 u64 rx_mirror_data_fault : 1;
2378 u64 rx_mcast_wqe_fault : 1;
2379 u64 rx_mirror_wqe_fault : 1;
2380 u64 rx_mce_fault : 1;
2381 u64 rx_mce_list_err : 1;
2382 u64 rx_unmapped_pf_func : 1;
2383 u64 reserved_7_11 : 5;
2384 u64 aq_door_err : 1;
2385 u64 aq_res_fault : 1;
2386 u64 aq_inst_fault : 1;
2387 u64 reserved_15_63 : 49;
2389 /* struct nixx_af_err_int_ena_w1c_s cn; */
2392 static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void)
2393 __attribute__ ((pure, always_inline));
2394 static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void)
2400 * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1s
2402 * NIX Admin Function Error Interrupt Enable Set Register This register
2403 * sets interrupt enable bits.
2405 union nixx_af_err_int_ena_w1s {
2407 struct nixx_af_err_int_ena_w1s_s {
2408 u64 rx_mcast_data_fault : 1;
2409 u64 rx_mirror_data_fault : 1;
2410 u64 rx_mcast_wqe_fault : 1;
2411 u64 rx_mirror_wqe_fault : 1;
2412 u64 rx_mce_fault : 1;
2413 u64 rx_mce_list_err : 1;
2414 u64 rx_unmapped_pf_func : 1;
2415 u64 reserved_7_11 : 5;
2416 u64 aq_door_err : 1;
2417 u64 aq_res_fault : 1;
2418 u64 aq_inst_fault : 1;
2419 u64 reserved_15_63 : 49;
2421 /* struct nixx_af_err_int_ena_w1s_s cn; */
2424 static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void)
2425 __attribute__ ((pure, always_inline));
2426 static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void)
2432 * Register (RVU_PF_BAR0) nix#_af_err_int_w1s
2434 * NIX Admin Function Error Interrupt Set Register This register sets
2437 union nixx_af_err_int_w1s {
2439 struct nixx_af_err_int_w1s_s {
2440 u64 rx_mcast_data_fault : 1;
2441 u64 rx_mirror_data_fault : 1;
2442 u64 rx_mcast_wqe_fault : 1;
2443 u64 rx_mirror_wqe_fault : 1;
2444 u64 rx_mce_fault : 1;
2445 u64 rx_mce_list_err : 1;
2446 u64 rx_unmapped_pf_func : 1;
2447 u64 reserved_7_11 : 5;
2448 u64 aq_door_err : 1;
2449 u64 aq_res_fault : 1;
2450 u64 aq_inst_fault : 1;
2451 u64 reserved_15_63 : 49;
2453 /* struct nixx_af_err_int_w1s_s cn; */
2456 static inline u64 NIXX_AF_ERR_INT_W1S(void)
2457 __attribute__ ((pure, always_inline));
2458 static inline u64 NIXX_AF_ERR_INT_W1S(void)
2464 * Register (RVU_PF_BAR0) nix#_af_expr_tx_fifo_status
2466 * INTERNAL: NIX AF Express Transmit FIFO Status Register Internal:
2467 * 802.3br frame preemption/express path is defeatured. Old definition:
2468 * Status of FIFO which transmits express packets to CGX and LBK.
2470 union nixx_af_expr_tx_fifo_status {
2472 struct nixx_af_expr_tx_fifo_status_s {
2474 u64 reserved_12_63 : 52;
2476 /* struct nixx_af_expr_tx_fifo_status_s cn; */
2479 static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void)
2480 __attribute__ ((pure, always_inline));
2481 static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void)
2487 * Register (RVU_PF_BAR0) nix#_af_gen_int
2489 * NIX AF General Interrupt Register
2491 union nixx_af_gen_int {
2493 struct nixx_af_gen_int_s {
2494 u64 rx_mcast_drop : 1;
2495 u64 rx_mirror_drop : 1;
2498 u64 smq_flush_done : 1;
2499 u64 reserved_5_63 : 59;
2501 /* struct nixx_af_gen_int_s cn; */
2504 static inline u64 NIXX_AF_GEN_INT(void)
2505 __attribute__ ((pure, always_inline));
2506 static inline u64 NIXX_AF_GEN_INT(void)
2512 * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1c
2514 * NIX AF General Interrupt Enable Clear Register This register clears
2515 * interrupt enable bits.
2517 union nixx_af_gen_int_ena_w1c {
2519 struct nixx_af_gen_int_ena_w1c_s {
2520 u64 rx_mcast_drop : 1;
2521 u64 rx_mirror_drop : 1;
2524 u64 smq_flush_done : 1;
2525 u64 reserved_5_63 : 59;
2527 /* struct nixx_af_gen_int_ena_w1c_s cn; */
2530 static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void)
2531 __attribute__ ((pure, always_inline));
2532 static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void)
2538 * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1s
2540 * NIX AF General Interrupt Enable Set Register This register sets
2541 * interrupt enable bits.
2543 union nixx_af_gen_int_ena_w1s {
2545 struct nixx_af_gen_int_ena_w1s_s {
2546 u64 rx_mcast_drop : 1;
2547 u64 rx_mirror_drop : 1;
2550 u64 smq_flush_done : 1;
2551 u64 reserved_5_63 : 59;
2553 /* struct nixx_af_gen_int_ena_w1s_s cn; */
2556 static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void)
2557 __attribute__ ((pure, always_inline));
2558 static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void)
2564 * Register (RVU_PF_BAR0) nix#_af_gen_int_w1s
2566 * NIX AF General Interrupt Set Register This register sets interrupt
2569 union nixx_af_gen_int_w1s {
2571 struct nixx_af_gen_int_w1s_s {
2572 u64 rx_mcast_drop : 1;
2573 u64 rx_mirror_drop : 1;
2576 u64 smq_flush_done : 1;
2577 u64 reserved_5_63 : 59;
2579 /* struct nixx_af_gen_int_w1s_s cn; */
2582 static inline u64 NIXX_AF_GEN_INT_W1S(void)
2583 __attribute__ ((pure, always_inline));
2584 static inline u64 NIXX_AF_GEN_INT_W1S(void)
2590 * Register (RVU_PF_BAR0) nix#_af_lf#_cfg
2592 * NIX AF Local Function Configuration Registers
2594 union nixx_af_lfx_cfg {
2596 struct nixx_af_lfx_cfg_s {
2597 u64 npa_pf_func : 16;
2598 u64 sso_pf_func : 16;
2601 u64 reserved_35_63 : 29;
2603 /* struct nixx_af_lfx_cfg_s cn; */
2606 static inline u64 NIXX_AF_LFX_CFG(u64 a)
2607 __attribute__ ((pure, always_inline));
2608 static inline u64 NIXX_AF_LFX_CFG(u64 a)
2610 return 0x4000 + 0x20000 * a;
2614 * Register (RVU_PF_BAR0) nix#_af_lf#_cints_base
2616 * NIX AF Local Function Completion Interrupts Base Address Registers
2617 * This register specifies the base AF IOVA of LF's completion interrupt
2618 * context table in NDC/LLC/DRAM. The table consists of
2619 * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures. After
2620 * writing to this register, software should read it back to ensure that
2621 * the write has completed before accessing any NIX_LF_CINT()_*
2624 union nixx_af_lfx_cints_base {
2626 struct nixx_af_lfx_cints_base_s {
2627 u64 reserved_0_6 : 7;
2629 u64 reserved_53_63 : 11;
2631 /* struct nixx_af_lfx_cints_base_s cn; */
2634 static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a)
2635 __attribute__ ((pure, always_inline));
2636 static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a)
2638 return 0x4130 + 0x20000 * a;
2642 * Register (RVU_PF_BAR0) nix#_af_lf#_cints_cfg
2644 * NIX AF Local Function Completion Interrupts Configuration Registers
2645 * This register controls access to the LF's completion interrupt context
2646 * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[CINTS]
2647 * contiguous NIX_CINT_HW_S structures. The size of each structure is 1
2648 * \<\< NIX_AF_CONST3[CINT_LOG2BYTES]. After writing to this register,
2649 * software should read it back to ensure that the write has completed
2650 * before accessing any NIX_LF_CINT()_* registers.
2652 union nixx_af_lfx_cints_cfg {
2654 struct nixx_af_lfx_cints_cfg_s {
2655 u64 reserved_0_19 : 20;
2658 u64 reserved_37_63 : 27;
2660 /* struct nixx_af_lfx_cints_cfg_s cn; */
2663 static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a)
2664 __attribute__ ((pure, always_inline));
2665 static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a)
2667 return 0x4120 + 0x20000 * a;
2671 * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_base
2673 * NIX AF Local Function Completion Queues Base Address Register This
2674 * register specifies the base AF IOVA of the LF's CQ context table. The
2675 * table consists of NIX_AF_LF()_CQS_CFG[MAX_QUEUESM1]+1 contiguous
2676 * NIX_CQ_CTX_S structures.
2678 union nixx_af_lfx_cqs_base {
2680 struct nixx_af_lfx_cqs_base_s {
2681 u64 reserved_0_6 : 7;
2683 u64 reserved_53_63 : 11;
2685 /* struct nixx_af_lfx_cqs_base_s cn; */
2688 static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a)
2689 __attribute__ ((pure, always_inline));
2690 static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a)
2692 return 0x4070 + 0x20000 * a;
2696 * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_cfg
2698 * NIX AF Local Function Completion Queues Configuration Register This
2699 * register configures completion queues in the LF.
2701 union nixx_af_lfx_cqs_cfg {
2703 struct nixx_af_lfx_cqs_cfg_s {
2704 u64 max_queuesm1 : 20;
2707 u64 reserved_37_63 : 27;
2709 /* struct nixx_af_lfx_cqs_cfg_s cn; */
2712 static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a)
2713 __attribute__ ((pure, always_inline));
2714 static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a)
2716 return 0x4060 + 0x20000 * a;
2720 * Register (RVU_PF_BAR0) nix#_af_lf#_lock#
2722 * NIX AF Local Function Lockdown Registers Internal: The NIX lockdown
2723 * depth of 32 bytes is shallow compared to 96 bytes for NIC and meant
2724 * for outer MAC and/or VLAN (optionally preceded by a small number of
2725 * skip bytes). NPC's MCAM can be used for deeper protocol-aware
2728 union nixx_af_lfx_lockx {
2730 struct nixx_af_lfx_lockx_s {
2734 /* struct nixx_af_lfx_lockx_s cn; */
2737 static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b)
2738 __attribute__ ((pure, always_inline));
2739 static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b)
2741 return 0x4300 + 0x20000 * a + 8 * b;
2745 * Register (RVU_PF_BAR0) nix#_af_lf#_qints_base
2747 * NIX AF Local Function Queue Interrupts Base Address Registers This
2748 * register specifies the base AF IOVA of LF's queue interrupt context
2749 * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS]
2750 * contiguous NIX_QINT_HW_S structures. After writing to this register,
2751 * software should read it back to ensure that the write has completed
2752 * before accessing any NIX_LF_QINT()_* registers.
2754 union nixx_af_lfx_qints_base {
2756 struct nixx_af_lfx_qints_base_s {
2757 u64 reserved_0_6 : 7;
2759 u64 reserved_53_63 : 11;
2761 /* struct nixx_af_lfx_qints_base_s cn; */
2764 static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a)
2765 __attribute__ ((pure, always_inline));
2766 static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a)
2768 return 0x4110 + 0x20000 * a;
2772 * Register (RVU_PF_BAR0) nix#_af_lf#_qints_cfg
2774 * NIX AF Local Function Queue Interrupts Configuration Registers This
2775 * register controls access to the LF's queue interrupt context table in
2776 * NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS] contiguous
2777 * NIX_QINT_HW_S structures. The size of each structure is 1 \<\<
2778 * NIX_AF_CONST3[QINT_LOG2BYTES]. After writing to this register,
2779 * software should read it back to ensure that the write has completed
2780 * before accessing any NIX_LF_QINT()_* registers.
2782 union nixx_af_lfx_qints_cfg {
2784 struct nixx_af_lfx_qints_cfg_s {
2785 u64 reserved_0_19 : 20;
2788 u64 reserved_37_63 : 27;
2790 /* struct nixx_af_lfx_qints_cfg_s cn; */
2793 static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a)
2794 __attribute__ ((pure, always_inline));
2795 static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a)
2797 return 0x4100 + 0x20000 * a;
2801 * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_base
2803 * NIX AF Local Function Receive Queues Base Address Register This
2804 * register specifies the base AF IOVA of the LF's RQ context table. The
2805 * table consists of NIX_AF_LF()_RQS_CFG[MAX_QUEUESM1]+1 contiguous
2806 * NIX_RQ_CTX_S structures.
2808 union nixx_af_lfx_rqs_base {
2810 struct nixx_af_lfx_rqs_base_s {
2811 u64 reserved_0_6 : 7;
2813 u64 reserved_53_63 : 11;
2815 /* struct nixx_af_lfx_rqs_base_s cn; */
2818 static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a)
2819 __attribute__ ((pure, always_inline));
2820 static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a)
2822 return 0x4050 + 0x20000 * a;
2826 * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_cfg
2828 * NIX AF Local Function Receive Queues Configuration Register This
2829 * register configures receive queues in the LF.
2831 union nixx_af_lfx_rqs_cfg {
2833 struct nixx_af_lfx_rqs_cfg_s {
2834 u64 max_queuesm1 : 20;
2837 u64 reserved_37_63 : 27;
2839 /* struct nixx_af_lfx_rqs_cfg_s cn; */
2842 static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a)
2843 __attribute__ ((pure, always_inline));
2844 static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a)
2846 return 0x4040 + 0x20000 * a;
2850 * Register (RVU_PF_BAR0) nix#_af_lf#_rss_base
2852 * NIX AF Local Function Receive Size Scaling Table Base Address Register
2853 * This register specifies the base AF IOVA of the RSS table per LF. The
2854 * table is present when NIX_AF_LF()_RSS_CFG[ENA] is set and consists of
2855 * 1 \<\< (NIX_AF_LF()_RSS_CFG[SIZE] + 8) contiguous NIX_RSSE_S
2856 * structures, where the size of each structure is 1 \<\<
2857 * NIX_AF_CONST3[RSSE_LOG2BYTES]. See NIX_AF_LF()_RSS_GRP().
2859 union nixx_af_lfx_rss_base {
2861 struct nixx_af_lfx_rss_base_s {
2862 u64 reserved_0_6 : 7;
2864 u64 reserved_53_63 : 11;
2866 /* struct nixx_af_lfx_rss_base_s cn; */
2869 static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a)
2870 __attribute__ ((pure, always_inline));
2871 static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a)
2873 return 0x40d0 + 0x20000 * a;
2877 * Register (RVU_PF_BAR0) nix#_af_lf#_rss_cfg
2879 * NIX AF Local Function Receive Size Scaling Table Configuration
2880 * Register See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP().
2882 union nixx_af_lfx_rss_cfg {
2884 struct nixx_af_lfx_rss_cfg_s {
2887 u64 adder_is_tag_lsb : 1;
2888 u64 reserved_6_19 : 14;
2891 u64 reserved_37_63 : 27;
2893 struct nixx_af_lfx_rss_cfg_cn96xxp1 {
2896 u64 reserved_5_19 : 15;
2899 u64 reserved_37_63 : 27;
2901 /* struct nixx_af_lfx_rss_cfg_s cn96xxp3; */
2902 /* struct nixx_af_lfx_rss_cfg_cn96xxp1 cnf95xx; */
2905 static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a)
2906 __attribute__ ((pure, always_inline));
2907 static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a)
2909 return 0x40c0 + 0x20000 * a;
2913 * Register (RVU_PF_BAR0) nix#_af_lf#_rss_grp#
2915 * NIX AF Local Function Receive Side Scaling Group Registers A receive
2916 * packet targets a LF's RSS group when its NIX_RX_ACTION_S[OP] =
2917 * NIX_RX_ACTIONOP_E::RSS, or its target multicast list has an entry with
2918 * NIX_RX_MCE_S[OP] = NIX_RX_MCOP_E::RSS. The RSS group index (this
2919 * register's last index) is NIX_RX_ACTION_S[INDEX] or
2920 * NIX_RX_MCE_S[INDEX]. The RSS computation is as follows: * The
2921 * packet's flow_tag (see NIX_LF_RX_SECRET()) and RSS group are used to
2922 * select a NIX_RSSE_S entry in the LF's RSS table (see [SIZEM1]). *
2923 * NIX_RSSE_S selects the packet's destination RQ.
2925 union nixx_af_lfx_rss_grpx {
2927 struct nixx_af_lfx_rss_grpx_s {
2929 u64 reserved_11_15 : 5;
2931 u64 reserved_19_63 : 45;
2933 /* struct nixx_af_lfx_rss_grpx_s cn; */
2936 static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b)
2937 __attribute__ ((pure, always_inline));
2938 static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b)
2940 return 0x4600 + 0x20000 * a + 8 * b;
2944 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_cfg
2946 * NIX AF Local Function Receive Configuration Register
2948 union nixx_af_lfx_rx_cfg {
2950 struct nixx_af_lfx_rx_cfg_s {
2951 u64 reserved_0_31 : 32;
2954 u64 ip6_udp_opt : 1;
2962 u64 reserved_42_63 : 22;
2964 struct nixx_af_lfx_rx_cfg_cn96xxp1 {
2965 u64 reserved_0_31 : 32;
2966 u64 reserved_32 : 1;
2968 u64 ip6_udp_opt : 1;
2976 u64 reserved_42_63 : 22;
2978 /* struct nixx_af_lfx_rx_cfg_s cn96xxp3; */
2979 /* struct nixx_af_lfx_rx_cfg_s cnf95xx; */
2982 static inline u64 NIXX_AF_LFX_RX_CFG(u64 a)
2983 __attribute__ ((pure, always_inline));
2984 static inline u64 NIXX_AF_LFX_RX_CFG(u64 a)
2986 return 0x40a0 + 0x20000 * a;
2990 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg0
2992 * INTERNAL: NIX AF LF Receive IPSEC Configuration Registers Internal:
2993 * Not used; no IPSEC fast-path.
2995 union nixx_af_lfx_rx_ipsec_cfg0 {
2997 struct nixx_af_lfx_rx_ipsec_cfg0_s {
2999 u64 reserved_14_15 : 2;
3000 u64 sa_pow2_size : 4;
3005 u64 reserved_48_63 : 16;
3007 /* struct nixx_af_lfx_rx_ipsec_cfg0_s cn; */
3010 static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a)
3011 __attribute__ ((pure, always_inline));
3012 static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a)
3014 return 0x4140 + 0x20000 * a;
3018 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg1
3020 * INTERNAL: NIX AF LF Receive IPSEC Security Association Configuration
3021 * Register Internal: Not used; no IPSEC fast-path.
3023 union nixx_af_lfx_rx_ipsec_cfg1 {
3025 struct nixx_af_lfx_rx_ipsec_cfg1_s {
3026 u64 sa_idx_max : 32;
3028 u64 reserved_37_63 : 27;
3030 /* struct nixx_af_lfx_rx_ipsec_cfg1_s cn; */
3033 static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a)
3034 __attribute__ ((pure, always_inline));
3035 static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a)
3037 return 0x4148 + 0x20000 * a;
3041 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_base
3043 * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address
3044 * Registers Internal: Not used; no IPSEC fast-path.
3046 union nixx_af_lfx_rx_ipsec_dyno_base {
3048 struct nixx_af_lfx_rx_ipsec_dyno_base_s {
3049 u64 reserved_0_6 : 7;
3051 u64 reserved_53_63 : 11;
3053 /* struct nixx_af_lfx_rx_ipsec_dyno_base_s cn; */
3056 static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a)
3057 __attribute__ ((pure, always_inline));
3058 static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a)
3060 return 0x4158 + 0x20000 * a;
3064 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_cfg
3066 * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address
3067 * Registers Internal: Not used; no IPSEC fast-path.
3069 union nixx_af_lfx_rx_ipsec_dyno_cfg {
3071 struct nixx_af_lfx_rx_ipsec_dyno_cfg_s {
3074 u64 reserved_5_19 : 15;
3077 u64 reserved_37_63 : 27;
3079 /* struct nixx_af_lfx_rx_ipsec_dyno_cfg_s cn; */
3082 static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a)
3083 __attribute__ ((pure, always_inline));
3084 static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a)
3086 return 0x4150 + 0x20000 * a;
3090 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_sa_base
3092 * INTERNAL: NIX AF LF Receive IPSEC Security Association Base Address
3093 * Register Internal: Not used; no IPSEC fast-path.
3095 union nixx_af_lfx_rx_ipsec_sa_base {
3097 struct nixx_af_lfx_rx_ipsec_sa_base_s {
3098 u64 reserved_0_6 : 7;
3100 u64 reserved_53_63 : 11;
3102 /* struct nixx_af_lfx_rx_ipsec_sa_base_s cn; */
3105 static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a)
3106 __attribute__ ((pure, always_inline));
3107 static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a)
3109 return 0x4170 + 0x20000 * a;
3113 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_stat#
3115 * NIX AF Local Function Receive Statistics Registers The last dimension
3116 * indicates which statistic, and is enumerated by NIX_STAT_LF_RX_E.
3118 union nixx_af_lfx_rx_statx {
3120 struct nixx_af_lfx_rx_statx_s {
3122 u64 reserved_48_63 : 16;
3124 /* struct nixx_af_lfx_rx_statx_s cn; */
3127 static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b)
3128 __attribute__ ((pure, always_inline));
3129 static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b)
3131 return 0x4500 + 0x20000 * a + 8 * b;
3135 * Register (RVU_PF_BAR0) nix#_af_lf#_rx_vtag_type#
3137 * NIX AF Local Function Receive Vtag Type Registers These registers
3138 * specify optional Vtag (e.g. VLAN, E-TAG) actions for received packets.
3139 * Indexed by NIX_RX_VTAG_ACTION_S[VTAG*_TYPE].
3141 union nixx_af_lfx_rx_vtag_typex {
3143 struct nixx_af_lfx_rx_vtag_typex_s {
3145 u64 reserved_1_3 : 3;
3148 u64 reserved_6_63 : 58;
3150 /* struct nixx_af_lfx_rx_vtag_typex_s cn; */
3153 static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b)
3154 __attribute__ ((pure, always_inline));
3155 static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b)
3157 return 0x4200 + 0x20000 * a + 8 * b;
3161 * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_base
3163 * NIX AF Local Function Send Queues Base Address Register This register
3164 * specifies the base AF IOVA of the LF's SQ context table. The table
3165 * consists of NIX_AF_LF()_SQS_CFG[MAX_QUEUESM1]+1 contiguous
3166 * NIX_SQ_CTX_HW_S structures.
3168 union nixx_af_lfx_sqs_base {
3170 struct nixx_af_lfx_sqs_base_s {
3171 u64 reserved_0_6 : 7;
3173 u64 reserved_53_63 : 11;
3175 /* struct nixx_af_lfx_sqs_base_s cn; */
3178 static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a)
3179 __attribute__ ((pure, always_inline));
3180 static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a)
3182 return 0x4030 + 0x20000 * a;
3186 * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_cfg
3188 * NIX AF Local Function Send Queues Configuration Register This register
3189 * configures send queues in the LF.
3191 union nixx_af_lfx_sqs_cfg {
3193 struct nixx_af_lfx_sqs_cfg_s {
3194 u64 max_queuesm1 : 20;
3197 u64 reserved_37_63 : 27;
3199 /* struct nixx_af_lfx_sqs_cfg_s cn; */
3202 static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a)
3203 __attribute__ ((pure, always_inline));
3204 static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a)
3206 return 0x4020 + 0x20000 * a;
3210 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg
3212 * NIX AF Local Function Transmit Configuration Register
3214 union nixx_af_lfx_tx_cfg {
3216 struct nixx_af_lfx_tx_cfg_s {
3217 u64 vlan0_ins_etype : 16;
3218 u64 vlan1_ins_etype : 16;
3219 u64 send_tstmp_ena : 1;
3220 u64 lock_viol_cqe_ena : 1;
3222 u64 reserved_35_63 : 29;
3224 /* struct nixx_af_lfx_tx_cfg_s cn; */
3227 static inline u64 NIXX_AF_LFX_TX_CFG(u64 a)
3228 __attribute__ ((pure, always_inline));
3229 static inline u64 NIXX_AF_LFX_TX_CFG(u64 a)
3231 return 0x4080 + 0x20000 * a;
3235 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg2
3237 * NIX AF Local Function Transmit Configuration Register
3239 union nixx_af_lfx_tx_cfg2 {
3241 struct nixx_af_lfx_tx_cfg2_s {
3243 u64 reserved_1_63 : 63;
3245 /* struct nixx_af_lfx_tx_cfg2_s cn; */
3248 static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a)
3249 __attribute__ ((pure, always_inline));
3250 static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a)
3252 return 0x4028 + 0x20000 * a;
3256 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_parse_cfg
3258 * NIX AF Local Function Transmit Parse Configuration Register
3260 union nixx_af_lfx_tx_parse_cfg {
3262 struct nixx_af_lfx_tx_parse_cfg_s {
3264 u64 reserved_6_63 : 58;
3266 /* struct nixx_af_lfx_tx_parse_cfg_s cn; */
3269 static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a)
3270 __attribute__ ((pure, always_inline));
3271 static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a)
3273 return 0x4090 + 0x20000 * a;
3277 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_stat#
3279 * NIX AF Local Function Transmit Statistics Registers The last dimension
3280 * indicates which statistic, and is enumerated by NIX_STAT_LF_TX_E.
3282 union nixx_af_lfx_tx_statx {
3284 struct nixx_af_lfx_tx_statx_s {
3286 u64 reserved_48_63 : 16;
3288 /* struct nixx_af_lfx_tx_statx_s cn; */
3291 static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b)
3292 __attribute__ ((pure, always_inline));
3293 static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b)
3295 return 0x4400 + 0x20000 * a + 8 * b;
3299 * Register (RVU_PF_BAR0) nix#_af_lf#_tx_status
3301 * NIX AF LF Transmit Status Register
3303 union nixx_af_lfx_tx_status {
3305 struct nixx_af_lfx_tx_status_s {
3307 u64 reserved_1_63 : 63;
3309 /* struct nixx_af_lfx_tx_status_s cn; */
3312 static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a)
3313 __attribute__ ((pure, always_inline));
3314 static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a)
3316 return 0x4180 + 0x20000 * a;
3320 * Register (RVU_PF_BAR0) nix#_af_lf_rst
3322 * NIX Admin Function LF Reset Register
3324 union nixx_af_lf_rst {
3326 struct nixx_af_lf_rst_s {
3328 u64 reserved_8_11 : 4;
3330 u64 reserved_13_63 : 51;
3332 /* struct nixx_af_lf_rst_s cn; */
3335 static inline u64 NIXX_AF_LF_RST(void)
3336 __attribute__ ((pure, always_inline));
3337 static inline u64 NIXX_AF_LF_RST(void)
3343 * Register (RVU_PF_BAR0) nix#_af_lso_cfg
3345 * NIX AF Large Send Offload Configuration Register
3347 union nixx_af_lso_cfg {
3349 struct nixx_af_lso_cfg_s {
3353 u64 reserved_48_62 : 15;
3356 /* struct nixx_af_lso_cfg_s cn; */
3359 static inline u64 NIXX_AF_LSO_CFG(void)
3360 __attribute__ ((pure, always_inline));
3361 static inline u64 NIXX_AF_LSO_CFG(void)
3367 * Register (RVU_PF_BAR0) nix#_af_lso_format#_field#
3369 * NIX AF Large Send Offload Format Field Registers These registers
3370 * specify LSO packet modification formats. Each format may modify up to
3371 * eight packet fields with the following constraints: * If fewer than
3372 * eight fields are modified, [ALG] must be NIX_LSOALG_E::NOP in the
3373 * unused field registers. * Modified fields must be specified in
3374 * contiguous field registers starting with NIX_AF_LSO_FORMAT()_FIELD(0).
3375 * * Modified fields cannot overlap. * Multiple fields with the same
3376 * [LAYER] value must be specified in ascending [OFFSET] order. * Fields
3377 * in different layers must be specified in ascending [LAYER] order.
3379 union nixx_af_lso_formatx_fieldx {
3381 struct nixx_af_lso_formatx_fieldx_s {
3384 u64 reserved_10_11 : 2;
3386 u64 reserved_14_15 : 2;
3388 u64 reserved_19_63 : 45;
3390 /* struct nixx_af_lso_formatx_fieldx_s cn; */
3393 static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b)
3394 __attribute__ ((pure, always_inline));
3395 static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b)
3397 return 0x1b00 + 0x10000 * a + 8 * b;
3401 * Register (RVU_PF_BAR0) nix#_af_mark_format#_ctl
3403 * NIX AF Packet Marking Format Registers Describes packet marking
3404 * calculations for YELLOW and for NIX_COLORRESULT_E::RED_SEND packets.
3405 * NIX_SEND_EXT_S[MARKFORM] selects the CSR used for the packet
3406 * descriptor. All the packet marking offset calculations assume big-
3407 * endian bits within a byte. For example, if NIX_SEND_EXT_S[MARKPTR] is
3408 * 3 and [OFFSET] is 5 and the packet is YELLOW, the NIX marking hardware
3409 * would do this: _ byte[3]\<2:0\> |= [Y_VAL]\<3:1\> _
3410 * byte[3]\<2:0\> &= ~[Y_MASK]\<3:1\> _ byte[4]\<7\> |= [Y_VAL]\<0\>
3411 * _ byte[4]\<7\> &= ~[Y_MASK]\<0\> where byte[3] is the third byte
3412 * in the packet, and byte[4] the fourth. For another example, if
3413 * NIX_SEND_EXT_S[MARKPTR] is 3 and [OFFSET] is 0 and the packet is
3414 * NIX_COLORRESULT_E::RED_SEND, _ byte[3]\<7:4\> |= [R_VAL]\<3:0\> _
3415 * byte[3]\<7:4\> &= ~[R_MASK]\<3:0\>
3417 union nixx_af_mark_formatx_ctl {
3419 struct nixx_af_mark_formatx_ctl_s {
3425 u64 reserved_19_63 : 45;
3427 /* struct nixx_af_mark_formatx_ctl_s cn; */
3430 static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a)
3431 __attribute__ ((pure, always_inline));
3432 static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a)
3434 return 0x900 + 0x40000 * a;
3438 * Register (RVU_PF_BAR0) nix#_af_mc_mirror_const
3440 * NIX AF Multicast/Mirror Constants Register This register contains
3441 * constants for software discovery.
3443 union nixx_af_mc_mirror_const {
3445 struct nixx_af_mc_mirror_const_s {
3447 u64 reserved_16_63 : 48;
3449 /* struct nixx_af_mc_mirror_const_s cn; */
3452 static inline u64 NIXX_AF_MC_MIRROR_CONST(void)
3453 __attribute__ ((pure, always_inline));
3454 static inline u64 NIXX_AF_MC_MIRROR_CONST(void)
3460 * Register (RVU_PF_BAR0) nix#_af_mdq#_cir
3462 * NIX AF Meta Descriptor Queue Committed Information Rate Registers This
3463 * register has the same bit fields as NIX_AF_TL1()_CIR.
3465 union nixx_af_mdqx_cir {
3467 struct nixx_af_mdqx_cir_s {
3469 u64 rate_mantissa : 8;
3470 u64 rate_exponent : 4;
3471 u64 rate_divider_exponent : 4;
3472 u64 reserved_17_28 : 12;
3473 u64 burst_mantissa : 8;
3474 u64 burst_exponent : 4;
3475 u64 reserved_41_63 : 23;
3477 /* struct nixx_af_mdqx_cir_s cn; */
3480 static inline u64 NIXX_AF_MDQX_CIR(u64 a)
3481 __attribute__ ((pure, always_inline));
3482 static inline u64 NIXX_AF_MDQX_CIR(u64 a)
3484 return 0x1420 + 0x10000 * a;
3488 * Register (RVU_PF_BAR0) nix#_af_mdq#_md_debug
3490 * NIX AF Meta Descriptor Queue Meta Descriptor State Debug Registers
3491 * This register provides access to the meta descriptor at the front of
3492 * the MDQ. An MDQ can hold up to 8 packet meta descriptors (PMD) and one
3493 * flush meta descriptor (FMD).
3495 union nixx_af_mdqx_md_debug {
3497 struct nixx_af_mdqx_md_debug_s {
3499 u64 red_algo_override : 2;
3501 u64 reserved_19 : 1;
3503 u64 reserved_29_31 : 3;
3504 u64 sqm_pkt_id : 13;
3505 u64 reserved_45_60 : 16;
3507 u64 reserved_63 : 1;
3509 /* struct nixx_af_mdqx_md_debug_s cn; */
3512 static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a)
3513 __attribute__ ((pure, always_inline));
3514 static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a)
3516 return 0x14c0 + 0x10000 * a;
3520 * Register (RVU_PF_BAR0) nix#_af_mdq#_parent
3522 * NIX AF Meta Descriptor Queue Topology Registers
3524 union nixx_af_mdqx_parent {
3526 struct nixx_af_mdqx_parent_s {
3527 u64 reserved_0_15 : 16;
3529 u64 reserved_25_63 : 39;
3531 /* struct nixx_af_mdqx_parent_s cn; */
3534 static inline u64 NIXX_AF_MDQX_PARENT(u64 a)
3535 __attribute__ ((pure, always_inline));
3536 static inline u64 NIXX_AF_MDQX_PARENT(u64 a)
3538 return 0x1480 + 0x10000 * a;
3542 * Register (RVU_PF_BAR0) nix#_af_mdq#_pir
3544 * NIX AF Meta Descriptor Queue Peak Information Rate Registers This
3545 * register has the same bit fields as NIX_AF_TL1()_CIR.
3547 union nixx_af_mdqx_pir {
3549 struct nixx_af_mdqx_pir_s {
3551 u64 rate_mantissa : 8;
3552 u64 rate_exponent : 4;
3553 u64 rate_divider_exponent : 4;
3554 u64 reserved_17_28 : 12;
3555 u64 burst_mantissa : 8;
3556 u64 burst_exponent : 4;
3557 u64 reserved_41_63 : 23;
3559 /* struct nixx_af_mdqx_pir_s cn; */
3562 static inline u64 NIXX_AF_MDQX_PIR(u64 a)
3563 __attribute__ ((pure, always_inline));
3564 static inline u64 NIXX_AF_MDQX_PIR(u64 a)
3566 return 0x1430 + 0x10000 * a;
3570 * Register (RVU_PF_BAR0) nix#_af_mdq#_pointers
3572 * INTERNAL: NIX AF Meta Descriptor 4 Linked List Pointers Debug Register
3573 * This register has the same bit fields as NIX_AF_TL4()_POINTERS.
3575 union nixx_af_mdqx_pointers {
3577 struct nixx_af_mdqx_pointers_s {
3579 u64 reserved_9_15 : 7;
3581 u64 reserved_25_63 : 39;
3583 /* struct nixx_af_mdqx_pointers_s cn; */
3586 static inline u64 NIXX_AF_MDQX_POINTERS(u64 a)
3587 __attribute__ ((pure, always_inline));
3588 static inline u64 NIXX_AF_MDQX_POINTERS(u64 a)
3590 return 0x1460 + 0x10000 * a;
3594 * Register (RVU_PF_BAR0) nix#_af_mdq#_ptr_fifo
3596 * INTERNAL: NIX Meta Descriptor Queue Pointer FIFO State Debug Registers
3598 union nixx_af_mdqx_ptr_fifo {
3600 struct nixx_af_mdqx_ptr_fifo_s {
3604 u64 reserved_9_63 : 55;
3606 /* struct nixx_af_mdqx_ptr_fifo_s cn; */
3609 static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a)
3610 __attribute__ ((pure, always_inline));
3611 static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a)
3613 return 0x14d0 + 0x10000 * a;
3617 * Register (RVU_PF_BAR0) nix#_af_mdq#_sched_state
3619 * NIX AF Meta Descriptor Queue Scheduling Control State Registers This
3620 * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE.
3622 union nixx_af_mdqx_sched_state {
3624 struct nixx_af_mdqx_sched_state_s {
3626 u64 reserved_25_63 : 39;
3628 /* struct nixx_af_mdqx_sched_state_s cn; */
3631 static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a)
3632 __attribute__ ((pure, always_inline));
3633 static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a)
3635 return 0x1440 + 0x10000 * a;
3639 * Register (RVU_PF_BAR0) nix#_af_mdq#_schedule
3641 * NIX AF Meta Descriptor Queue Scheduling Control Registers This
3642 * register has the same bit fields as NIX_AF_TL2()_SCHEDULE.
3644 union nixx_af_mdqx_schedule {
3646 struct nixx_af_mdqx_schedule_s {
3647 u64 rr_quantum : 24;
3649 u64 reserved_28_63 : 36;
3651 /* struct nixx_af_mdqx_schedule_s cn; */
3654 static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a)
3655 __attribute__ ((pure, always_inline));
3656 static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a)
3658 return 0x1400 + 0x10000 * a;
3662 * Register (RVU_PF_BAR0) nix#_af_mdq#_shape
3664 * NIX AF Meta Descriptor Queue Shaping Control Registers This register
3665 * has the same bit fields as NIX_AF_TL3()_SHAPE.
3667 union nixx_af_mdqx_shape {
3669 struct nixx_af_mdqx_shape_s {
3672 u64 red_disable : 1;
3673 u64 yellow_disable : 1;
3674 u64 reserved_13_23 : 11;
3675 u64 length_disable : 1;
3676 u64 schedule_list : 2;
3677 u64 reserved_27_63 : 37;
3679 /* struct nixx_af_mdqx_shape_s cn; */
3682 static inline u64 NIXX_AF_MDQX_SHAPE(u64 a)
3683 __attribute__ ((pure, always_inline));
3684 static inline u64 NIXX_AF_MDQX_SHAPE(u64 a)
3686 return 0x1410 + 0x10000 * a;
3690 * Register (RVU_PF_BAR0) nix#_af_mdq#_shape_state
3692 * NIX AF Meta Descriptor Queue Shaping State Registers This register has
3693 * the same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must
3694 * not be written during normal operation.
3696 union nixx_af_mdqx_shape_state {
3698 struct nixx_af_mdqx_shape_state_s {
3702 u64 reserved_54_63 : 10;
3704 /* struct nixx_af_mdqx_shape_state_s cn; */
3707 static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a)
3708 __attribute__ ((pure, always_inline));
3709 static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a)
3711 return 0x1450 + 0x10000 * a;
3715 * Register (RVU_PF_BAR0) nix#_af_mdq#_sw_xoff
3717 * NIX AF Meta Descriptor Controlled XOFF Registers This register has the
3718 * same bit fields as NIX_AF_TL1()_SW_XOFF
3720 union nixx_af_mdqx_sw_xoff {
3722 struct nixx_af_mdqx_sw_xoff_s {
3727 u64 reserved_4_63 : 60;
3729 /* struct nixx_af_mdqx_sw_xoff_s cn; */
3732 static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a)
3733 __attribute__ ((pure, always_inline));
3734 static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a)
3736 return 0x1470 + 0x10000 * a;
3740 * Register (RVU_PF_BAR0) nix#_af_mdq_const
3742 * NIX AF Meta Descriptor Queue Constants Register This register contains
3743 * constants for software discovery.
3745 union nixx_af_mdq_const {
3747 struct nixx_af_mdq_const_s {
3749 u64 reserved_16_63 : 48;
3751 /* struct nixx_af_mdq_const_s cn; */
3754 static inline u64 NIXX_AF_MDQ_CONST(void)
3755 __attribute__ ((pure, always_inline));
3756 static inline u64 NIXX_AF_MDQ_CONST(void)
3762 * Register (RVU_PF_BAR0) nix#_af_ndc_cfg
3764 * NIX AF General Configuration Register
3766 union nixx_af_ndc_cfg {
3768 struct nixx_af_ndc_cfg_s {
3769 u64 ndc_ign_pois : 1;
3778 u64 byp_mc_data : 1;
3780 u64 byp_mr_data : 1;
3783 u64 reserved_14_63 : 50;
3785 /* struct nixx_af_ndc_cfg_s cn; */
3788 static inline u64 NIXX_AF_NDC_CFG(void)
3789 __attribute__ ((pure, always_inline));
3790 static inline u64 NIXX_AF_NDC_CFG(void)
3796 * Register (RVU_PF_BAR0) nix#_af_ndc_rx_sync
3798 * NIX AF Receive NDC Sync Register Used to synchronize the NIX receive
3799 * NDC (NDC_IDX_E::NIX()_RX).
3801 union nixx_af_ndc_rx_sync {
3803 struct nixx_af_ndc_rx_sync_s {
3805 u64 reserved_8_11 : 4;
3807 u64 reserved_13_63 : 51;
3809 /* struct nixx_af_ndc_rx_sync_s cn; */
3812 static inline u64 NIXX_AF_NDC_RX_SYNC(void)
3813 __attribute__ ((pure, always_inline));
3814 static inline u64 NIXX_AF_NDC_RX_SYNC(void)
3820 * Register (RVU_PF_BAR0) nix#_af_ndc_tx_sync
3822 * NIX AF NDC_TX Sync Register Used to synchronize the NIX transmit NDC
3823 * (NDC_IDX_E::NIX()_TX).
3825 union nixx_af_ndc_tx_sync {
3827 struct nixx_af_ndc_tx_sync_s {
3829 u64 reserved_8_11 : 4;
3831 u64 reserved_13_63 : 51;
3833 /* struct nixx_af_ndc_tx_sync_s cn; */
3836 static inline u64 NIXX_AF_NDC_TX_SYNC(void)
3837 __attribute__ ((pure, always_inline));
3838 static inline u64 NIXX_AF_NDC_TX_SYNC(void)
3844 * Register (RVU_PF_BAR0) nix#_af_norm_tx_fifo_status
3846 * NIX AF Normal Transmit FIFO Status Register Status of FIFO which
3847 * transmits normal packets to CGX and LBK.
3849 union nixx_af_norm_tx_fifo_status {
3851 struct nixx_af_norm_tx_fifo_status_s {
3853 u64 reserved_12_63 : 52;
3855 /* struct nixx_af_norm_tx_fifo_status_s cn; */
3858 static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void)
3859 __attribute__ ((pure, always_inline));
3860 static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void)
3866 * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_exp
3868 * INTERNAL: NIX AF PQ Arb Link EXPRESS Debug Register
3870 union nixx_af_pqx_dbg_arb_link_exp {
3872 struct nixx_af_pqx_dbg_arb_link_exp_s {
3876 u64 reserved_4_5 : 2;
3878 u64 reserved_7_63 : 57;
3880 /* struct nixx_af_pqx_dbg_arb_link_exp_s cn; */
3883 static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a)
3884 __attribute__ ((pure, always_inline));
3885 static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a)
3887 return 0xce8 + 0x10000 * a;
3891 * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_nrm
3893 * INTERNAL: NIX AF PQ Arb Link NORMAL Debug Register
3895 union nixx_af_pqx_dbg_arb_link_nrm {
3897 struct nixx_af_pqx_dbg_arb_link_nrm_s {
3901 u64 reserved_4_5 : 2;
3903 u64 reserved_7_63 : 57;
3905 /* struct nixx_af_pqx_dbg_arb_link_nrm_s cn; */
3908 static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a)
3909 __attribute__ ((pure, always_inline));
3910 static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a)
3912 return 0xce0 + 0x10000 * a;
3916 * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_sdp
3918 * INTERNAL: NIX AF PQ Arb Link SDP Debug Register
3920 union nixx_af_pqx_dbg_arb_link_sdp {
3922 struct nixx_af_pqx_dbg_arb_link_sdp_s {
3926 u64 reserved_4_5 : 2;
3928 u64 reserved_7_63 : 57;
3930 /* struct nixx_af_pqx_dbg_arb_link_sdp_s cn; */
3933 static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a)
3934 __attribute__ ((pure, always_inline));
3935 static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a)
3937 return 0xcf0 + 0x10000 * a;
3941 * Register (RVU_PF_BAR0) nix#_af_pq_arb_crd_rdy_debug
3943 * INTERNAL: NIX AF PQ_ARB Node Credit Ready Registers NIX AF PQ ARB
3944 * Credit ready register
3946 union nixx_af_pq_arb_crd_rdy_debug {
3948 struct nixx_af_pq_arb_crd_rdy_debug_s {
3949 u64 node_crd_rdy : 28;
3950 u64 reserved_28_63 : 36;
3952 /* struct nixx_af_pq_arb_crd_rdy_debug_s cn; */
3955 static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void)
3956 __attribute__ ((pure, always_inline));
3957 static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void)
3963 * Register (RVU_PF_BAR0) nix#_af_pq_arb_dwrr_msk_debug
3965 * INTERNAL: NIX AF PQ_ARB DWRR mask set read only debug Registers
3967 union nixx_af_pq_arb_dwrr_msk_debug {
3969 struct nixx_af_pq_arb_dwrr_msk_debug_s {
3970 u64 node_dwrr_mask_set : 28;
3971 u64 reserved_28_63 : 36;
3973 /* struct nixx_af_pq_arb_dwrr_msk_debug_s cn; */
3976 static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void)
3977 __attribute__ ((pure, always_inline));
3978 static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void)
3984 * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_gnt_debug
3986 * INTERNAL: NIX AF PQ_ARB Node Grant vector Registers
3988 union nixx_af_pq_arb_node_gnt_debug {
3990 struct nixx_af_pq_arb_node_gnt_debug_s {
3991 u64 node_grant_vec : 28;
3992 u64 reserved_28_63 : 36;
3994 /* struct nixx_af_pq_arb_node_gnt_debug_s cn; */
3997 static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void)
3998 __attribute__ ((pure, always_inline));
3999 static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void)
4005 * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_req_debug
4007 * INTERNAL: NIX AF PQ_ARB Node Request Debug Registers NIX AF PQ ARB
4008 * Node Request Debug register
4010 union nixx_af_pq_arb_node_req_debug {
4012 struct nixx_af_pq_arb_node_req_debug_s {
4014 u64 reserved_28_63 : 36;
4016 /* struct nixx_af_pq_arb_node_req_debug_s cn; */
4019 static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void)
4020 __attribute__ ((pure, always_inline));
4021 static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void)
4027 * Register (RVU_PF_BAR0) nix#_af_pq_arb_shape_vld_dbg
4029 * INTERNAL: NIX AF PQ_ARB shape valid set Register
4031 union nixx_af_pq_arb_shape_vld_dbg {
4033 struct nixx_af_pq_arb_shape_vld_dbg_s {
4034 u64 node_shape_vld_set : 28;
4035 u64 reserved_28_63 : 36;
4037 /* struct nixx_af_pq_arb_shape_vld_dbg_s cn; */
4040 static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void)
4041 __attribute__ ((pure, always_inline));
4042 static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void)
4048 * Register (RVU_PF_BAR0) nix#_af_pq_dbg_arb_0
4050 * INTERNAL: NIX AF PQ Arb Debug 0 Register
4052 union nixx_af_pq_dbg_arb_0 {
4054 struct nixx_af_pq_dbg_arb_0_s {
4055 u64 rr_mask_clr : 1;
4056 u64 reserved_1_63 : 63;
4058 /* struct nixx_af_pq_dbg_arb_0_s cn; */
4061 static inline u64 NIXX_AF_PQ_DBG_ARB_0(void)
4062 __attribute__ ((pure, always_inline));
4063 static inline u64 NIXX_AF_PQ_DBG_ARB_0(void)
4069 * Register (RVU_PF_BAR0) nix#_af_pq_lnk_#_dwrr_msk_dbg
4071 * INTERNAL: NIX AF PQ_ARB Physical Link DWRR MASK Registers
4073 union nixx_af_pq_lnk_x_dwrr_msk_dbg {
4075 struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s {
4076 u64 link_dwrr_mask_set : 28;
4077 u64 reserved_28_63 : 36;
4079 /* struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s cn; */
4082 static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a)
4083 __attribute__ ((pure, always_inline));
4084 static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a)
4086 return 0x1100 + 0x10000 * a;
4090 * Register (RVU_PF_BAR0) nix#_af_pse_400_rate_divider
4092 * INTERNAL: NIX AF PSE 400 Rate Divider Register
4094 union nixx_af_pse_400_rate_divider {
4096 struct nixx_af_pse_400_rate_divider_s {
4097 u64 rate_div_cfg : 9;
4098 u64 reserved_9_63 : 55;
4100 /* struct nixx_af_pse_400_rate_divider_s cn; */
4103 static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void)
4104 __attribute__ ((pure, always_inline));
4105 static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void)
4111 * Register (RVU_PF_BAR0) nix#_af_pse_active_cycles_pc
4113 * NIX AF Active Cycles Register These registers are indexed by the
4114 * conditional clock domain number.
4116 union nixx_af_pse_active_cycles_pc {
4118 struct nixx_af_pse_active_cycles_pc_s {
4121 /* struct nixx_af_pse_active_cycles_pc_s cn; */
4124 static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void)
4125 __attribute__ ((pure, always_inline));
4126 static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void)
4132 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test0
4134 * INTERNAL: NIX AF PSE Backpressure Test 0 Register
4136 union nixx_af_pse_bp_test0 {
4138 struct nixx_af_pse_bp_test0_s {
4140 u64 reserved_12_63 : 52;
4142 struct nixx_af_pse_bp_test0_cn96xxp1 {
4144 u64 reserved_12_15 : 4;
4146 u64 reserved_24_59 : 36;
4149 struct nixx_af_pse_bp_test0_cn96xxp3 {
4151 u64 reserved_12_15 : 4;
4152 u64 reserved_16_19 : 4;
4154 u64 reserved_32_55 : 24;
4155 u64 reserved_56_57 : 2;
4158 /* struct nixx_af_pse_bp_test0_cn96xxp1 cnf95xxp1; */
4159 struct nixx_af_pse_bp_test0_cnf95xxp2 {
4161 u64 reserved_12_15 : 4;
4163 u64 reserved_24_31 : 8;
4164 u64 reserved_32_55 : 24;
4165 u64 reserved_56_59 : 4;
4170 static inline u64 NIXX_AF_PSE_BP_TEST0(void)
4171 __attribute__ ((pure, always_inline));
4172 static inline u64 NIXX_AF_PSE_BP_TEST0(void)
4178 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test1
4180 * INTERNAL: NIX AF PSE Backpressure Test 1 Register
4182 union nixx_af_pse_bp_test1 {
4184 struct nixx_af_pse_bp_test1_s {
4186 u64 reserved_12_15 : 4;
4188 u64 reserved_26_63 : 38;
4190 struct nixx_af_pse_bp_test1_cn96xxp1 {
4192 u64 reserved_12_15 : 4;
4194 u64 reserved_24_59 : 36;
4197 struct nixx_af_pse_bp_test1_cn96xxp3 {
4199 u64 reserved_12_15 : 4;
4201 u64 reserved_26_31 : 6;
4202 u64 reserved_32_55 : 24;
4203 u64 reserved_56_58 : 3;
4206 /* struct nixx_af_pse_bp_test1_cn96xxp1 cnf95xxp1; */
4207 struct nixx_af_pse_bp_test1_cnf95xxp2 {
4209 u64 reserved_12_15 : 4;
4211 u64 reserved_24_31 : 8;
4212 u64 reserved_32_55 : 24;
4213 u64 reserved_56_59 : 4;
4218 static inline u64 NIXX_AF_PSE_BP_TEST1(void)
4219 __attribute__ ((pure, always_inline));
4220 static inline u64 NIXX_AF_PSE_BP_TEST1(void)
4226 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test2
4228 * INTERNAL: NIX AF PSE Backpressure Test 2 Register
4230 union nixx_af_pse_bp_test2 {
4232 struct nixx_af_pse_bp_test2_s {
4234 u64 reserved_12_15 : 4;
4236 u64 reserved_26_63 : 38;
4238 struct nixx_af_pse_bp_test2_cn96xxp1 {
4240 u64 reserved_12_15 : 4;
4242 u64 reserved_24_59 : 36;
4245 struct nixx_af_pse_bp_test2_cn96xxp3 {
4247 u64 reserved_12_15 : 4;
4249 u64 reserved_26_31 : 6;
4250 u64 reserved_32_55 : 24;
4251 u64 reserved_56_58 : 3;
4254 /* struct nixx_af_pse_bp_test2_cn96xxp1 cnf95xxp1; */
4255 struct nixx_af_pse_bp_test2_cnf95xxp2 {
4257 u64 reserved_12_15 : 4;
4259 u64 reserved_24_31 : 8;
4260 u64 reserved_32_55 : 24;
4261 u64 reserved_56_59 : 4;
4266 static inline u64 NIXX_AF_PSE_BP_TEST2(void)
4267 __attribute__ ((pure, always_inline));
4268 static inline u64 NIXX_AF_PSE_BP_TEST2(void)
4274 * Register (RVU_PF_BAR0) nix#_af_pse_bp_test3
4276 * INTERNAL: NIX AF PSE Backpressure Test 3 Register
4278 union nixx_af_pse_bp_test3 {
4280 struct nixx_af_pse_bp_test3_s {
4282 u64 reserved_12_15 : 4;
4284 u64 reserved_26_63 : 38;
4286 struct nixx_af_pse_bp_test3_cn96xxp1 {
4288 u64 reserved_12_15 : 4;
4290 u64 reserved_24_59 : 36;
4293 struct nixx_af_pse_bp_test3_cn96xxp3 {
4295 u64 reserved_12_15 : 4;
4297 u64 reserved_26_31 : 6;
4298 u64 reserved_32_55 : 24;
4299 u64 reserved_56_58 : 3;
4302 /* struct nixx_af_pse_bp_test3_cn96xxp1 cnf95xxp1; */
4303 struct nixx_af_pse_bp_test3_cnf95xxp2 {
4305 u64 reserved_12_15 : 4;
4307 u64 reserved_24_31 : 8;
4308 u64 reserved_32_55 : 24;
4309 u64 reserved_56_59 : 4;
4314 static inline u64 NIXX_AF_PSE_BP_TEST3(void)
4315 __attribute__ ((pure, always_inline));
4316 static inline u64 NIXX_AF_PSE_BP_TEST3(void)
4322 * Register (RVU_PF_BAR0) nix#_af_pse_channel_level
4324 * NIX AF PSE Channel Level Register
4326 union nixx_af_pse_channel_level {
4328 struct nixx_af_pse_channel_level_s {
4330 u64 reserved_1_63 : 63;
4332 /* struct nixx_af_pse_channel_level_s cn; */
4335 static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void)
4336 __attribute__ ((pure, always_inline));
4337 static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void)
4343 * Register (RVU_PF_BAR0) nix#_af_pse_const
4345 * NIX AF PSE Constants Register This register contains constants for
4346 * software discovery.
4348 union nixx_af_pse_const {
4350 struct nixx_af_pse_const_s {
4352 u64 reserved_4_7 : 4;
4353 u64 mark_formats : 8;
4354 u64 reserved_16_63 : 48;
4356 /* struct nixx_af_pse_const_s cn; */
4359 static inline u64 NIXX_AF_PSE_CONST(void)
4360 __attribute__ ((pure, always_inline));
4361 static inline u64 NIXX_AF_PSE_CONST(void)
4367 * Register (RVU_PF_BAR0) nix#_af_pse_eco
4369 * INTERNAL: AF PSE ECO Register
4371 union nixx_af_pse_eco {
4373 struct nixx_af_pse_eco_s {
4376 /* struct nixx_af_pse_eco_s cn; */
4379 static inline u64 NIXX_AF_PSE_ECO(void)
4380 __attribute__ ((pure, always_inline));
4381 static inline u64 NIXX_AF_PSE_ECO(void)
4387 * Register (RVU_PF_BAR0) nix#_af_pse_expr_bp_test
4389 * INTERNAL: NIX AF PSE Express Backpressure Test Register Internal:
4390 * 802.3br frame preemption/express path is defeatured.
4392 union nixx_af_pse_expr_bp_test {
4394 struct nixx_af_pse_expr_bp_test_s {
4396 u64 reserved_12_15 : 4;
4400 /* struct nixx_af_pse_expr_bp_test_s cn; */
4403 static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void)
4404 __attribute__ ((pure, always_inline));
4405 static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void)
4411 * Register (RVU_PF_BAR0) nix#_af_pse_norm_bp_test
4413 * INTERNAL: NIX AF PSE Normal Backpressure Test Register
4415 union nixx_af_pse_norm_bp_test {
4417 struct nixx_af_pse_norm_bp_test_s {
4419 u64 reserved_12_15 : 4;
4421 u64 reserved_48_63 : 16;
4423 struct nixx_af_pse_norm_bp_test_cn96xxp1 {
4425 u64 reserved_12_15 : 4;
4429 struct nixx_af_pse_norm_bp_test_cn96xxp3 {
4431 u64 reserved_12_15 : 4;
4433 u64 reserved_28_57 : 30;
4436 /* struct nixx_af_pse_norm_bp_test_cn96xxp1 cnf95xx; */
4439 static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void)
4440 __attribute__ ((pure, always_inline));
4441 static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void)
4447 * Register (RVU_PF_BAR0) nix#_af_pse_shaper_cfg
4449 * NIX AF PSE Shaper Configuration Register
4451 union nixx_af_pse_shaper_cfg {
4453 struct nixx_af_pse_shaper_cfg_s {
4454 u64 red_send_as_yellow : 1;
4455 u64 color_aware : 1;
4456 u64 reserved_2_63 : 62;
4458 /* struct nixx_af_pse_shaper_cfg_s cn; */
4461 static inline u64 NIXX_AF_PSE_SHAPER_CFG(void)
4462 __attribute__ ((pure, always_inline));
4463 static inline u64 NIXX_AF_PSE_SHAPER_CFG(void)
4469 * Register (RVU_PF_BAR0) nix#_af_ras
4471 * NIX AF RAS Interrupt Register This register is intended for delivery
4472 * of RAS events to the SCP, so should be ignored by OS drivers.
4476 struct nixx_af_ras_s {
4477 u64 rx_mce_poison : 1;
4478 u64 rx_mcast_wqe_poison : 1;
4479 u64 rx_mirror_wqe_poison : 1;
4480 u64 rx_mcast_data_poison : 1;
4481 u64 rx_mirror_data_poison : 1;
4482 u64 reserved_5_31 : 27;
4483 u64 aq_ctx_poison : 1;
4484 u64 aq_res_poison : 1;
4485 u64 aq_inst_poison : 1;
4486 u64 reserved_35_63 : 29;
4488 /* struct nixx_af_ras_s cn; */
4491 static inline u64 NIXX_AF_RAS(void)
4492 __attribute__ ((pure, always_inline));
4493 static inline u64 NIXX_AF_RAS(void)
4499 * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1c
4501 * NIX AF RAS Interrupt Enable Clear Register This register clears
4502 * interrupt enable bits.
4504 union nixx_af_ras_ena_w1c {
4506 struct nixx_af_ras_ena_w1c_s {
4507 u64 rx_mce_poison : 1;
4508 u64 rx_mcast_wqe_poison : 1;
4509 u64 rx_mirror_wqe_poison : 1;
4510 u64 rx_mcast_data_poison : 1;
4511 u64 rx_mirror_data_poison : 1;
4512 u64 reserved_5_31 : 27;
4513 u64 aq_ctx_poison : 1;
4514 u64 aq_res_poison : 1;
4515 u64 aq_inst_poison : 1;
4516 u64 reserved_35_63 : 29;
4518 /* struct nixx_af_ras_ena_w1c_s cn; */
4521 static inline u64 NIXX_AF_RAS_ENA_W1C(void)
4522 __attribute__ ((pure, always_inline));
4523 static inline u64 NIXX_AF_RAS_ENA_W1C(void)
4529 * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1s
4531 * NIX AF RAS Interrupt Enable Set Register This register sets interrupt
4534 union nixx_af_ras_ena_w1s {
4536 struct nixx_af_ras_ena_w1s_s {
4537 u64 rx_mce_poison : 1;
4538 u64 rx_mcast_wqe_poison : 1;
4539 u64 rx_mirror_wqe_poison : 1;
4540 u64 rx_mcast_data_poison : 1;
4541 u64 rx_mirror_data_poison : 1;
4542 u64 reserved_5_31 : 27;
4543 u64 aq_ctx_poison : 1;
4544 u64 aq_res_poison : 1;
4545 u64 aq_inst_poison : 1;
4546 u64 reserved_35_63 : 29;
4548 /* struct nixx_af_ras_ena_w1s_s cn; */
4551 static inline u64 NIXX_AF_RAS_ENA_W1S(void)
4552 __attribute__ ((pure, always_inline));
4553 static inline u64 NIXX_AF_RAS_ENA_W1S(void)
4559 * Register (RVU_PF_BAR0) nix#_af_ras_w1s
4561 * NIX AF RAS Interrupt Set Register This register sets interrupt bits.
4563 union nixx_af_ras_w1s {
4565 struct nixx_af_ras_w1s_s {
4566 u64 rx_mce_poison : 1;
4567 u64 rx_mcast_wqe_poison : 1;
4568 u64 rx_mirror_wqe_poison : 1;
4569 u64 rx_mcast_data_poison : 1;
4570 u64 rx_mirror_data_poison : 1;
4571 u64 reserved_5_31 : 27;
4572 u64 aq_ctx_poison : 1;
4573 u64 aq_res_poison : 1;
4574 u64 aq_inst_poison : 1;
4575 u64 reserved_35_63 : 29;
4577 /* struct nixx_af_ras_w1s_s cn; */
4580 static inline u64 NIXX_AF_RAS_W1S(void)
4581 __attribute__ ((pure, always_inline));
4582 static inline u64 NIXX_AF_RAS_W1S(void)
4588 * Register (RVU_PF_BAR0) nix#_af_reb_bp_test#
4590 * INTERNAL: NIX AF REB Backpressure Test Registers
4592 union nixx_af_reb_bp_testx {
4594 struct nixx_af_reb_bp_testx_s {
4596 u64 reserved_12_15 : 4;
4598 u64 reserved_24_47 : 24;
4600 u64 reserved_52_63 : 12;
4602 /* struct nixx_af_reb_bp_testx_s cn; */
4605 static inline u64 NIXX_AF_REB_BP_TESTX(u64 a)
4606 __attribute__ ((pure, always_inline));
4607 static inline u64 NIXX_AF_REB_BP_TESTX(u64 a)
4609 return 0x4840 + 0x10000 * a;
4613 * Register (RVU_PF_BAR0) nix#_af_rq_const
4615 * NIX AF RQ Constants Register This register contains constants for
4616 * software discovery.
4618 union nixx_af_rq_const {
4620 struct nixx_af_rq_const_s {
4621 u64 queues_per_lf : 24;
4622 u64 reserved_24_63 : 40;
4624 /* struct nixx_af_rq_const_s cn; */
4627 static inline u64 NIXX_AF_RQ_CONST(void)
4628 __attribute__ ((pure, always_inline));
4629 static inline u64 NIXX_AF_RQ_CONST(void)
4635 * Register (RVU_PF_BAR0) nix#_af_rqm_bp_test
4637 * INTERNAL: NIX AF REB Backpressure Test Registers
4639 union nixx_af_rqm_bp_test {
4641 struct nixx_af_rqm_bp_test_s {
4643 u64 reserved_12_15 : 4;
4645 u64 reserved_32_47 : 16;
4647 u64 reserved_56_63 : 8;
4649 /* struct nixx_af_rqm_bp_test_s cn; */
4652 static inline u64 NIXX_AF_RQM_BP_TEST(void)
4653 __attribute__ ((pure, always_inline));
4654 static inline u64 NIXX_AF_RQM_BP_TEST(void)
4660 * Register (RVU_PF_BAR0) nix#_af_rqm_eco
4662 * INTERNAL: AF RQM ECO Register
4664 union nixx_af_rqm_eco {
4666 struct nixx_af_rqm_eco_s {
4669 /* struct nixx_af_rqm_eco_s cn; */
4672 static inline u64 NIXX_AF_RQM_ECO(void)
4673 __attribute__ ((pure, always_inline));
4674 static inline u64 NIXX_AF_RQM_ECO(void)
4680 * Register (RVU_PF_BAR0) nix#_af_rvu_int
4682 * NIX AF RVU Interrupt Register This register contains RVU error
4683 * interrupt summary bits.
4685 union nixx_af_rvu_int {
4687 struct nixx_af_rvu_int_s {
4688 u64 unmapped_slot : 1;
4689 u64 reserved_1_63 : 63;
4691 /* struct nixx_af_rvu_int_s cn; */
4694 static inline u64 NIXX_AF_RVU_INT(void)
4695 __attribute__ ((pure, always_inline));
4696 static inline u64 NIXX_AF_RVU_INT(void)
4702 * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1c
4704 * NIX AF RVU Interrupt Enable Clear Register This register clears
4705 * interrupt enable bits.
4707 union nixx_af_rvu_int_ena_w1c {
4709 struct nixx_af_rvu_int_ena_w1c_s {
4710 u64 unmapped_slot : 1;
4711 u64 reserved_1_63 : 63;
4713 /* struct nixx_af_rvu_int_ena_w1c_s cn; */
4716 static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void)
4717 __attribute__ ((pure, always_inline));
4718 static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void)
4724 * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1s
4726 * NIX AF RVU Interrupt Enable Set Register This register sets interrupt
4729 union nixx_af_rvu_int_ena_w1s {
4731 struct nixx_af_rvu_int_ena_w1s_s {
4732 u64 unmapped_slot : 1;
4733 u64 reserved_1_63 : 63;
4735 /* struct nixx_af_rvu_int_ena_w1s_s cn; */
4738 static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void)
4739 __attribute__ ((pure, always_inline));
4740 static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void)
4746 * Register (RVU_PF_BAR0) nix#_af_rvu_int_w1s
4748 * NIX AF RVU Interrupt Set Register This register sets interrupt bits.
4750 union nixx_af_rvu_int_w1s {
4752 struct nixx_af_rvu_int_w1s_s {
4753 u64 unmapped_slot : 1;
4754 u64 reserved_1_63 : 63;
4756 /* struct nixx_af_rvu_int_w1s_s cn; */
4759 static inline u64 NIXX_AF_RVU_INT_W1S(void)
4760 __attribute__ ((pure, always_inline));
4761 static inline u64 NIXX_AF_RVU_INT_W1S(void)
4767 * Register (RVU_PF_BAR0) nix#_af_rvu_lf_cfg_debug
4769 * NIX Privileged LF Configuration Debug Register This debug register
4770 * allows software to lookup the reverse mapping from VF/PF slot to LF.
4771 * The forward mapping is programmed with NIX_PRIV_LF()_CFG.
4773 union nixx_af_rvu_lf_cfg_debug {
4775 struct nixx_af_rvu_lf_cfg_debug_s {
4779 u64 reserved_14_15 : 2;
4782 u64 reserved_40_63 : 24;
4784 /* struct nixx_af_rvu_lf_cfg_debug_s cn; */
4787 static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void)
4788 __attribute__ ((pure, always_inline));
4789 static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void)
4795 * Register (RVU_PF_BAR0) nix#_af_rx_active_cycles_pc#
4797 * NIX AF Active Cycles Register These registers are indexed by the
4798 * conditional clock domain number.
4800 union nixx_af_rx_active_cycles_pcx {
4802 struct nixx_af_rx_active_cycles_pcx_s {
4805 /* struct nixx_af_rx_active_cycles_pcx_s cn; */
4808 static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a)
4809 __attribute__ ((pure, always_inline));
4810 static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a)
4812 return 0x4800 + 0x10000 * a;
4816 * Register (RVU_PF_BAR0) nix#_af_rx_bpid#_status
4818 * NIX AF Receive Backpressure ID Status Registers
4820 union nixx_af_rx_bpidx_status {
4822 struct nixx_af_rx_bpidx_status_s {
4826 /* struct nixx_af_rx_bpidx_status_s cn; */
4829 static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a)
4830 __attribute__ ((pure, always_inline));
4831 static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a)
4833 return 0x1a20 + 0x20000 * a;
4837 * Register (RVU_PF_BAR0) nix#_af_rx_cfg
4839 * NIX AF Receive Configuration Register
4841 union nixx_af_rx_cfg {
4843 struct nixx_af_rx_cfg_s {
4845 u64 reserved_1_63 : 63;
4847 /* struct nixx_af_rx_cfg_s cn; */
4850 static inline u64 NIXX_AF_RX_CFG(void)
4851 __attribute__ ((pure, always_inline));
4852 static inline u64 NIXX_AF_RX_CFG(void)
4858 * Register (RVU_PF_BAR0) nix#_af_rx_chan#_cfg
4860 * NIX AF Receive Channel Configuration Registers
4862 union nixx_af_rx_chanx_cfg {
4864 struct nixx_af_rx_chanx_cfg_s {
4866 u64 reserved_9_15 : 7;
4870 u64 reserved_19_63 : 45;
4872 /* struct nixx_af_rx_chanx_cfg_s cn; */
4875 static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a)
4876 __attribute__ ((pure, always_inline));
4877 static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a)
4879 return 0x1a30 + 0x8000 * a;
4883 * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_credit
4885 * INTERNAL: NIX AF Receive CPT Credit Register Internal: Not used; no
4888 union nixx_af_rx_cptx_credit {
4890 struct nixx_af_rx_cptx_credit_s {
4891 u64 inst_cred_cnt : 22;
4892 u64 reserved_22_63 : 42;
4894 /* struct nixx_af_rx_cptx_credit_s cn; */
4897 static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a)
4898 __attribute__ ((pure, always_inline));
4899 static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a)
4901 return 0x360 + 8 * a;
4905 * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_inst_qsel
4907 * INTERNAL: NIX AF Receive CPT Instruction Queue Select Register
4908 * Internal: Not used; no IPSEC fast-path.
4910 union nixx_af_rx_cptx_inst_qsel {
4912 struct nixx_af_rx_cptx_inst_qsel_s {
4915 u64 reserved_24_63 : 40;
4917 /* struct nixx_af_rx_cptx_inst_qsel_s cn; */
4920 static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a)
4921 __attribute__ ((pure, always_inline));
4922 static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a)
4924 return 0x320 + 8 * a;
4928 * Register (RVU_PF_BAR0) nix#_af_rx_def_iip4
4930 * NIX AF Receive Inner IPv4 Header Definition Register Defines layer
4931 * information in NPC_RESULT_S to identify an inner IPv4 header.
4932 * Typically the same as NPC_AF_PCK_DEF_IIP4.
4934 union nixx_af_rx_def_iip4 {
4936 struct nixx_af_rx_def_iip4_s {
4938 u64 ltype_match : 4;
4940 u64 reserved_11_63 : 53;
4942 /* struct nixx_af_rx_def_iip4_s cn; */
4945 static inline u64 NIXX_AF_RX_DEF_IIP4(void)
4946 __attribute__ ((pure, always_inline));
4947 static inline u64 NIXX_AF_RX_DEF_IIP4(void)
4953 * Register (RVU_PF_BAR0) nix#_af_rx_def_iip6
4955 * NIX AF Receive Inner IPv6 Header Definition Register Defines layer
4956 * information in NPC_RESULT_S to identify an inner IPv6 header.
4958 union nixx_af_rx_def_iip6 {
4960 struct nixx_af_rx_def_iip6_s {
4962 u64 ltype_match : 4;
4964 u64 reserved_11_63 : 53;
4966 /* struct nixx_af_rx_def_iip6_s cn; */
4969 static inline u64 NIXX_AF_RX_DEF_IIP6(void)
4970 __attribute__ ((pure, always_inline));
4971 static inline u64 NIXX_AF_RX_DEF_IIP6(void)
4977 * Register (RVU_PF_BAR0) nix#_af_rx_def_ipsec#
4979 * INTERNAL: NIX AF Receive IPSEC Header Definition Registers Internal:
4980 * Not used; no IPSEC fast-path.
4982 union nixx_af_rx_def_ipsecx {
4984 struct nixx_af_rx_def_ipsecx_s {
4986 u64 ltype_match : 4;
4988 u64 reserved_11 : 1;
4991 u64 reserved_17_63 : 47;
4993 /* struct nixx_af_rx_def_ipsecx_s cn; */
4996 static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a)
4997 __attribute__ ((pure, always_inline));
4998 static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a)
5000 return 0x2b0 + 8 * a;
5004 * Register (RVU_PF_BAR0) nix#_af_rx_def_isctp
5006 * NIX AF Receive Inner SCTP Header Definition Register Defines layer
5007 * information in NPC_RESULT_S to identify an inner SCTP header.
5009 union nixx_af_rx_def_isctp {
5011 struct nixx_af_rx_def_isctp_s {
5013 u64 ltype_match : 4;
5015 u64 reserved_11_63 : 53;
5017 /* struct nixx_af_rx_def_isctp_s cn; */
5020 static inline u64 NIXX_AF_RX_DEF_ISCTP(void)
5021 __attribute__ ((pure, always_inline));
5022 static inline u64 NIXX_AF_RX_DEF_ISCTP(void)
5028 * Register (RVU_PF_BAR0) nix#_af_rx_def_itcp
5030 * NIX AF Receive Inner TCP Header Definition Register Defines layer
5031 * information in NPC_RESULT_S to identify an inner TCP header.
5033 union nixx_af_rx_def_itcp {
5035 struct nixx_af_rx_def_itcp_s {
5037 u64 ltype_match : 4;
5039 u64 reserved_11_63 : 53;
5041 /* struct nixx_af_rx_def_itcp_s cn; */
5044 static inline u64 NIXX_AF_RX_DEF_ITCP(void)
5045 __attribute__ ((pure, always_inline));
5046 static inline u64 NIXX_AF_RX_DEF_ITCP(void)
5052 * Register (RVU_PF_BAR0) nix#_af_rx_def_iudp
5054 * NIX AF Receive Inner UDP Header Definition Register Defines layer
5055 * information in NPC_RESULT_S to identify an inner UDP header.
5057 union nixx_af_rx_def_iudp {
5059 struct nixx_af_rx_def_iudp_s {
5061 u64 ltype_match : 4;
5063 u64 reserved_11_63 : 53;
5065 /* struct nixx_af_rx_def_iudp_s cn; */
5068 static inline u64 NIXX_AF_RX_DEF_IUDP(void)
5069 __attribute__ ((pure, always_inline));
5070 static inline u64 NIXX_AF_RX_DEF_IUDP(void)
5076 * Register (RVU_PF_BAR0) nix#_af_rx_def_oip4
5078 * NIX AF Receive Outer IPv4 Header Definition Register Defines layer
5079 * information in NPC_RESULT_S to identify an outer IPv4 L3 header.
5080 * Typically the same as NPC_AF_PCK_DEF_OIP4.
5082 union nixx_af_rx_def_oip4 {
5084 struct nixx_af_rx_def_oip4_s {
5086 u64 ltype_match : 4;
5088 u64 reserved_11_63 : 53;
5090 /* struct nixx_af_rx_def_oip4_s cn; */
5093 static inline u64 NIXX_AF_RX_DEF_OIP4(void)
5094 __attribute__ ((pure, always_inline));
5095 static inline u64 NIXX_AF_RX_DEF_OIP4(void)
5101 * Register (RVU_PF_BAR0) nix#_af_rx_def_oip6
5103 * NIX AF Receive Outer IPv6 Header Definition Register Defines layer
5104 * information in NPC_RESULT_S to identify an outer IPv6 header.
5105 * Typically the same as NPC_AF_PCK_DEF_OIP6.
5107 union nixx_af_rx_def_oip6 {
5109 struct nixx_af_rx_def_oip6_s {
5111 u64 ltype_match : 4;
5113 u64 reserved_11_63 : 53;
5115 /* struct nixx_af_rx_def_oip6_s cn; */
5118 static inline u64 NIXX_AF_RX_DEF_OIP6(void)
5119 __attribute__ ((pure, always_inline));
5120 static inline u64 NIXX_AF_RX_DEF_OIP6(void)
5126 * Register (RVU_PF_BAR0) nix#_af_rx_def_ol2
5128 * NIX AF Receive Outer L2 Header Definition Register Defines layer
5129 * information in NPC_RESULT_S to identify an outer L2/Ethernet header.
5130 * Typically the same as NPC_AF_PCK_DEF_OL2.
5132 union nixx_af_rx_def_ol2 {
5134 struct nixx_af_rx_def_ol2_s {
5136 u64 ltype_match : 4;
5138 u64 reserved_11_63 : 53;
5140 /* struct nixx_af_rx_def_ol2_s cn; */
5143 static inline u64 NIXX_AF_RX_DEF_OL2(void)
5144 __attribute__ ((pure, always_inline));
5145 static inline u64 NIXX_AF_RX_DEF_OL2(void)
5151 * Register (RVU_PF_BAR0) nix#_af_rx_def_osctp
5153 * NIX AF Receive Outer SCTP Header Definition Register Defines layer
5154 * information in NPC_RESULT_S to identify an outer SCTP header.
5156 union nixx_af_rx_def_osctp {
5158 struct nixx_af_rx_def_osctp_s {
5160 u64 ltype_match : 4;
5162 u64 reserved_11_63 : 53;
5164 /* struct nixx_af_rx_def_osctp_s cn; */
5167 static inline u64 NIXX_AF_RX_DEF_OSCTP(void)
5168 __attribute__ ((pure, always_inline));
5169 static inline u64 NIXX_AF_RX_DEF_OSCTP(void)
5175 * Register (RVU_PF_BAR0) nix#_af_rx_def_otcp
5177 * NIX AF Receive Outer TCP Header Definition Register Defines layer
5178 * information in NPC_RESULT_S to identify an outer TCP header.
5180 union nixx_af_rx_def_otcp {
5182 struct nixx_af_rx_def_otcp_s {
5184 u64 ltype_match : 4;
5186 u64 reserved_11_63 : 53;
5188 /* struct nixx_af_rx_def_otcp_s cn; */
5191 static inline u64 NIXX_AF_RX_DEF_OTCP(void)
5192 __attribute__ ((pure, always_inline));
5193 static inline u64 NIXX_AF_RX_DEF_OTCP(void)
5199 * Register (RVU_PF_BAR0) nix#_af_rx_def_oudp
5201 * NIX AF Receive Outer UDP Header Definition Register Defines layer
5202 * information in NPC_RESULT_S to identify an outer UDP header.
5204 union nixx_af_rx_def_oudp {
5206 struct nixx_af_rx_def_oudp_s {
5208 u64 ltype_match : 4;
5210 u64 reserved_11_63 : 53;
5212 /* struct nixx_af_rx_def_oudp_s cn; */
5215 static inline u64 NIXX_AF_RX_DEF_OUDP(void)
5216 __attribute__ ((pure, always_inline));
5217 static inline u64 NIXX_AF_RX_DEF_OUDP(void)
5223 * Register (RVU_PF_BAR0) nix#_af_rx_flow_key_alg#_field#
5225 * NIX AF Receive Flow Key Algorithm Field Registers A flow key algorithm
5226 * defines how the 40-byte FLOW_KEY is formed from the received packet
5227 * header. FLOW_KEY is formed using up to five header fields (this
5228 * register's last index) with up to 16 bytes per field. Header fields
5229 * must not overlap in FLOW_KEY. The algorithm (index {a} (ALG) of these
5230 * registers) is selected by NIX_RX_ACTION_S[FLOW_KEY_ALG] from the
5231 * packet's NPC_RESULT_S[ACTION]. Internal: 40-byte FLOW_KEY is wide
5232 * enough to support an IPv6 5-tuple that includes a VXLAN/GENEVE/NVGRE
5233 * tunnel ID, e.g: _ Source IP: 16B. _ Dest IP: 16B. _ Source port: 2B. _
5234 * Dest port: 2B. _ Tunnel VNI/VSI: 3B. _ Total: 39B.
5236 union nixx_af_rx_flow_key_algx_fieldx {
5238 struct nixx_af_rx_flow_key_algx_fieldx_s {
5245 u64 reserved_24 : 1;
5249 u64 ltype_match : 4;
5250 u64 reserved_35_63 : 29;
5252 /* struct nixx_af_rx_flow_key_algx_fieldx_s cn; */
5255 static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b)
5256 __attribute__ ((pure, always_inline));
5257 static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b)
5259 return 0x1800 + 0x40000 * a + 8 * b;
5263 * Register (RVU_PF_BAR0) nix#_af_rx_ipsec_gen_cfg
5265 * INTERNAL: NIX AF Receive IPSEC General Configuration Register
5266 * Internal: Not used; no IPSEC fast-path.
5268 union nixx_af_rx_ipsec_gen_cfg {
5270 struct nixx_af_rx_ipsec_gen_cfg_s {
5275 u64 reserved_51_63 : 13;
5277 /* struct nixx_af_rx_ipsec_gen_cfg_s cn; */
5280 static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void)
5281 __attribute__ ((pure, always_inline));
5282 static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void)
5288 * Register (RVU_PF_BAR0) nix#_af_rx_link#_cfg
5290 * NIX AF Receive Link Configuration Registers Index enumerated by
5293 union nixx_af_rx_linkx_cfg {
5295 struct nixx_af_rx_linkx_cfg_s {
5298 u64 reserved_32_63 : 32;
5300 /* struct nixx_af_rx_linkx_cfg_s cn; */
5303 static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a)
5304 __attribute__ ((pure, always_inline));
5305 static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a)
5307 return 0x540 + 0x10000 * a;
5311 * Register (RVU_PF_BAR0) nix#_af_rx_link#_sl#_spkt_cnt
5313 * INTERNAL: NIX Receive Software Sync Link Packet Count Registers For
5314 * diagnostic use only for debug of NIX_AF_RX_SW_SYNC[ENA] function. LINK
5315 * index is enumerated by NIX_LINK_E. For the internal multicast/mirror
5316 * link (NIX_LINK_E::MC), SL index is zero for multicast replay, one for
5317 * mirror replay. SL index one is reserved for all other links.
5318 * Internal: 802.3br frame preemption/express path is defeatured. Old
5319 * definition of SL index: SL index is zero for non-express packets, one
5320 * for express packets. For the internal NIX_LINK_E::MC, SL index is zero
5321 * for multicast replay, one for mirror replay.
5323 union nixx_af_rx_linkx_slx_spkt_cnt {
5325 struct nixx_af_rx_linkx_slx_spkt_cnt_s {
5327 u64 reserved_20_31 : 12;
5329 u64 reserved_52_63 : 12;
5331 /* struct nixx_af_rx_linkx_slx_spkt_cnt_s cn; */
5334 static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b)
5335 __attribute__ ((pure, always_inline));
5336 static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b)
5338 return 0x500 + 0x10000 * a + 8 * b;
5342 * Register (RVU_PF_BAR0) nix#_af_rx_link#_wrr_cfg
5344 * NIX AF Receive Link Weighted Round Robin Configuration Registers Index
5345 * enumerated by NIX_LINK_E.
5347 union nixx_af_rx_linkx_wrr_cfg {
5349 struct nixx_af_rx_linkx_wrr_cfg_s {
5351 u64 reserved_8_63 : 56;
5353 /* struct nixx_af_rx_linkx_wrr_cfg_s cn; */
5356 static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a)
5357 __attribute__ ((pure, always_inline));
5358 static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a)
5360 return 0x560 + 0x10000 * a;
5364 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_base
5366 * NIX AF Receive Multicast/Mirror Table Base Address Register This
5367 * register specifies the base AF IOVA of the receive multicast/mirror
5368 * table in NDC/LLC/DRAM. The table consists of 1 \<\<
5369 * (NIX_AF_RX_MCAST_CFG[SIZE] + 8) contiguous NIX_RX_MCE_S structures.
5370 * The size of each structure is 1 \<\< NIX_AF_CONST3[MCE_LOG2BYTES].
5371 * The table contains multicast/mirror replication lists. Each list
5372 * consists of linked entries with NIX_RX_MCE_S[EOL] = 1 in the last
5373 * entry. All lists must reside within the table size specified by
5374 * NIX_AF_RX_MCAST_CFG[SIZE]. A mirror replication list will typically
5375 * consist of two entries, but that is not checked or enforced by
5376 * hardware. A receive packet is multicast when the action returned by
5377 * NPC has NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MCAST. A receive
5378 * packet is mirrored when the action returned by NPC has
5379 * NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MIRROR. In both cases,
5380 * NIX_RX_ACTION_S[INDEX] specifies the index of the replication list's
5381 * first NIX_RX_MCE_S in the table, and a linked entry with
5382 * NIX_RX_MCE_S[EOL] = 1 indicates the end of list. If a mirrored flow
5383 * is part of a multicast replication list, software should include the
5384 * two mirror entries in that list. Internal: A multicast list may have
5385 * multiple entries for the same LF (e.g. for future RoCE/IB multicast).
5387 union nixx_af_rx_mcast_base {
5389 struct nixx_af_rx_mcast_base_s {
5390 u64 reserved_0_6 : 7;
5392 u64 reserved_53_63 : 11;
5394 /* struct nixx_af_rx_mcast_base_s cn; */
5397 static inline u64 NIXX_AF_RX_MCAST_BASE(void)
5398 __attribute__ ((pure, always_inline));
5399 static inline u64 NIXX_AF_RX_MCAST_BASE(void)
5405 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_base
5407 * NIX AF Receive Multicast Buffer Base Address Register This register
5408 * specifies the base AF IOVA of the receive multicast buffers in
5409 * NDC/LLC/DRAM. These buffers are used to temporarily store packets
5410 * whose action returned by NPC has NIX_RX_ACTION_S[OP] =
5411 * NIX_RX_ACTIONOP_E::MCAST. The number of buffers is configured by
5412 * NIX_AF_RX_MCAST_BUF_CFG[SIZE]. If the number of free buffers is
5413 * insufficient for a received multicast packet, hardware tail drops the
5414 * packet and sets NIX_AF_GEN_INT[RX_MCAST_DROP]. Hardware prioritizes
5415 * the processing of RX mirror packets over RX multicast packets.
5417 union nixx_af_rx_mcast_buf_base {
5419 struct nixx_af_rx_mcast_buf_base_s {
5420 u64 reserved_0_6 : 7;
5422 u64 reserved_53_63 : 11;
5424 /* struct nixx_af_rx_mcast_buf_base_s cn; */
5427 static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void)
5428 __attribute__ ((pure, always_inline));
5429 static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void)
5435 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_cfg
5437 * NIX AF Receive Multicast Buffer Configuration Register See
5438 * NIX_AF_RX_MCAST_BUF_BASE.
5440 union nixx_af_rx_mcast_buf_cfg {
5442 struct nixx_af_rx_mcast_buf_cfg_s {
5446 u64 reserved_21_23 : 3;
5447 u64 npc_replay_pkind : 6;
5448 u64 reserved_30_31 : 2;
5449 u64 free_buf_level : 11;
5450 u64 reserved_43_61 : 19;
5454 struct nixx_af_rx_mcast_buf_cfg_cn96xxp1 {
5458 u64 reserved_21_23 : 3;
5459 u64 npc_replay_pkind : 6;
5460 u64 reserved_30_31 : 2;
5461 u64 free_buf_level : 11;
5462 u64 reserved_43_61 : 19;
5463 u64 reserved_62 : 1;
5466 /* struct nixx_af_rx_mcast_buf_cfg_s cn96xxp3; */
5467 struct nixx_af_rx_mcast_buf_cfg_cnf95xxp1 {
5471 u64 reserved_21_23 : 3;
5472 u64 npc_replay_pkind : 6;
5473 u64 reserved_30_31 : 2;
5474 u64 free_buf_level : 11;
5475 u64 reserved_43_62 : 20;
5478 /* struct nixx_af_rx_mcast_buf_cfg_s cnf95xxp2; */
5481 static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void)
5482 __attribute__ ((pure, always_inline));
5483 static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void)
5489 * Register (RVU_PF_BAR0) nix#_af_rx_mcast_cfg
5491 * NIX AF Receive Multicast/Mirror Table Configuration Register See
5492 * NIX_AF_RX_MCAST_BASE.
5494 union nixx_af_rx_mcast_cfg {
5496 struct nixx_af_rx_mcast_cfg_s {
5498 u64 max_list_lenm1 : 8;
5499 u64 reserved_12_19 : 8;
5502 u64 reserved_37_63 : 27;
5504 /* struct nixx_af_rx_mcast_cfg_s cn; */
5507 static inline u64 NIXX_AF_RX_MCAST_CFG(void)
5508 __attribute__ ((pure, always_inline));
5509 static inline u64 NIXX_AF_RX_MCAST_CFG(void)
5515 * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_base
5517 * NIX AF Receive Mirror Buffer Base Address Register This register
5518 * specifies the base AF IOVA of the receive mirror buffers in
5519 * NDC/LLC/DRAM. These buffers are used to temporarily store packets
5520 * whose action returned by NPC has NIX_RX_ACTION_S[OP] =
5521 * NIX_RX_ACTIONOP_E::MIRROR. The number of buffers is configured by
5522 * NIX_AF_RX_MIRROR_BUF_CFG[SIZE]. If the number of free buffers is
5523 * insufficient for a received multicast packet, hardware tail drops the
5524 * packet and sets NIX_AF_GEN_INT[RX_MIRROR_DROP]. Hardware prioritizes
5525 * the processing of RX mirror packets over RX multicast packets.
5527 union nixx_af_rx_mirror_buf_base {
5529 struct nixx_af_rx_mirror_buf_base_s {
5530 u64 reserved_0_6 : 7;
5532 u64 reserved_53_63 : 11;
5534 /* struct nixx_af_rx_mirror_buf_base_s cn; */
5537 static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void)
5538 __attribute__ ((pure, always_inline));
5539 static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void)
5545 * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_cfg
5547 * NIX AF Receive Mirror Buffer Configuration Register See
5548 * NIX_AF_RX_MIRROR_BUF_BASE.
5550 union nixx_af_rx_mirror_buf_cfg {
5552 struct nixx_af_rx_mirror_buf_cfg_s {
5556 u64 reserved_21_23 : 3;
5557 u64 npc_replay_pkind : 6;
5558 u64 reserved_30_31 : 2;
5559 u64 free_buf_level : 11;
5560 u64 reserved_43_61 : 19;
5564 struct nixx_af_rx_mirror_buf_cfg_cn96xxp1 {
5568 u64 reserved_21_23 : 3;
5569 u64 npc_replay_pkind : 6;
5570 u64 reserved_30_31 : 2;
5571 u64 free_buf_level : 11;
5572 u64 reserved_43_61 : 19;
5573 u64 reserved_62 : 1;
5576 /* struct nixx_af_rx_mirror_buf_cfg_s cn96xxp3; */
5577 struct nixx_af_rx_mirror_buf_cfg_cnf95xxp1 {
5581 u64 reserved_21_23 : 3;
5582 u64 npc_replay_pkind : 6;
5583 u64 reserved_30_31 : 2;
5584 u64 free_buf_level : 11;
5585 u64 reserved_43_62 : 20;
5588 /* struct nixx_af_rx_mirror_buf_cfg_s cnf95xxp2; */
5591 static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void)
5592 __attribute__ ((pure, always_inline));
5593 static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void)
5599 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_drop
5601 * NIX AF Multicast Drop Statistics Register The counter increments for
5602 * every dropped MC packet marked by the NPC.
5604 union nixx_af_rx_npc_mc_drop {
5606 struct nixx_af_rx_npc_mc_drop_s {
5608 u64 reserved_48_63 : 16;
5610 /* struct nixx_af_rx_npc_mc_drop_s cn; */
5613 static inline u64 NIXX_AF_RX_NPC_MC_DROP(void)
5614 __attribute__ ((pure, always_inline));
5615 static inline u64 NIXX_AF_RX_NPC_MC_DROP(void)
5621 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_rcv
5623 * NIX AF Multicast Receive Statistics Register The counter increments
5624 * for every received MC packet marked by the NPC.
5626 union nixx_af_rx_npc_mc_rcv {
5628 struct nixx_af_rx_npc_mc_rcv_s {
5630 u64 reserved_48_63 : 16;
5632 /* struct nixx_af_rx_npc_mc_rcv_s cn; */
5635 static inline u64 NIXX_AF_RX_NPC_MC_RCV(void)
5636 __attribute__ ((pure, always_inline));
5637 static inline u64 NIXX_AF_RX_NPC_MC_RCV(void)
5643 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_drop
5645 * NIX AF Mirror Drop Statistics Register The counter increments for
5646 * every dropped MIRROR packet marked by the NPC.
5648 union nixx_af_rx_npc_mirror_drop {
5650 struct nixx_af_rx_npc_mirror_drop_s {
5652 u64 reserved_48_63 : 16;
5654 /* struct nixx_af_rx_npc_mirror_drop_s cn; */
5657 static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void)
5658 __attribute__ ((pure, always_inline));
5659 static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void)
5665 * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_rcv
5667 * NIX AF Mirror Receive Statistics Register The counter increments for
5668 * every received MIRROR packet marked by the NPC.
5670 union nixx_af_rx_npc_mirror_rcv {
5672 struct nixx_af_rx_npc_mirror_rcv_s {
5674 u64 reserved_48_63 : 16;
5676 /* struct nixx_af_rx_npc_mirror_rcv_s cn; */
5679 static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void)
5680 __attribute__ ((pure, always_inline));
5681 static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void)
5687 * Register (RVU_PF_BAR0) nix#_af_rx_sw_sync
5689 * NIX AF Receive Software Sync Register
5691 union nixx_af_rx_sw_sync {
5693 struct nixx_af_rx_sw_sync_s {
5695 u64 reserved_1_63 : 63;
5697 /* struct nixx_af_rx_sw_sync_s cn; */
5700 static inline u64 NIXX_AF_RX_SW_SYNC(void)
5701 __attribute__ ((pure, always_inline));
5702 static inline u64 NIXX_AF_RX_SW_SYNC(void)
5708 * Register (RVU_PF_BAR0) nix#_af_sdp_hw_xoff#
5710 * NIX AF SDP Transmit Link Hardware Controlled XOFF Registers .
5712 union nixx_af_sdp_hw_xoffx {
5714 struct nixx_af_sdp_hw_xoffx_s {
5717 /* struct nixx_af_sdp_hw_xoffx_s cn; */
5720 static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a)
5721 __attribute__ ((pure, always_inline));
5722 static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a)
5724 return 0xac0 + 8 * a;
5728 * Register (RVU_PF_BAR0) nix#_af_sdp_link_credit
5730 * NIX AF Transmit Link SDP Credit Register This register tracks SDP link
5733 union nixx_af_sdp_link_credit {
5735 struct nixx_af_sdp_link_credit_s {
5738 u64 cc_packet_cnt : 10;
5739 u64 cc_unit_cnt : 20;
5740 u64 reserved_32_62 : 31;
5741 u64 pse_pkt_id_lmt : 1;
5743 struct nixx_af_sdp_link_credit_cn96xx {
5746 u64 cc_packet_cnt : 10;
5747 u64 cc_unit_cnt : 20;
5748 u64 reserved_32_62 : 31;
5749 u64 reserved_63 : 1;
5751 /* struct nixx_af_sdp_link_credit_s cnf95xx; */
5754 static inline u64 NIXX_AF_SDP_LINK_CREDIT(void)
5755 __attribute__ ((pure, always_inline));
5756 static inline u64 NIXX_AF_SDP_LINK_CREDIT(void)
5762 * Register (RVU_PF_BAR0) nix#_af_sdp_sw_xoff#
5764 * INTERNAL: NIX AF SDP Transmit Link Software Controlled XOFF Registers
5765 * Internal: Defeatured registers. Software should use
5766 * NIX_AF_TL4()_SW_XOFF registers instead.
5768 union nixx_af_sdp_sw_xoffx {
5770 struct nixx_af_sdp_sw_xoffx_s {
5773 /* struct nixx_af_sdp_sw_xoffx_s cn; */
5776 static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a)
5777 __attribute__ ((pure, always_inline));
5778 static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a)
5780 return 0xa60 + 8 * a;
5784 * Register (RVU_PF_BAR0) nix#_af_sdp_tx_fifo_status
5786 * NIX AF SDP Transmit FIFO Status Register Status of FIFO which
5787 * transmits packets to SDP.
5789 union nixx_af_sdp_tx_fifo_status {
5791 struct nixx_af_sdp_tx_fifo_status_s {
5793 u64 reserved_12_63 : 52;
5795 /* struct nixx_af_sdp_tx_fifo_status_s cn; */
5798 static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void)
5799 __attribute__ ((pure, always_inline));
5800 static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void)
5806 * Register (RVU_PF_BAR0) nix#_af_seb_active_cycles_pc#
5808 * NIX AF Active Cycles Register These registers are indexed by the
5809 * conditional clock domain number.
5811 union nixx_af_seb_active_cycles_pcx {
5813 struct nixx_af_seb_active_cycles_pcx_s {
5816 /* struct nixx_af_seb_active_cycles_pcx_s cn; */
5819 static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a)
5820 __attribute__ ((pure, always_inline));
5821 static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a)
5823 return 0x6c0 + 8 * a;
5827 * Register (RVU_PF_BAR0) nix#_af_seb_bp_test
5829 * INTERNAL: NIX AF SEB Backpressure Test Register
5831 union nixx_af_seb_bp_test {
5833 struct nixx_af_seb_bp_test_s {
5835 u64 reserved_12_15 : 4;
5837 u64 reserved_30_47 : 18;
5839 u64 reserved_55_63 : 9;
5841 /* struct nixx_af_seb_bp_test_s cn; */
5844 static inline u64 NIXX_AF_SEB_BP_TEST(void)
5845 __attribute__ ((pure, always_inline));
5846 static inline u64 NIXX_AF_SEB_BP_TEST(void)
5852 * Register (RVU_PF_BAR0) nix#_af_seb_cfg
5854 * NIX SEB Configuration Register
5856 union nixx_af_seb_cfg {
5858 struct nixx_af_seb_cfg_s {
5860 u64 reserved_1_63 : 63;
5862 /* struct nixx_af_seb_cfg_s cn; */
5865 static inline u64 NIXX_AF_SEB_CFG(void)
5866 __attribute__ ((pure, always_inline));
5867 static inline u64 NIXX_AF_SEB_CFG(void)
5873 * Register (RVU_PF_BAR0) nix#_af_seb_eco
5875 * INTERNAL: AF SEB ECO Register
5877 union nixx_af_seb_eco {
5879 struct nixx_af_seb_eco_s {
5882 /* struct nixx_af_seb_eco_s cn; */
5885 static inline u64 NIXX_AF_SEB_ECO(void)
5886 __attribute__ ((pure, always_inline));
5887 static inline u64 NIXX_AF_SEB_ECO(void)
5893 * Register (RVU_PF_BAR0) nix#_af_seb_pipe_bp_test#
5895 * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers
5897 union nixx_af_seb_pipe_bp_testx {
5899 struct nixx_af_seb_pipe_bp_testx_s {
5901 u64 reserved_12_15 : 4;
5903 u64 reserved_40_47 : 8;
5905 u64 reserved_60_63 : 4;
5907 /* struct nixx_af_seb_pipe_bp_testx_s cn; */
5910 static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a)
5911 __attribute__ ((pure, always_inline));
5912 static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a)
5914 return 0x600 + 0x10 * a;
5918 * Register (RVU_PF_BAR0) nix#_af_seb_pipeb_bp_test#
5920 * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers
5922 union nixx_af_seb_pipeb_bp_testx {
5924 struct nixx_af_seb_pipeb_bp_testx_s {
5926 u64 reserved_12_15 : 4;
5928 u64 reserved_34_47 : 14;
5930 u64 reserved_57_63 : 7;
5932 /* struct nixx_af_seb_pipeb_bp_testx_s cn; */
5935 static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a)
5936 __attribute__ ((pure, always_inline));
5937 static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a)
5939 return 0x608 + 0x10 * a;
5943 * Register (RVU_PF_BAR0) nix#_af_seb_wd_tick_divider
5945 * INTERNAL: NIX AF SEB TSTMP Watchdog Tick Divider Register
5947 union nixx_af_seb_wd_tick_divider {
5949 struct nixx_af_seb_wd_tick_divider_s {
5950 u64 tick_div_cfg : 7;
5951 u64 reserved_7_63 : 57;
5953 /* struct nixx_af_seb_wd_tick_divider_s cn; */
5956 static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void)
5957 __attribute__ ((pure, always_inline));
5958 static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void)
5964 * Register (RVU_PF_BAR0) nix#_af_smq#_cfg
5966 * NIX AF SQM PSE Queue Configuration Registers
5968 union nixx_af_smqx_cfg {
5970 struct nixx_af_smqx_cfg_s {
5972 u64 desc_shp_ctl_dis : 1;
5975 u64 reserved_31_35 : 5;
5976 u64 max_vtag_ins : 3;
5982 u64 reserved_57_63 : 7;
5984 /* struct nixx_af_smqx_cfg_s cn; */
5987 static inline u64 NIXX_AF_SMQX_CFG(u64 a)
5988 __attribute__ ((pure, always_inline));
5989 static inline u64 NIXX_AF_SMQX_CFG(u64 a)
5991 return 0x700 + 0x10000 * a;
5995 * Register (RVU_PF_BAR0) nix#_af_smq#_head
5997 * NIX AF SQM SMQ Head Register These registers track the head of the SMQ
6000 union nixx_af_smqx_head {
6002 struct nixx_af_smqx_head_s {
6005 u64 reserved_21_63 : 43;
6007 /* struct nixx_af_smqx_head_s cn; */
6010 static inline u64 NIXX_AF_SMQX_HEAD(u64 a)
6011 __attribute__ ((pure, always_inline));
6012 static inline u64 NIXX_AF_SMQX_HEAD(u64 a)
6014 return 0x710 + 0x10000 * a;
6018 * Register (RVU_PF_BAR0) nix#_af_smq#_nxt_head
6020 * NIX AF SQM SMQ Next Head Register These registers track the next head
6021 * of the SMQ linked list.
6023 union nixx_af_smqx_nxt_head {
6025 struct nixx_af_smqx_nxt_head_s {
6028 u64 reserved_21_63 : 43;
6030 /* struct nixx_af_smqx_nxt_head_s cn; */
6033 static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a)
6034 __attribute__ ((pure, always_inline));
6035 static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a)
6037 return 0x740 + 0x10000 * a;
6041 * Register (RVU_PF_BAR0) nix#_af_smq#_status
6043 * NIX AF SQM SMQ Status Register These registers track the status of the
6046 union nixx_af_smqx_status {
6048 struct nixx_af_smqx_status_s {
6050 u64 reserved_7_63 : 57;
6052 /* struct nixx_af_smqx_status_s cn; */
6055 static inline u64 NIXX_AF_SMQX_STATUS(u64 a)
6056 __attribute__ ((pure, always_inline));
6057 static inline u64 NIXX_AF_SMQX_STATUS(u64 a)
6059 return 0x730 + 0x10000 * a;
6063 * Register (RVU_PF_BAR0) nix#_af_smq#_tail
6065 * NIX AF SQM SMQ Head Register These registers track the tail of SMQ
6068 union nixx_af_smqx_tail {
6070 struct nixx_af_smqx_tail_s {
6073 u64 reserved_21_63 : 43;
6075 /* struct nixx_af_smqx_tail_s cn; */
6078 static inline u64 NIXX_AF_SMQX_TAIL(u64 a)
6079 __attribute__ ((pure, always_inline));
6080 static inline u64 NIXX_AF_SMQX_TAIL(u64 a)
6082 return 0x720 + 0x10000 * a;
6086 * Register (RVU_PF_BAR0) nix#_af_sq_const
6088 * NIX AF SQ Constants Register This register contains constants for
6089 * software discovery.
6091 union nixx_af_sq_const {
6093 struct nixx_af_sq_const_s {
6094 u64 queues_per_lf : 24;
6097 u64 reserved_50_63 : 14;
6099 /* struct nixx_af_sq_const_s cn; */
6102 static inline u64 NIXX_AF_SQ_CONST(void)
6103 __attribute__ ((pure, always_inline));
6104 static inline u64 NIXX_AF_SQ_CONST(void)
6110 * Register (RVU_PF_BAR0) nix#_af_sqm_active_cycles_pc
6112 * NIX AF SQM Active Cycles Register These registers are indexed by the
6113 * conditional clock domain number.
6115 union nixx_af_sqm_active_cycles_pc {
6117 struct nixx_af_sqm_active_cycles_pc_s {
6120 /* struct nixx_af_sqm_active_cycles_pc_s cn; */
6123 static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void)
6124 __attribute__ ((pure, always_inline));
6125 static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void)
6131 * Register (RVU_PF_BAR0) nix#_af_sqm_bp_test#
6133 * INTERNAL: NIX AF SQM Backpressure Test Register
6135 union nixx_af_sqm_bp_testx {
6137 struct nixx_af_sqm_bp_testx_s {
6139 u64 reserved_12_15 : 4;
6141 u64 reserved_24_59 : 36;
6144 /* struct nixx_af_sqm_bp_testx_s cn; */
6147 static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a)
6148 __attribute__ ((pure, always_inline));
6149 static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a)
6151 return 0x760 + 0x10000 * a;
6155 * Register (RVU_PF_BAR0) nix#_af_sqm_dbg_ctl_status
6157 * NIX AF SQM Debug Register This register is for SQM diagnostic use
6160 union nixx_af_sqm_dbg_ctl_status {
6162 struct nixx_af_sqm_dbg_ctl_status_s {
6176 u64 reserved_26_63 : 38;
6178 struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 {
6188 u64 reserved_22_63 : 42;
6190 /* struct nixx_af_sqm_dbg_ctl_status_s cn96xxp3; */
6191 /* struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 cnf95xxp1; */
6192 struct nixx_af_sqm_dbg_ctl_status_cnf95xxp2 {
6202 u64 reserved_22 : 1;
6203 u64 reserved_23 : 1;
6204 u64 reserved_24 : 1;
6205 u64 reserved_25 : 1;
6206 u64 reserved_26_63 : 38;
6210 static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void)
6211 __attribute__ ((pure, always_inline));
6212 static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void)
6218 * Register (RVU_PF_BAR0) nix#_af_sqm_eco
6220 * INTERNAL: AF SQM ECO Register
6222 union nixx_af_sqm_eco {
6224 struct nixx_af_sqm_eco_s {
6227 /* struct nixx_af_sqm_eco_s cn; */
6230 static inline u64 NIXX_AF_SQM_ECO(void)
6231 __attribute__ ((pure, always_inline));
6232 static inline u64 NIXX_AF_SQM_ECO(void)
6238 * Register (RVU_PF_BAR0) nix#_af_status
6240 * NIX AF General Status Register
6242 union nixx_af_status {
6244 struct nixx_af_status_s {
6246 u64 calibrate_done : 1;
6247 u64 reserved_11_15 : 5;
6248 u64 calibrate_status : 15;
6249 u64 reserved_31_63 : 33;
6251 /* struct nixx_af_status_s cn; */
6254 static inline u64 NIXX_AF_STATUS(void)
6255 __attribute__ ((pure, always_inline));
6256 static inline u64 NIXX_AF_STATUS(void)
6262 * Register (RVU_PF_BAR0) nix#_af_tcp_timer
6264 * NIX TCP Timer Register
6266 union nixx_af_tcp_timer {
6268 struct nixx_af_tcp_timer_s {
6269 u64 dur_counter : 16;
6271 u64 reserved_24_31 : 8;
6273 u64 reserved_48_62 : 15;
6276 /* struct nixx_af_tcp_timer_s cn; */
6279 static inline u64 NIXX_AF_TCP_TIMER(void)
6280 __attribute__ ((pure, always_inline));
6281 static inline u64 NIXX_AF_TCP_TIMER(void)
6287 * Register (RVU_PF_BAR0) nix#_af_tl1#_cir
6289 * NIX AF Transmit Level 1 Committed Information Rate Register
6291 union nixx_af_tl1x_cir {
6293 struct nixx_af_tl1x_cir_s {
6295 u64 rate_mantissa : 8;
6296 u64 rate_exponent : 4;
6297 u64 rate_divider_exponent : 4;
6298 u64 reserved_17_28 : 12;
6299 u64 burst_mantissa : 8;
6300 u64 burst_exponent : 4;
6301 u64 reserved_41_63 : 23;
6303 /* struct nixx_af_tl1x_cir_s cn; */
6306 static inline u64 NIXX_AF_TL1X_CIR(u64 a)
6307 __attribute__ ((pure, always_inline));
6308 static inline u64 NIXX_AF_TL1X_CIR(u64 a)
6310 return 0xc20 + 0x10000 * a;
6314 * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_bytes
6316 * NIX AF Transmit Level 1 Dropped Bytes Registers This register has the
6317 * same bit fields as NIX_AF_TL1()_GREEN_BYTES.
6319 union nixx_af_tl1x_dropped_bytes {
6321 struct nixx_af_tl1x_dropped_bytes_s {
6323 u64 reserved_48_63 : 16;
6325 /* struct nixx_af_tl1x_dropped_bytes_s cn; */
6328 static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a)
6329 __attribute__ ((pure, always_inline));
6330 static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a)
6332 return 0xd30 + 0x10000 * a;
6336 * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_packets
6338 * NIX AF Transmit Level 1 Dropped Packets Registers This register has
6339 * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS.
6341 union nixx_af_tl1x_dropped_packets {
6343 struct nixx_af_tl1x_dropped_packets_s {
6345 u64 reserved_40_63 : 24;
6347 /* struct nixx_af_tl1x_dropped_packets_s cn; */
6350 static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a)
6351 __attribute__ ((pure, always_inline));
6352 static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a)
6354 return 0xd20 + 0x10000 * a;
6358 * Register (RVU_PF_BAR0) nix#_af_tl1#_green
6360 * INTERNAL: NIX Transmit Level 1 Green State Debug Register
6362 union nixx_af_tl1x_green {
6364 struct nixx_af_tl1x_green_s {
6366 u64 reserved_8_9 : 2;
6368 u64 reserved_18_19 : 2;
6369 u64 active_vec : 20;
6371 u64 reserved_41_63 : 23;
6373 /* struct nixx_af_tl1x_green_s cn; */
6376 static inline u64 NIXX_AF_TL1X_GREEN(u64 a)
6377 __attribute__ ((pure, always_inline));
6378 static inline u64 NIXX_AF_TL1X_GREEN(u64 a)
6380 return 0xc90 + 0x10000 * a;
6384 * Register (RVU_PF_BAR0) nix#_af_tl1#_green_bytes
6386 * NIX AF Transmit Level 1 Green Sent Bytes Registers
6388 union nixx_af_tl1x_green_bytes {
6390 struct nixx_af_tl1x_green_bytes_s {
6392 u64 reserved_48_63 : 16;
6394 /* struct nixx_af_tl1x_green_bytes_s cn; */
6397 static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a)
6398 __attribute__ ((pure, always_inline));
6399 static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a)
6401 return 0xd90 + 0x10000 * a;
6405 * Register (RVU_PF_BAR0) nix#_af_tl1#_green_packets
6407 * NIX AF Transmit Level 1 Green Sent Packets Registers
6409 union nixx_af_tl1x_green_packets {
6411 struct nixx_af_tl1x_green_packets_s {
6413 u64 reserved_40_63 : 24;
6415 /* struct nixx_af_tl1x_green_packets_s cn; */
6418 static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a)
6419 __attribute__ ((pure, always_inline));
6420 static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a)
6422 return 0xd80 + 0x10000 * a;
6426 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug0
6428 * NIX AF Transmit Level 1 Meta Descriptor Debug 0 Registers
6429 * NIX_AF_TL1()_MD_DEBUG0, NIX_AF_TL1()_MD_DEBUG1, NIX_AF_TL1()_MD_DEBUG2
6430 * and NIX_AF_TL1()_MD_DEBUG3 provide access to the TLn queue meta
6431 * descriptor. A TLn queue can hold up to two packet meta descriptors
6432 * (PMD) and one flush meta descriptor (FMD): * PMD0 state is accessed
6433 * with [PMD0_VLD], [PMD0_LENGTH] and NIX_AF_TL1()_MD_DEBUG1. * PMD1 is
6434 * accessed with [PMD1_VLD], [PMD1_LENGTH] and NIX_AF_TL1()_MD_DEBUG2. *
6435 * FMD is accessed with NIX_AF_TL1()_MD_DEBUG3.
6437 union nixx_af_tl1x_md_debug0 {
6439 struct nixx_af_tl1x_md_debug0_s {
6440 u64 pmd0_length : 16;
6441 u64 pmd1_length : 16;
6444 u64 reserved_34_45 : 12;
6449 u64 reserved_50_51 : 2;
6451 u64 reserved_62 : 1;
6454 /* struct nixx_af_tl1x_md_debug0_s cn96xxp1; */
6455 struct nixx_af_tl1x_md_debug0_cn96xxp3 {
6456 u64 pmd0_length : 16;
6457 u64 reserved_16_31 : 16;
6459 u64 reserved_33 : 1;
6460 u64 reserved_34_45 : 12;
6461 u64 reserved_46 : 1;
6462 u64 reserved_47 : 1;
6465 u64 reserved_50_51 : 2;
6467 u64 reserved_62 : 1;
6468 u64 reserved_63 : 1;
6470 /* struct nixx_af_tl1x_md_debug0_s cnf95xx; */
6473 static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a)
6474 __attribute__ ((pure, always_inline));
6475 static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a)
6477 return 0xcc0 + 0x10000 * a;
6481 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug1
6483 * NIX AF Transmit Level 1 Meta Descriptor Debug 1 Registers Packet meta
6484 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
6486 union nixx_af_tl1x_md_debug1 {
6488 struct nixx_af_tl1x_md_debug1_s {
6489 u64 reserved_0_5 : 6;
6490 u64 red_algo_override : 2;
6495 u64 reserved_23 : 1;
6499 u64 reserved_36 : 1;
6501 u64 sqm_pkt_id : 13;
6503 u64 reserved_62 : 1;
6506 struct nixx_af_tl1x_md_debug1_cn96xxp1 {
6507 u64 reserved_0_5 : 6;
6508 u64 red_algo_override : 2;
6517 u64 reserved_36 : 1;
6519 u64 sqm_pkt_id : 13;
6521 u64 reserved_62 : 1;
6524 struct nixx_af_tl1x_md_debug1_cn96xxp3 {
6525 u64 reserved_0_5 : 6;
6526 u64 red_algo_override : 2;
6530 u64 reserved_19_22 : 4;
6535 u64 reserved_36 : 1;
6537 u64 sqm_pkt_id : 13;
6539 u64 reserved_62 : 1;
6542 /* struct nixx_af_tl1x_md_debug1_cn96xxp1 cnf95xx; */
6545 static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a)
6546 __attribute__ ((pure, always_inline));
6547 static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a)
6549 return 0xcc8 + 0x10000 * a;
6553 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug2
6555 * NIX AF Transmit Level 1 Meta Descriptor Debug 2 Registers Packet meta
6556 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
6558 union nixx_af_tl1x_md_debug2 {
6560 struct nixx_af_tl1x_md_debug2_s {
6561 u64 reserved_0_5 : 6;
6562 u64 red_algo_override : 2;
6567 u64 reserved_23 : 1;
6571 u64 reserved_36 : 1;
6573 u64 sqm_pkt_id : 13;
6575 u64 reserved_62 : 1;
6578 struct nixx_af_tl1x_md_debug2_cn96xxp1 {
6579 u64 reserved_0_5 : 6;
6580 u64 red_algo_override : 2;
6589 u64 reserved_36 : 1;
6591 u64 sqm_pkt_id : 13;
6593 u64 reserved_62 : 1;
6596 struct nixx_af_tl1x_md_debug2_cn96xxp3 {
6597 u64 reserved_0_5 : 6;
6598 u64 red_algo_override : 2;
6602 u64 reserved_19_22 : 4;
6607 u64 reserved_36 : 1;
6609 u64 sqm_pkt_id : 13;
6611 u64 reserved_62 : 1;
6614 /* struct nixx_af_tl1x_md_debug2_cn96xxp1 cnf95xx; */
6617 static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a)
6618 __attribute__ ((pure, always_inline));
6619 static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a)
6621 return 0xcd0 + 0x10000 * a;
6625 * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug3
6627 * NIX AF Transmit Level 1 Meta Descriptor Debug 3 Registers Flush meta
6628 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
6630 union nixx_af_tl1x_md_debug3 {
6632 struct nixx_af_tl1x_md_debug3_s {
6633 u64 reserved_0_36 : 37;
6635 u64 sqm_pkt_id : 13;
6637 u64 reserved_62 : 1;
6640 /* struct nixx_af_tl1x_md_debug3_s cn96xxp1; */
6641 struct nixx_af_tl1x_md_debug3_cn96xxp3 {
6642 u64 reserved_0_36 : 37;
6643 u64 reserved_37_38 : 2;
6644 u64 reserved_39_51 : 13;
6645 u64 reserved_52_61 : 10;
6646 u64 reserved_62 : 1;
6647 u64 reserved_63 : 1;
6649 /* struct nixx_af_tl1x_md_debug3_s cnf95xx; */
6652 static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a)
6653 __attribute__ ((pure, always_inline));
6654 static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a)
6656 return 0xcd8 + 0x10000 * a;
6660 * Register (RVU_PF_BAR0) nix#_af_tl1#_red
6662 * INTERNAL: NIX Transmit Level 1 Red State Debug Register This register
6663 * has the same bit fields as NIX_AF_TL1()_YELLOW.
6665 union nixx_af_tl1x_red {
6667 struct nixx_af_tl1x_red_s {
6669 u64 reserved_8_9 : 2;
6671 u64 reserved_18_63 : 46;
6673 /* struct nixx_af_tl1x_red_s cn; */
6676 static inline u64 NIXX_AF_TL1X_RED(u64 a)
6677 __attribute__ ((pure, always_inline));
6678 static inline u64 NIXX_AF_TL1X_RED(u64 a)
6680 return 0xcb0 + 0x10000 * a;
6684 * Register (RVU_PF_BAR0) nix#_af_tl1#_red_bytes
6686 * NIX AF Transmit Level 1 Red Sent Bytes Registers This register has the
6687 * same bit fields as NIX_AF_TL1()_GREEN_BYTES.
6689 union nixx_af_tl1x_red_bytes {
6691 struct nixx_af_tl1x_red_bytes_s {
6693 u64 reserved_48_63 : 16;
6695 /* struct nixx_af_tl1x_red_bytes_s cn; */
6698 static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a)
6699 __attribute__ ((pure, always_inline));
6700 static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a)
6702 return 0xd50 + 0x10000 * a;
6706 * Register (RVU_PF_BAR0) nix#_af_tl1#_red_packets
6708 * NIX AF Transmit Level 1 Red Sent Packets Registers This register has
6709 * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS.
6711 union nixx_af_tl1x_red_packets {
6713 struct nixx_af_tl1x_red_packets_s {
6715 u64 reserved_40_63 : 24;
6717 /* struct nixx_af_tl1x_red_packets_s cn; */
6720 static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a)
6721 __attribute__ ((pure, always_inline));
6722 static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a)
6724 return 0xd40 + 0x10000 * a;
6728 * Register (RVU_PF_BAR0) nix#_af_tl1#_schedule
6730 * NIX AF Transmit Level 1 Scheduling Control Register
6732 union nixx_af_tl1x_schedule {
6734 struct nixx_af_tl1x_schedule_s {
6735 u64 rr_quantum : 24;
6736 u64 reserved_24_63 : 40;
6738 /* struct nixx_af_tl1x_schedule_s cn; */
6741 static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a)
6742 __attribute__ ((pure, always_inline));
6743 static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a)
6745 return 0xc00 + 0x10000 * a;
6749 * Register (RVU_PF_BAR0) nix#_af_tl1#_shape
6751 * NIX AF Transmit Level 1 Shaping Control Register
6753 union nixx_af_tl1x_shape {
6755 struct nixx_af_tl1x_shape_s {
6757 u64 reserved_9_23 : 15;
6758 u64 length_disable : 1;
6759 u64 reserved_25_63 : 39;
6761 struct nixx_af_tl1x_shape_cn {
6763 u64 reserved_9_17 : 9;
6764 u64 reserved_18_23 : 6;
6765 u64 length_disable : 1;
6766 u64 reserved_25_63 : 39;
6770 static inline u64 NIXX_AF_TL1X_SHAPE(u64 a)
6771 __attribute__ ((pure, always_inline));
6772 static inline u64 NIXX_AF_TL1X_SHAPE(u64 a)
6774 return 0xc10 + 0x10000 * a;
6778 * Register (RVU_PF_BAR0) nix#_af_tl1#_shape_state
6780 * NIX AF Transmit Level 1 Shape State Register This register must not be
6781 * written during normal operation.
6783 union nixx_af_tl1x_shape_state {
6785 struct nixx_af_tl1x_shape_state_s {
6787 u64 reserved_26_51 : 26;
6789 u64 reserved_53_63 : 11;
6791 /* struct nixx_af_tl1x_shape_state_s cn; */
6794 static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a)
6795 __attribute__ ((pure, always_inline));
6796 static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a)
6798 return 0xc50 + 0x10000 * a;
6802 * Register (RVU_PF_BAR0) nix#_af_tl1#_sw_xoff
6804 * NIX AF Transmit Level 1 Software Controlled XOFF Registers
6806 union nixx_af_tl1x_sw_xoff {
6808 struct nixx_af_tl1x_sw_xoff_s {
6813 u64 reserved_4_63 : 60;
6815 /* struct nixx_af_tl1x_sw_xoff_s cn; */
6818 static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a)
6819 __attribute__ ((pure, always_inline));
6820 static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a)
6822 return 0xc70 + 0x10000 * a;
6826 * Register (RVU_PF_BAR0) nix#_af_tl1#_topology
6828 * NIX AF Transmit Level 1 Topology Registers
6830 union nixx_af_tl1x_topology {
6832 struct nixx_af_tl1x_topology_s {
6835 u64 reserved_5_31 : 27;
6836 u64 prio_anchor : 8;
6837 u64 reserved_40_63 : 24;
6839 /* struct nixx_af_tl1x_topology_s cn; */
6842 static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a)
6843 __attribute__ ((pure, always_inline));
6844 static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a)
6846 return 0xc80 + 0x10000 * a;
6850 * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow
6852 * INTERNAL: NIX Transmit Level 1 Yellow State Debug Register
6854 union nixx_af_tl1x_yellow {
6856 struct nixx_af_tl1x_yellow_s {
6858 u64 reserved_8_9 : 2;
6860 u64 reserved_18_63 : 46;
6862 /* struct nixx_af_tl1x_yellow_s cn; */
6865 static inline u64 NIXX_AF_TL1X_YELLOW(u64 a)
6866 __attribute__ ((pure, always_inline));
6867 static inline u64 NIXX_AF_TL1X_YELLOW(u64 a)
6869 return 0xca0 + 0x10000 * a;
6873 * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_bytes
6875 * NIX AF Transmit Level 1 Yellow Sent Bytes Registers This register has
6876 * the same bit fields as NIX_AF_TL1()_GREEN_BYTES.
6878 union nixx_af_tl1x_yellow_bytes {
6880 struct nixx_af_tl1x_yellow_bytes_s {
6882 u64 reserved_48_63 : 16;
6884 /* struct nixx_af_tl1x_yellow_bytes_s cn; */
6887 static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a)
6888 __attribute__ ((pure, always_inline));
6889 static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a)
6891 return 0xd70 + 0x10000 * a;
6895 * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_packets
6897 * NIX AF Transmit Level 1 Yellow Sent Packets Registers This register
6898 * has the same bit fields as NIX_AF_TL1()_GREEN_PACKETS.
6900 union nixx_af_tl1x_yellow_packets {
6902 struct nixx_af_tl1x_yellow_packets_s {
6904 u64 reserved_40_63 : 24;
6906 /* struct nixx_af_tl1x_yellow_packets_s cn; */
6909 static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a)
6910 __attribute__ ((pure, always_inline));
6911 static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a)
6913 return 0xd60 + 0x10000 * a;
6917 * Register (RVU_PF_BAR0) nix#_af_tl1_const
6919 * NIX AF Transmit Level 1 Constants Register This register contains
6920 * constants for software discovery.
6922 union nixx_af_tl1_const {
6924 struct nixx_af_tl1_const_s {
6926 u64 reserved_16_63 : 48;
6928 /* struct nixx_af_tl1_const_s cn; */
6931 static inline u64 NIXX_AF_TL1_CONST(void)
6932 __attribute__ ((pure, always_inline));
6933 static inline u64 NIXX_AF_TL1_CONST(void)
6939 * Register (RVU_PF_BAR0) nix#_af_tl2#_cir
6941 * NIX AF Transmit Level 2 Committed Information Rate Registers This
6942 * register has the same bit fields as NIX_AF_TL1()_CIR.
6944 union nixx_af_tl2x_cir {
6946 struct nixx_af_tl2x_cir_s {
6948 u64 rate_mantissa : 8;
6949 u64 rate_exponent : 4;
6950 u64 rate_divider_exponent : 4;
6951 u64 reserved_17_28 : 12;
6952 u64 burst_mantissa : 8;
6953 u64 burst_exponent : 4;
6954 u64 reserved_41_63 : 23;
6956 /* struct nixx_af_tl2x_cir_s cn; */
6959 static inline u64 NIXX_AF_TL2X_CIR(u64 a)
6960 __attribute__ ((pure, always_inline));
6961 static inline u64 NIXX_AF_TL2X_CIR(u64 a)
6963 return 0xe20 + 0x10000 * a;
6967 * Register (RVU_PF_BAR0) nix#_af_tl2#_green
6969 * INTERNAL: NIX Transmit Level 2 Green State Debug Register This
6970 * register has the same bit fields as NIX_AF_TL1()_GREEN.
6972 union nixx_af_tl2x_green {
6974 struct nixx_af_tl2x_green_s {
6976 u64 reserved_8_9 : 2;
6978 u64 reserved_18_19 : 2;
6979 u64 active_vec : 20;
6981 u64 reserved_41_63 : 23;
6983 /* struct nixx_af_tl2x_green_s cn; */
6986 static inline u64 NIXX_AF_TL2X_GREEN(u64 a)
6987 __attribute__ ((pure, always_inline));
6988 static inline u64 NIXX_AF_TL2X_GREEN(u64 a)
6990 return 0xe90 + 0x10000 * a;
6994 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug0
6996 * NIX AF Transmit Level 2 Meta Descriptor Debug 0 Registers See
6997 * NIX_AF_TL1()_MD_DEBUG0
6999 union nixx_af_tl2x_md_debug0 {
7001 struct nixx_af_tl2x_md_debug0_s {
7002 u64 pmd0_length : 16;
7003 u64 pmd1_length : 16;
7006 u64 reserved_34_45 : 12;
7011 u64 reserved_50_51 : 2;
7013 u64 reserved_62 : 1;
7016 /* struct nixx_af_tl2x_md_debug0_s cn96xxp1; */
7017 struct nixx_af_tl2x_md_debug0_cn96xxp3 {
7018 u64 pmd0_length : 16;
7019 u64 reserved_16_31 : 16;
7021 u64 reserved_33 : 1;
7022 u64 reserved_34_45 : 12;
7023 u64 reserved_46 : 1;
7024 u64 reserved_47 : 1;
7027 u64 reserved_50_51 : 2;
7029 u64 reserved_62 : 1;
7030 u64 reserved_63 : 1;
7032 /* struct nixx_af_tl2x_md_debug0_s cnf95xx; */
7035 static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a)
7036 __attribute__ ((pure, always_inline));
7037 static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a)
7039 return 0xec0 + 0x10000 * a;
7043 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug1
7045 * NIX AF Transmit Level 2 Meta Descriptor Debug 1 Registers Packet meta
7046 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
7048 union nixx_af_tl2x_md_debug1 {
7050 struct nixx_af_tl2x_md_debug1_s {
7051 u64 reserved_0_5 : 6;
7052 u64 red_algo_override : 2;
7057 u64 reserved_23 : 1;
7061 u64 reserved_36 : 1;
7063 u64 sqm_pkt_id : 13;
7065 u64 reserved_62 : 1;
7068 struct nixx_af_tl2x_md_debug1_cn96xxp1 {
7069 u64 reserved_0_5 : 6;
7070 u64 red_algo_override : 2;
7079 u64 reserved_36 : 1;
7081 u64 sqm_pkt_id : 13;
7083 u64 reserved_62 : 1;
7086 struct nixx_af_tl2x_md_debug1_cn96xxp3 {
7087 u64 reserved_0_5 : 6;
7088 u64 red_algo_override : 2;
7092 u64 reserved_19_22 : 4;
7097 u64 reserved_36 : 1;
7099 u64 sqm_pkt_id : 13;
7101 u64 reserved_62 : 1;
7104 /* struct nixx_af_tl2x_md_debug1_cn96xxp1 cnf95xx; */
7107 static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a)
7108 __attribute__ ((pure, always_inline));
7109 static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a)
7111 return 0xec8 + 0x10000 * a;
7115 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug2
7117 * NIX AF Transmit Level 2 Meta Descriptor Debug 2 Registers Packet meta
7118 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
7120 union nixx_af_tl2x_md_debug2 {
7122 struct nixx_af_tl2x_md_debug2_s {
7123 u64 reserved_0_5 : 6;
7124 u64 red_algo_override : 2;
7129 u64 reserved_23 : 1;
7133 u64 reserved_36 : 1;
7135 u64 sqm_pkt_id : 13;
7137 u64 reserved_62 : 1;
7140 struct nixx_af_tl2x_md_debug2_cn96xxp1 {
7141 u64 reserved_0_5 : 6;
7142 u64 red_algo_override : 2;
7151 u64 reserved_36 : 1;
7153 u64 sqm_pkt_id : 13;
7155 u64 reserved_62 : 1;
7158 struct nixx_af_tl2x_md_debug2_cn96xxp3 {
7159 u64 reserved_0_5 : 6;
7160 u64 red_algo_override : 2;
7164 u64 reserved_19_22 : 4;
7169 u64 reserved_36 : 1;
7171 u64 sqm_pkt_id : 13;
7173 u64 reserved_62 : 1;
7176 /* struct nixx_af_tl2x_md_debug2_cn96xxp1 cnf95xx; */
7179 static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a)
7180 __attribute__ ((pure, always_inline));
7181 static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a)
7183 return 0xed0 + 0x10000 * a;
7187 * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug3
7189 * NIX AF Transmit Level 2 Meta Descriptor Debug 3 Registers Flush meta
7190 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
7192 union nixx_af_tl2x_md_debug3 {
7194 struct nixx_af_tl2x_md_debug3_s {
7195 u64 reserved_0_36 : 37;
7197 u64 sqm_pkt_id : 13;
7199 u64 reserved_62 : 1;
7202 /* struct nixx_af_tl2x_md_debug3_s cn96xxp1; */
7203 struct nixx_af_tl2x_md_debug3_cn96xxp3 {
7204 u64 reserved_0_36 : 37;
7205 u64 reserved_37_38 : 2;
7206 u64 reserved_39_51 : 13;
7207 u64 reserved_52_61 : 10;
7208 u64 reserved_62 : 1;
7209 u64 reserved_63 : 1;
7211 /* struct nixx_af_tl2x_md_debug3_s cnf95xx; */
7214 static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a)
7215 __attribute__ ((pure, always_inline));
7216 static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a)
7218 return 0xed8 + 0x10000 * a;
7222 * Register (RVU_PF_BAR0) nix#_af_tl2#_parent
7224 * NIX AF Transmit Level 2 Parent Registers
7226 union nixx_af_tl2x_parent {
7228 struct nixx_af_tl2x_parent_s {
7229 u64 reserved_0_15 : 16;
7231 u64 reserved_21_63 : 43;
7233 /* struct nixx_af_tl2x_parent_s cn; */
7236 static inline u64 NIXX_AF_TL2X_PARENT(u64 a)
7237 __attribute__ ((pure, always_inline));
7238 static inline u64 NIXX_AF_TL2X_PARENT(u64 a)
7240 return 0xe88 + 0x10000 * a;
7244 * Register (RVU_PF_BAR0) nix#_af_tl2#_pir
7246 * NIX AF Transmit Level 2 Peak Information Rate Registers This register
7247 * has the same bit fields as NIX_AF_TL1()_CIR.
7249 union nixx_af_tl2x_pir {
7251 struct nixx_af_tl2x_pir_s {
7253 u64 rate_mantissa : 8;
7254 u64 rate_exponent : 4;
7255 u64 rate_divider_exponent : 4;
7256 u64 reserved_17_28 : 12;
7257 u64 burst_mantissa : 8;
7258 u64 burst_exponent : 4;
7259 u64 reserved_41_63 : 23;
7261 /* struct nixx_af_tl2x_pir_s cn; */
7264 static inline u64 NIXX_AF_TL2X_PIR(u64 a)
7265 __attribute__ ((pure, always_inline));
7266 static inline u64 NIXX_AF_TL2X_PIR(u64 a)
7268 return 0xe30 + 0x10000 * a;
7272 * Register (RVU_PF_BAR0) nix#_af_tl2#_pointers
7274 * INTERNAL: NIX Transmit Level 2 Linked List Pointers Debug Register
7276 union nixx_af_tl2x_pointers {
7278 struct nixx_af_tl2x_pointers_s {
7280 u64 reserved_8_15 : 8;
7282 u64 reserved_24_63 : 40;
7284 /* struct nixx_af_tl2x_pointers_s cn; */
7287 static inline u64 NIXX_AF_TL2X_POINTERS(u64 a)
7288 __attribute__ ((pure, always_inline));
7289 static inline u64 NIXX_AF_TL2X_POINTERS(u64 a)
7291 return 0xe60 + 0x10000 * a;
7295 * Register (RVU_PF_BAR0) nix#_af_tl2#_red
7297 * INTERNAL: NIX Transmit Level 2 Red State Debug Register This register
7298 * has the same bit fields as NIX_AF_TL1()_RED.
7300 union nixx_af_tl2x_red {
7302 struct nixx_af_tl2x_red_s {
7304 u64 reserved_8_9 : 2;
7306 u64 reserved_18_63 : 46;
7308 /* struct nixx_af_tl2x_red_s cn; */
7311 static inline u64 NIXX_AF_TL2X_RED(u64 a)
7312 __attribute__ ((pure, always_inline));
7313 static inline u64 NIXX_AF_TL2X_RED(u64 a)
7315 return 0xeb0 + 0x10000 * a;
7319 * Register (RVU_PF_BAR0) nix#_af_tl2#_sched_state
7321 * NIX AF Transmit Level 2 Scheduling Control State Registers
7323 union nixx_af_tl2x_sched_state {
7325 struct nixx_af_tl2x_sched_state_s {
7327 u64 reserved_25_63 : 39;
7329 /* struct nixx_af_tl2x_sched_state_s cn; */
7332 static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a)
7333 __attribute__ ((pure, always_inline));
7334 static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a)
7336 return 0xe40 + 0x10000 * a;
7340 * Register (RVU_PF_BAR0) nix#_af_tl2#_schedule
7342 * NIX AF Transmit Level 2 Scheduling Control Registers
7344 union nixx_af_tl2x_schedule {
7346 struct nixx_af_tl2x_schedule_s {
7347 u64 rr_quantum : 24;
7349 u64 reserved_28_63 : 36;
7351 /* struct nixx_af_tl2x_schedule_s cn; */
7354 static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a)
7355 __attribute__ ((pure, always_inline));
7356 static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a)
7358 return 0xe00 + 0x10000 * a;
7362 * Register (RVU_PF_BAR0) nix#_af_tl2#_shape
7364 * NIX AF Transmit Level 2 Shaping Control Registers
7366 union nixx_af_tl2x_shape {
7368 struct nixx_af_tl2x_shape_s {
7371 u64 red_disable : 1;
7372 u64 yellow_disable : 1;
7373 u64 reserved_13_23 : 11;
7374 u64 length_disable : 1;
7375 u64 schedule_list : 2;
7376 u64 reserved_27_63 : 37;
7378 /* struct nixx_af_tl2x_shape_s cn; */
7381 static inline u64 NIXX_AF_TL2X_SHAPE(u64 a)
7382 __attribute__ ((pure, always_inline));
7383 static inline u64 NIXX_AF_TL2X_SHAPE(u64 a)
7385 return 0xe10 + 0x10000 * a;
7389 * Register (RVU_PF_BAR0) nix#_af_tl2#_shape_state
7391 * NIX AF Transmit Level 2 Shape State Registers This register must not
7392 * be written during normal operation.
7394 union nixx_af_tl2x_shape_state {
7396 struct nixx_af_tl2x_shape_state_s {
7400 u64 reserved_54_63 : 10;
7402 /* struct nixx_af_tl2x_shape_state_s cn; */
7405 static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a)
7406 __attribute__ ((pure, always_inline));
7407 static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a)
7409 return 0xe50 + 0x10000 * a;
7413 * Register (RVU_PF_BAR0) nix#_af_tl2#_sw_xoff
7415 * NIX AF Transmit Level 2 Software Controlled XOFF Registers This
7416 * register has the same bit fields as NIX_AF_TL1()_SW_XOFF.
7418 union nixx_af_tl2x_sw_xoff {
7420 struct nixx_af_tl2x_sw_xoff_s {
7425 u64 reserved_4_63 : 60;
7427 /* struct nixx_af_tl2x_sw_xoff_s cn; */
7430 static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a)
7431 __attribute__ ((pure, always_inline));
7432 static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a)
7434 return 0xe70 + 0x10000 * a;
7438 * Register (RVU_PF_BAR0) nix#_af_tl2#_topology
7440 * NIX AF Transmit Level 2 Topology Registers
7442 union nixx_af_tl2x_topology {
7444 struct nixx_af_tl2x_topology_s {
7447 u64 reserved_5_31 : 27;
7448 u64 prio_anchor : 8;
7449 u64 reserved_40_63 : 24;
7451 /* struct nixx_af_tl2x_topology_s cn; */
7454 static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a)
7455 __attribute__ ((pure, always_inline));
7456 static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a)
7458 return 0xe80 + 0x10000 * a;
7462 * Register (RVU_PF_BAR0) nix#_af_tl2#_yellow
7464 * INTERNAL: NIX Transmit Level 2 Yellow State Debug Register This
7465 * register has the same bit fields as NIX_AF_TL1()_YELLOW.
7467 union nixx_af_tl2x_yellow {
7469 struct nixx_af_tl2x_yellow_s {
7471 u64 reserved_8_9 : 2;
7473 u64 reserved_18_63 : 46;
7475 /* struct nixx_af_tl2x_yellow_s cn; */
7478 static inline u64 NIXX_AF_TL2X_YELLOW(u64 a)
7479 __attribute__ ((pure, always_inline));
7480 static inline u64 NIXX_AF_TL2X_YELLOW(u64 a)
7482 return 0xea0 + 0x10000 * a;
7486 * Register (RVU_PF_BAR0) nix#_af_tl2_const
7488 * NIX AF Transmit Level 2 Constants Register This register contains
7489 * constants for software discovery.
7491 union nixx_af_tl2_const {
7493 struct nixx_af_tl2_const_s {
7495 u64 reserved_16_63 : 48;
7497 /* struct nixx_af_tl2_const_s cn; */
7500 static inline u64 NIXX_AF_TL2_CONST(void)
7501 __attribute__ ((pure, always_inline));
7502 static inline u64 NIXX_AF_TL2_CONST(void)
7508 * Register (RVU_PF_BAR0) nix#_af_tl3#_cir
7510 * NIX AF Transmit Level 3 Committed Information Rate Registers This
7511 * register has the same bit fields as NIX_AF_TL1()_CIR.
7513 union nixx_af_tl3x_cir {
7515 struct nixx_af_tl3x_cir_s {
7517 u64 rate_mantissa : 8;
7518 u64 rate_exponent : 4;
7519 u64 rate_divider_exponent : 4;
7520 u64 reserved_17_28 : 12;
7521 u64 burst_mantissa : 8;
7522 u64 burst_exponent : 4;
7523 u64 reserved_41_63 : 23;
7525 /* struct nixx_af_tl3x_cir_s cn; */
7528 static inline u64 NIXX_AF_TL3X_CIR(u64 a)
7529 __attribute__ ((pure, always_inline));
7530 static inline u64 NIXX_AF_TL3X_CIR(u64 a)
7532 return 0x1020 + 0x10000 * a;
7536 * Register (RVU_PF_BAR0) nix#_af_tl3#_green
7538 * INTERNAL: NIX Transmit Level 3 Green State Debug Register
7540 union nixx_af_tl3x_green {
7542 struct nixx_af_tl3x_green_s {
7546 u64 reserved_19 : 1;
7547 u64 active_vec : 20;
7549 u64 reserved_41_63 : 23;
7551 /* struct nixx_af_tl3x_green_s cn; */
7554 static inline u64 NIXX_AF_TL3X_GREEN(u64 a)
7555 __attribute__ ((pure, always_inline));
7556 static inline u64 NIXX_AF_TL3X_GREEN(u64 a)
7558 return 0x1090 + 0x10000 * a;
7562 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug0
7564 * NIX AF Transmit Level 3 Meta Descriptor Debug 0 Registers See
7565 * NIX_AF_TL1()_MD_DEBUG0.
7567 union nixx_af_tl3x_md_debug0 {
7569 struct nixx_af_tl3x_md_debug0_s {
7570 u64 pmd0_length : 16;
7571 u64 pmd1_length : 16;
7574 u64 reserved_34_45 : 12;
7579 u64 reserved_50_51 : 2;
7581 u64 reserved_62 : 1;
7584 /* struct nixx_af_tl3x_md_debug0_s cn96xxp1; */
7585 struct nixx_af_tl3x_md_debug0_cn96xxp3 {
7586 u64 pmd0_length : 16;
7587 u64 reserved_16_31 : 16;
7589 u64 reserved_33 : 1;
7590 u64 reserved_34_45 : 12;
7591 u64 reserved_46 : 1;
7592 u64 reserved_47 : 1;
7595 u64 reserved_50_51 : 2;
7597 u64 reserved_62 : 1;
7598 u64 reserved_63 : 1;
7600 /* struct nixx_af_tl3x_md_debug0_s cnf95xx; */
7603 static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a)
7604 __attribute__ ((pure, always_inline));
7605 static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a)
7607 return 0x10c0 + 0x10000 * a;
7611 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug1
7613 * NIX AF Transmit Level 3 Meta Descriptor Debug 1 Registers Packet meta
7614 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
7616 union nixx_af_tl3x_md_debug1 {
7618 struct nixx_af_tl3x_md_debug1_s {
7619 u64 reserved_0_5 : 6;
7620 u64 red_algo_override : 2;
7625 u64 reserved_23 : 1;
7629 u64 reserved_36 : 1;
7631 u64 sqm_pkt_id : 13;
7633 u64 reserved_62 : 1;
7636 struct nixx_af_tl3x_md_debug1_cn96xxp1 {
7637 u64 reserved_0_5 : 6;
7638 u64 red_algo_override : 2;
7647 u64 reserved_36 : 1;
7649 u64 sqm_pkt_id : 13;
7651 u64 reserved_62 : 1;
7654 struct nixx_af_tl3x_md_debug1_cn96xxp3 {
7655 u64 reserved_0_5 : 6;
7656 u64 red_algo_override : 2;
7660 u64 reserved_19_22 : 4;
7665 u64 reserved_36 : 1;
7667 u64 sqm_pkt_id : 13;
7669 u64 reserved_62 : 1;
7672 /* struct nixx_af_tl3x_md_debug1_cn96xxp1 cnf95xx; */
7675 static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a)
7676 __attribute__ ((pure, always_inline));
7677 static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a)
7679 return 0x10c8 + 0x10000 * a;
7683 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug2
7685 * NIX AF Transmit Level 3 Meta Descriptor Debug 2 Registers Packet meta
7686 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
7688 union nixx_af_tl3x_md_debug2 {
7690 struct nixx_af_tl3x_md_debug2_s {
7691 u64 reserved_0_5 : 6;
7692 u64 red_algo_override : 2;
7697 u64 reserved_23 : 1;
7701 u64 reserved_36 : 1;
7703 u64 sqm_pkt_id : 13;
7705 u64 reserved_62 : 1;
7708 struct nixx_af_tl3x_md_debug2_cn96xxp1 {
7709 u64 reserved_0_5 : 6;
7710 u64 red_algo_override : 2;
7719 u64 reserved_36 : 1;
7721 u64 sqm_pkt_id : 13;
7723 u64 reserved_62 : 1;
7726 struct nixx_af_tl3x_md_debug2_cn96xxp3 {
7727 u64 reserved_0_5 : 6;
7728 u64 red_algo_override : 2;
7732 u64 reserved_19_22 : 4;
7737 u64 reserved_36 : 1;
7739 u64 sqm_pkt_id : 13;
7741 u64 reserved_62 : 1;
7744 /* struct nixx_af_tl3x_md_debug2_cn96xxp1 cnf95xx; */
7747 static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a)
7748 __attribute__ ((pure, always_inline));
7749 static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a)
7751 return 0x10d0 + 0x10000 * a;
7755 * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug3
7757 * NIX AF Transmit Level 3 Meta Descriptor Debug 3 Registers Flush meta
7758 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
7760 union nixx_af_tl3x_md_debug3 {
7762 struct nixx_af_tl3x_md_debug3_s {
7763 u64 reserved_0_36 : 37;
7765 u64 sqm_pkt_id : 13;
7767 u64 reserved_62 : 1;
7770 /* struct nixx_af_tl3x_md_debug3_s cn96xxp1; */
7771 struct nixx_af_tl3x_md_debug3_cn96xxp3 {
7772 u64 reserved_0_36 : 37;
7773 u64 reserved_37_38 : 2;
7774 u64 reserved_39_51 : 13;
7775 u64 reserved_52_61 : 10;
7776 u64 reserved_62 : 1;
7777 u64 reserved_63 : 1;
7779 /* struct nixx_af_tl3x_md_debug3_s cnf95xx; */
7782 static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a)
7783 __attribute__ ((pure, always_inline));
7784 static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a)
7786 return 0x10d8 + 0x10000 * a;
7790 * Register (RVU_PF_BAR0) nix#_af_tl3#_parent
7792 * NIX AF Transmit Level 3 Parent Registers
7794 union nixx_af_tl3x_parent {
7796 struct nixx_af_tl3x_parent_s {
7797 u64 reserved_0_15 : 16;
7799 u64 reserved_24_63 : 40;
7801 /* struct nixx_af_tl3x_parent_s cn; */
7804 static inline u64 NIXX_AF_TL3X_PARENT(u64 a)
7805 __attribute__ ((pure, always_inline));
7806 static inline u64 NIXX_AF_TL3X_PARENT(u64 a)
7808 return 0x1088 + 0x10000 * a;
7812 * Register (RVU_PF_BAR0) nix#_af_tl3#_pir
7814 * NIX AF Transmit Level 3 Peak Information Rate Registers This register
7815 * has the same bit fields as NIX_AF_TL1()_CIR.
7817 union nixx_af_tl3x_pir {
7819 struct nixx_af_tl3x_pir_s {
7821 u64 rate_mantissa : 8;
7822 u64 rate_exponent : 4;
7823 u64 rate_divider_exponent : 4;
7824 u64 reserved_17_28 : 12;
7825 u64 burst_mantissa : 8;
7826 u64 burst_exponent : 4;
7827 u64 reserved_41_63 : 23;
7829 /* struct nixx_af_tl3x_pir_s cn; */
7832 static inline u64 NIXX_AF_TL3X_PIR(u64 a)
7833 __attribute__ ((pure, always_inline));
7834 static inline u64 NIXX_AF_TL3X_PIR(u64 a)
7836 return 0x1030 + 0x10000 * a;
7840 * Register (RVU_PF_BAR0) nix#_af_tl3#_pointers
7842 * INTERNAL: NIX Transmit Level 3 Linked List Pointers Debug Register
7843 * This register has the same bit fields as NIX_AF_TL2()_POINTERS.
7845 union nixx_af_tl3x_pointers {
7847 struct nixx_af_tl3x_pointers_s {
7849 u64 reserved_8_15 : 8;
7851 u64 reserved_24_63 : 40;
7853 /* struct nixx_af_tl3x_pointers_s cn; */
7856 static inline u64 NIXX_AF_TL3X_POINTERS(u64 a)
7857 __attribute__ ((pure, always_inline));
7858 static inline u64 NIXX_AF_TL3X_POINTERS(u64 a)
7860 return 0x1060 + 0x10000 * a;
7864 * Register (RVU_PF_BAR0) nix#_af_tl3#_red
7866 * INTERNAL: NIX Transmit Level 3 Red State Debug Register This register
7867 * has the same bit fields as NIX_AF_TL3()_YELLOW.
7869 union nixx_af_tl3x_red {
7871 struct nixx_af_tl3x_red_s {
7875 u64 reserved_19_63 : 45;
7877 /* struct nixx_af_tl3x_red_s cn; */
7880 static inline u64 NIXX_AF_TL3X_RED(u64 a)
7881 __attribute__ ((pure, always_inline));
7882 static inline u64 NIXX_AF_TL3X_RED(u64 a)
7884 return 0x10b0 + 0x10000 * a;
7888 * Register (RVU_PF_BAR0) nix#_af_tl3#_sched_state
7890 * NIX AF Transmit Level 3 Scheduling Control State Registers This
7891 * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE.
7893 union nixx_af_tl3x_sched_state {
7895 struct nixx_af_tl3x_sched_state_s {
7897 u64 reserved_25_63 : 39;
7899 /* struct nixx_af_tl3x_sched_state_s cn; */
7902 static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a)
7903 __attribute__ ((pure, always_inline));
7904 static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a)
7906 return 0x1040 + 0x10000 * a;
7910 * Register (RVU_PF_BAR0) nix#_af_tl3#_schedule
7912 * NIX AF Transmit Level 3 Scheduling Control Registers This register has
7913 * the same bit fields as NIX_AF_TL2()_SCHEDULE.
7915 union nixx_af_tl3x_schedule {
7917 struct nixx_af_tl3x_schedule_s {
7918 u64 rr_quantum : 24;
7920 u64 reserved_28_63 : 36;
7922 /* struct nixx_af_tl3x_schedule_s cn; */
7925 static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a)
7926 __attribute__ ((pure, always_inline));
7927 static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a)
7929 return 0x1000 + 0x10000 * a;
7933 * Register (RVU_PF_BAR0) nix#_af_tl3#_shape
7935 * NIX AF Transmit Level 3 Shaping Control Registers
7937 union nixx_af_tl3x_shape {
7939 struct nixx_af_tl3x_shape_s {
7942 u64 red_disable : 1;
7943 u64 yellow_disable : 1;
7944 u64 reserved_13_23 : 11;
7945 u64 length_disable : 1;
7946 u64 schedule_list : 2;
7947 u64 reserved_27_63 : 37;
7949 /* struct nixx_af_tl3x_shape_s cn; */
7952 static inline u64 NIXX_AF_TL3X_SHAPE(u64 a)
7953 __attribute__ ((pure, always_inline));
7954 static inline u64 NIXX_AF_TL3X_SHAPE(u64 a)
7956 return 0x1010 + 0x10000 * a;
7960 * Register (RVU_PF_BAR0) nix#_af_tl3#_shape_state
7962 * NIX AF Transmit Level 3 Shaping State Registers This register has the
7963 * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be
7964 * written during normal operation.
7966 union nixx_af_tl3x_shape_state {
7968 struct nixx_af_tl3x_shape_state_s {
7972 u64 reserved_54_63 : 10;
7974 /* struct nixx_af_tl3x_shape_state_s cn; */
7977 static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a)
7978 __attribute__ ((pure, always_inline));
7979 static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a)
7981 return 0x1050 + 0x10000 * a;
7985 * Register (RVU_PF_BAR0) nix#_af_tl3#_sw_xoff
7987 * NIX AF Transmit Level 3 Software Controlled XOFF Registers This
7988 * register has the same bit fields as NIX_AF_TL1()_SW_XOFF
7990 union nixx_af_tl3x_sw_xoff {
7992 struct nixx_af_tl3x_sw_xoff_s {
7997 u64 reserved_4_63 : 60;
7999 /* struct nixx_af_tl3x_sw_xoff_s cn; */
8002 static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a)
8003 __attribute__ ((pure, always_inline));
8004 static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a)
8006 return 0x1070 + 0x10000 * a;
8010 * Register (RVU_PF_BAR0) nix#_af_tl3#_topology
8012 * NIX AF Transmit Level 3 Topology Registers
8014 union nixx_af_tl3x_topology {
8016 struct nixx_af_tl3x_topology_s {
8019 u64 reserved_5_31 : 27;
8020 u64 prio_anchor : 9;
8021 u64 reserved_41_63 : 23;
8023 /* struct nixx_af_tl3x_topology_s cn; */
8026 static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a)
8027 __attribute__ ((pure, always_inline));
8028 static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a)
8030 return 0x1080 + 0x10000 * a;
8034 * Register (RVU_PF_BAR0) nix#_af_tl3#_yellow
8036 * INTERNAL: NIX Transmit Level 3 Yellow State Debug Register
8038 union nixx_af_tl3x_yellow {
8040 struct nixx_af_tl3x_yellow_s {
8044 u64 reserved_19_63 : 45;
8046 /* struct nixx_af_tl3x_yellow_s cn; */
8049 static inline u64 NIXX_AF_TL3X_YELLOW(u64 a)
8050 __attribute__ ((pure, always_inline));
8051 static inline u64 NIXX_AF_TL3X_YELLOW(u64 a)
8053 return 0x10a0 + 0x10000 * a;
8057 * Register (RVU_PF_BAR0) nix#_af_tl3_const
8059 * NIX AF Transmit Level 3 Constants Register This register contains
8060 * constants for software discovery.
8062 union nixx_af_tl3_const {
8064 struct nixx_af_tl3_const_s {
8066 u64 reserved_16_63 : 48;
8068 /* struct nixx_af_tl3_const_s cn; */
8071 static inline u64 NIXX_AF_TL3_CONST(void)
8072 __attribute__ ((pure, always_inline));
8073 static inline u64 NIXX_AF_TL3_CONST(void)
8079 * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_bp_status
8081 * NIX AF Transmit Level 3/2 Backpressure Status Registers
8083 union nixx_af_tl3_tl2x_bp_status {
8085 struct nixx_af_tl3_tl2x_bp_status_s {
8087 u64 reserved_1_63 : 63;
8089 /* struct nixx_af_tl3_tl2x_bp_status_s cn; */
8092 static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a)
8093 __attribute__ ((pure, always_inline));
8094 static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a)
8096 return 0x1610 + 0x10000 * a;
8100 * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_cfg
8102 * NIX AF Transmit Level 3/2 Configuration Registers
8104 union nixx_af_tl3_tl2x_cfg {
8106 struct nixx_af_tl3_tl2x_cfg_s {
8108 u64 reserved_1_63 : 63;
8110 /* struct nixx_af_tl3_tl2x_cfg_s cn; */
8113 static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a)
8114 __attribute__ ((pure, always_inline));
8115 static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a)
8117 return 0x1600 + 0x10000 * a;
8121 * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_link#_cfg
8123 * NIX AF Transmit Level 3/2 Link Configuration Registers These registers
8124 * specify the links and associated channels that a given TL3 or TL2
8125 * queue (depending on NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL]) can transmit
8126 * on. Each TL3/TL2 queue can be enabled to transmit on and be
8127 * backpressured by one or more links and associated channels. The last
8128 * index (LINK) is enumerated by NIX_LINK_E.
8130 union nixx_af_tl3_tl2x_linkx_cfg {
8132 struct nixx_af_tl3_tl2x_linkx_cfg_s {
8134 u64 reserved_8_11 : 4;
8137 u64 reserved_14_63 : 50;
8139 /* struct nixx_af_tl3_tl2x_linkx_cfg_s cn; */
8142 static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b)
8143 __attribute__ ((pure, always_inline));
8144 static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b)
8146 return 0x1700 + 0x10000 * a + 8 * b;
8150 * Register (RVU_PF_BAR0) nix#_af_tl4#_bp_status
8152 * NIX AF Transmit Level 4 Backpressure Status Registers
8154 union nixx_af_tl4x_bp_status {
8156 struct nixx_af_tl4x_bp_status_s {
8158 u64 reserved_1_63 : 63;
8160 /* struct nixx_af_tl4x_bp_status_s cn; */
8163 static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a)
8164 __attribute__ ((pure, always_inline));
8165 static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a)
8167 return 0xb00 + 0x10000 * a;
8171 * Register (RVU_PF_BAR0) nix#_af_tl4#_cir
8173 * NIX AF Transmit Level 4 Committed Information Rate Registers This
8174 * register has the same bit fields as NIX_AF_TL1()_CIR.
8176 union nixx_af_tl4x_cir {
8178 struct nixx_af_tl4x_cir_s {
8180 u64 rate_mantissa : 8;
8181 u64 rate_exponent : 4;
8182 u64 rate_divider_exponent : 4;
8183 u64 reserved_17_28 : 12;
8184 u64 burst_mantissa : 8;
8185 u64 burst_exponent : 4;
8186 u64 reserved_41_63 : 23;
8188 /* struct nixx_af_tl4x_cir_s cn; */
8191 static inline u64 NIXX_AF_TL4X_CIR(u64 a)
8192 __attribute__ ((pure, always_inline));
8193 static inline u64 NIXX_AF_TL4X_CIR(u64 a)
8195 return 0x1220 + 0x10000 * a;
8199 * Register (RVU_PF_BAR0) nix#_af_tl4#_green
8201 * INTERNAL: NIX Transmit Level 4 Green State Debug Register This
8202 * register has the same bit fields as NIX_AF_TL3()_GREEN.
8204 union nixx_af_tl4x_green {
8206 struct nixx_af_tl4x_green_s {
8210 u64 reserved_19 : 1;
8211 u64 active_vec : 20;
8213 u64 reserved_41_63 : 23;
8215 /* struct nixx_af_tl4x_green_s cn; */
8218 static inline u64 NIXX_AF_TL4X_GREEN(u64 a)
8219 __attribute__ ((pure, always_inline));
8220 static inline u64 NIXX_AF_TL4X_GREEN(u64 a)
8222 return 0x1290 + 0x10000 * a;
8226 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug0
8228 * NIX AF Transmit Level 4 Meta Descriptor Debug 0 Registers See
8229 * NIX_AF_TL1()_MD_DEBUG0.
8231 union nixx_af_tl4x_md_debug0 {
8233 struct nixx_af_tl4x_md_debug0_s {
8234 u64 pmd0_length : 16;
8235 u64 pmd1_length : 16;
8238 u64 reserved_34_45 : 12;
8243 u64 reserved_50_51 : 2;
8245 u64 reserved_62 : 1;
8248 /* struct nixx_af_tl4x_md_debug0_s cn96xxp1; */
8249 struct nixx_af_tl4x_md_debug0_cn96xxp3 {
8250 u64 pmd0_length : 16;
8251 u64 reserved_16_31 : 16;
8253 u64 reserved_33 : 1;
8254 u64 reserved_34_45 : 12;
8255 u64 reserved_46 : 1;
8256 u64 reserved_47 : 1;
8259 u64 reserved_50_51 : 2;
8261 u64 reserved_62 : 1;
8262 u64 reserved_63 : 1;
8264 /* struct nixx_af_tl4x_md_debug0_s cnf95xx; */
8267 static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a)
8268 __attribute__ ((pure, always_inline));
8269 static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a)
8271 return 0x12c0 + 0x10000 * a;
8275 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug1
8277 * NIX AF Transmit Level 4 Meta Descriptor Debug 1 Registers Packet meta
8278 * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
8280 union nixx_af_tl4x_md_debug1 {
8282 struct nixx_af_tl4x_md_debug1_s {
8283 u64 reserved_0_5 : 6;
8284 u64 red_algo_override : 2;
8289 u64 reserved_23 : 1;
8293 u64 reserved_36 : 1;
8295 u64 sqm_pkt_id : 13;
8297 u64 reserved_62 : 1;
8300 struct nixx_af_tl4x_md_debug1_cn96xxp1 {
8301 u64 reserved_0_5 : 6;
8302 u64 red_algo_override : 2;
8311 u64 reserved_36 : 1;
8313 u64 sqm_pkt_id : 13;
8315 u64 reserved_62 : 1;
8318 struct nixx_af_tl4x_md_debug1_cn96xxp3 {
8319 u64 reserved_0_5 : 6;
8320 u64 red_algo_override : 2;
8324 u64 reserved_19_22 : 4;
8329 u64 reserved_36 : 1;
8331 u64 sqm_pkt_id : 13;
8333 u64 reserved_62 : 1;
8336 /* struct nixx_af_tl4x_md_debug1_cn96xxp1 cnf95xx; */
8339 static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a)
8340 __attribute__ ((pure, always_inline));
8341 static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a)
8343 return 0x12c8 + 0x10000 * a;
8347 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug2
8349 * NIX AF Transmit Level 4 Meta Descriptor Debug 2 Registers Packet meta
8350 * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
8352 union nixx_af_tl4x_md_debug2 {
8354 struct nixx_af_tl4x_md_debug2_s {
8355 u64 reserved_0_5 : 6;
8356 u64 red_algo_override : 2;
8361 u64 reserved_23 : 1;
8365 u64 reserved_36 : 1;
8367 u64 sqm_pkt_id : 13;
8369 u64 reserved_62 : 1;
8372 struct nixx_af_tl4x_md_debug2_cn96xxp1 {
8373 u64 reserved_0_5 : 6;
8374 u64 red_algo_override : 2;
8383 u64 reserved_36 : 1;
8385 u64 sqm_pkt_id : 13;
8387 u64 reserved_62 : 1;
8390 struct nixx_af_tl4x_md_debug2_cn96xxp3 {
8391 u64 reserved_0_5 : 6;
8392 u64 red_algo_override : 2;
8396 u64 reserved_19_22 : 4;
8401 u64 reserved_36 : 1;
8403 u64 sqm_pkt_id : 13;
8405 u64 reserved_62 : 1;
8408 /* struct nixx_af_tl4x_md_debug2_cn96xxp1 cnf95xx; */
8411 static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a)
8412 __attribute__ ((pure, always_inline));
8413 static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a)
8415 return 0x12d0 + 0x10000 * a;
8419 * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug3
8421 * NIX AF Transmit Level 4 Meta Descriptor Debug 3 Registers Flush meta
8422 * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
8424 union nixx_af_tl4x_md_debug3 {
8426 struct nixx_af_tl4x_md_debug3_s {
8427 u64 reserved_0_36 : 37;
8429 u64 sqm_pkt_id : 13;
8431 u64 reserved_62 : 1;
8434 /* struct nixx_af_tl4x_md_debug3_s cn96xxp1; */
8435 struct nixx_af_tl4x_md_debug3_cn96xxp3 {
8436 u64 reserved_0_36 : 37;
8437 u64 reserved_37_38 : 2;
8438 u64 reserved_39_51 : 13;
8439 u64 reserved_52_61 : 10;
8440 u64 reserved_62 : 1;
8441 u64 reserved_63 : 1;
8443 /* struct nixx_af_tl4x_md_debug3_s cnf95xx; */
8446 static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a)
8447 __attribute__ ((pure, always_inline));
8448 static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a)
8450 return 0x12d8 + 0x10000 * a;
8454 * Register (RVU_PF_BAR0) nix#_af_tl4#_parent
8456 * NIX AF Transmit Level 4 Parent Registers
8458 union nixx_af_tl4x_parent {
8460 struct nixx_af_tl4x_parent_s {
8461 u64 reserved_0_15 : 16;
8463 u64 reserved_24_63 : 40;
8465 /* struct nixx_af_tl4x_parent_s cn; */
8468 static inline u64 NIXX_AF_TL4X_PARENT(u64 a)
8469 __attribute__ ((pure, always_inline));
8470 static inline u64 NIXX_AF_TL4X_PARENT(u64 a)
8472 return 0x1288 + 0x10000 * a;
8476 * Register (RVU_PF_BAR0) nix#_af_tl4#_pir
8478 * NIX AF Transmit Level 4 Peak Information Rate Registers This register
8479 * has the same bit fields as NIX_AF_TL1()_CIR.
8481 union nixx_af_tl4x_pir {
8483 struct nixx_af_tl4x_pir_s {
8485 u64 rate_mantissa : 8;
8486 u64 rate_exponent : 4;
8487 u64 rate_divider_exponent : 4;
8488 u64 reserved_17_28 : 12;
8489 u64 burst_mantissa : 8;
8490 u64 burst_exponent : 4;
8491 u64 reserved_41_63 : 23;
8493 /* struct nixx_af_tl4x_pir_s cn; */
8496 static inline u64 NIXX_AF_TL4X_PIR(u64 a)
8497 __attribute__ ((pure, always_inline));
8498 static inline u64 NIXX_AF_TL4X_PIR(u64 a)
8500 return 0x1230 + 0x10000 * a;
8504 * Register (RVU_PF_BAR0) nix#_af_tl4#_pointers
8506 * INTERNAL: NIX Transmit Level 4 Linked List Pointers Debug Register
8507 * This register has the same bit fields as NIX_AF_TL2()_POINTERS.
8509 union nixx_af_tl4x_pointers {
8511 struct nixx_af_tl4x_pointers_s {
8513 u64 reserved_9_15 : 7;
8515 u64 reserved_25_63 : 39;
8517 /* struct nixx_af_tl4x_pointers_s cn; */
8520 static inline u64 NIXX_AF_TL4X_POINTERS(u64 a)
8521 __attribute__ ((pure, always_inline));
8522 static inline u64 NIXX_AF_TL4X_POINTERS(u64 a)
8524 return 0x1260 + 0x10000 * a;
8528 * Register (RVU_PF_BAR0) nix#_af_tl4#_red
8530 * INTERNAL: NIX Transmit Level 4 Red State Debug Register This register
8531 * has the same bit fields as NIX_AF_TL3()_YELLOW.
8533 union nixx_af_tl4x_red {
8535 struct nixx_af_tl4x_red_s {
8539 u64 reserved_19_63 : 45;
8541 /* struct nixx_af_tl4x_red_s cn; */
8544 static inline u64 NIXX_AF_TL4X_RED(u64 a)
8545 __attribute__ ((pure, always_inline));
8546 static inline u64 NIXX_AF_TL4X_RED(u64 a)
8548 return 0x12b0 + 0x10000 * a;
8552 * Register (RVU_PF_BAR0) nix#_af_tl4#_sched_state
8554 * NIX AF Transmit Level 4 Scheduling Control State Registers This
8555 * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE.
8557 union nixx_af_tl4x_sched_state {
8559 struct nixx_af_tl4x_sched_state_s {
8561 u64 reserved_25_63 : 39;
8563 /* struct nixx_af_tl4x_sched_state_s cn; */
8566 static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a)
8567 __attribute__ ((pure, always_inline));
8568 static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a)
8570 return 0x1240 + 0x10000 * a;
8574 * Register (RVU_PF_BAR0) nix#_af_tl4#_schedule
8576 * NIX AF Transmit Level 4 Scheduling Control Registers This register has
8577 * the same bit fields as NIX_AF_TL2()_SCHEDULE.
8579 union nixx_af_tl4x_schedule {
8581 struct nixx_af_tl4x_schedule_s {
8582 u64 rr_quantum : 24;
8584 u64 reserved_28_63 : 36;
8586 /* struct nixx_af_tl4x_schedule_s cn; */
8589 static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a)
8590 __attribute__ ((pure, always_inline));
8591 static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a)
8593 return 0x1200 + 0x10000 * a;
8597 * Register (RVU_PF_BAR0) nix#_af_tl4#_sdp_link_cfg
8599 * NIX AF Transmit Level 4 Link Configuration Registers These registers
8600 * specify which TL4 queues transmit to and are optionally backpressured
8603 union nixx_af_tl4x_sdp_link_cfg {
8605 struct nixx_af_tl4x_sdp_link_cfg_s {
8607 u64 reserved_8_11 : 4;
8610 u64 reserved_14_63 : 50;
8612 /* struct nixx_af_tl4x_sdp_link_cfg_s cn; */
8615 static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a)
8616 __attribute__ ((pure, always_inline));
8617 static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a)
8619 return 0xb10 + 0x10000 * a;
8623 * Register (RVU_PF_BAR0) nix#_af_tl4#_shape
8625 * NIX AF Transmit Level 4 Shaping Control Registers This register has
8626 * the same bit fields as NIX_AF_TL2()_SHAPE.
8628 union nixx_af_tl4x_shape {
8630 struct nixx_af_tl4x_shape_s {
8633 u64 red_disable : 1;
8634 u64 yellow_disable : 1;
8635 u64 reserved_13_23 : 11;
8636 u64 length_disable : 1;
8637 u64 schedule_list : 2;
8638 u64 reserved_27_63 : 37;
8640 /* struct nixx_af_tl4x_shape_s cn; */
8643 static inline u64 NIXX_AF_TL4X_SHAPE(u64 a)
8644 __attribute__ ((pure, always_inline));
8645 static inline u64 NIXX_AF_TL4X_SHAPE(u64 a)
8647 return 0x1210 + 0x10000 * a;
8651 * Register (RVU_PF_BAR0) nix#_af_tl4#_shape_state
8653 * NIX AF Transmit Level 4 Shaping State Registers This register has the
8654 * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be
8655 * written during normal operation.
8657 union nixx_af_tl4x_shape_state {
8659 struct nixx_af_tl4x_shape_state_s {
8663 u64 reserved_54_63 : 10;
8665 /* struct nixx_af_tl4x_shape_state_s cn; */
8668 static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a)
8669 __attribute__ ((pure, always_inline));
8670 static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a)
8672 return 0x1250 + 0x10000 * a;
8676 * Register (RVU_PF_BAR0) nix#_af_tl4#_sw_xoff
8678 * NIX AF Transmit Level 4 Software Controlled XOFF Registers This
8679 * register has the same bit fields as NIX_AF_TL1()_SW_XOFF
8681 union nixx_af_tl4x_sw_xoff {
8683 struct nixx_af_tl4x_sw_xoff_s {
8688 u64 reserved_4_63 : 60;
8690 /* struct nixx_af_tl4x_sw_xoff_s cn; */
8693 static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a)
8694 __attribute__ ((pure, always_inline));
8695 static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a)
8697 return 0x1270 + 0x10000 * a;
8701 * Register (RVU_PF_BAR0) nix#_af_tl4#_topology
8703 * NIX AF Transmit Level 4 Topology Registers
8705 union nixx_af_tl4x_topology {
8707 struct nixx_af_tl4x_topology_s {
8710 u64 reserved_5_31 : 27;
8711 u64 prio_anchor : 9;
8712 u64 reserved_41_63 : 23;
8714 /* struct nixx_af_tl4x_topology_s cn; */
8717 static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a)
8718 __attribute__ ((pure, always_inline));
8719 static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a)
8721 return 0x1280 + 0x10000 * a;
8725 * Register (RVU_PF_BAR0) nix#_af_tl4#_yellow
8727 * INTERNAL: NIX Transmit Level 4 Yellow State Debug Register This
8728 * register has the same bit fields as NIX_AF_TL3()_YELLOW
8730 union nixx_af_tl4x_yellow {
8732 struct nixx_af_tl4x_yellow_s {
8736 u64 reserved_19_63 : 45;
8738 /* struct nixx_af_tl4x_yellow_s cn; */
8741 static inline u64 NIXX_AF_TL4X_YELLOW(u64 a)
8742 __attribute__ ((pure, always_inline));
8743 static inline u64 NIXX_AF_TL4X_YELLOW(u64 a)
8745 return 0x12a0 + 0x10000 * a;
8749 * Register (RVU_PF_BAR0) nix#_af_tl4_const
8751 * NIX AF Transmit Level 4 Constants Register This register contains
8752 * constants for software discovery.
8754 union nixx_af_tl4_const {
8756 struct nixx_af_tl4_const_s {
8758 u64 reserved_16_63 : 48;
8760 /* struct nixx_af_tl4_const_s cn; */
8763 static inline u64 NIXX_AF_TL4_CONST(void)
8764 __attribute__ ((pure, always_inline));
8765 static inline u64 NIXX_AF_TL4_CONST(void)
8771 * Register (RVU_PF_BAR0) nix#_af_tx_link#_expr_credit
8773 * INTERNAL: NIX AF Transmit Link Express Credit Registers Internal:
8774 * 802.3br frame preemption/express path is defeatured. Old definition:
8775 * These registers track credits per link for express packets that may
8776 * potentially preempt normal packets. Link index enumerated by
8779 union nixx_af_tx_linkx_expr_credit {
8781 struct nixx_af_tx_linkx_expr_credit_s {
8784 u64 cc_packet_cnt : 10;
8785 u64 cc_unit_cnt : 20;
8786 u64 reserved_32_63 : 32;
8788 /* struct nixx_af_tx_linkx_expr_credit_s cn; */
8791 static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a)
8792 __attribute__ ((pure, always_inline));
8793 static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a)
8795 return 0xa10 + 0x10000 * a;
8799 * Register (RVU_PF_BAR0) nix#_af_tx_link#_hw_xoff
8801 * NIX AF Transmit Link Hardware Controlled XOFF Registers Link index
8802 * enumerated by NIX_LINK_E.
8804 union nixx_af_tx_linkx_hw_xoff {
8806 struct nixx_af_tx_linkx_hw_xoff_s {
8809 /* struct nixx_af_tx_linkx_hw_xoff_s cn; */
8812 static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a)
8813 __attribute__ ((pure, always_inline));
8814 static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a)
8816 return 0xa30 + 0x10000 * a;
8820 * Register (RVU_PF_BAR0) nix#_af_tx_link#_norm_credit
8822 * NIX AF Transmit Link Normal Credit Registers These registers track
8823 * credits per link for normal packets sent to CGX and LBK. Link index
8824 * enumerated by NIX_LINK_E.
8826 union nixx_af_tx_linkx_norm_credit {
8828 struct nixx_af_tx_linkx_norm_credit_s {
8831 u64 cc_packet_cnt : 10;
8832 u64 cc_unit_cnt : 20;
8833 u64 reserved_32_63 : 32;
8835 /* struct nixx_af_tx_linkx_norm_credit_s cn; */
8838 static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a)
8839 __attribute__ ((pure, always_inline));
8840 static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a)
8842 return 0xa00 + 0x10000 * a;
8846 * Register (RVU_PF_BAR0) nix#_af_tx_link#_sw_xoff
8848 * INTERNAL: NIX AF Transmit Link Software Controlled XOFF Registers
8849 * Link index enumerated by NIX_LINK_E. Internal: Defeatured registers.
8850 * Software should instead use NIX_AF_TL3()_SW_XOFF registers when
8851 * NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is set and NIX_AF_TL2()_SW_XOFF
8852 * registers when NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is clear.
8854 union nixx_af_tx_linkx_sw_xoff {
8856 struct nixx_af_tx_linkx_sw_xoff_s {
8859 /* struct nixx_af_tx_linkx_sw_xoff_s cn; */
8862 static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a)
8863 __attribute__ ((pure, always_inline));
8864 static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a)
8866 return 0xa20 + 0x10000 * a;
8870 * Register (RVU_PF_BAR0) nix#_af_tx_mcast#
8872 * NIX AF Transmit Multicast Registers These registers access transmit
8873 * multicast table entries used to specify multicast replication lists.
8874 * Each list consists of linked entries with [EOL] = 1 in the last entry.
8875 * A transmit packet is multicast when the action returned by NPC has
8876 * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. NIX_TX_ACTION_S[INDEX]
8877 * points to the start of the multicast replication list, and [EOL] = 1
8878 * indicates the end of list.
8880 union nixx_af_tx_mcastx {
8882 struct nixx_af_tx_mcastx_s {
8885 u64 reserved_13_15 : 3;
8887 u64 reserved_32_63 : 32;
8889 /* struct nixx_af_tx_mcastx_s cn; */
8892 static inline u64 NIXX_AF_TX_MCASTX(u64 a)
8893 __attribute__ ((pure, always_inline));
8894 static inline u64 NIXX_AF_TX_MCASTX(u64 a)
8896 return 0x1900 + 0x8000 * a;
8900 * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_config
8902 * NIX AF Transmit NPC Response Capture Configuration Register Configures
8903 * the NPC response capture logic for transmit packets. When enabled,
8904 * allows NPC responses for selected packets to be captured in
8905 * NIX_AF_TX_NPC_CAPTURE_INFO and NIX_AF_TX_NPC_CAPTURE_RESP().
8907 union nixx_af_tx_npc_capture_config {
8909 struct nixx_af_tx_npc_capture_config_s {
8912 u64 lso_segnum_en : 1;
8916 u64 reserved_6_11 : 6;
8922 /* struct nixx_af_tx_npc_capture_config_s cn; */
8925 static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void)
8926 __attribute__ ((pure, always_inline));
8927 static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void)
8933 * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_info
8935 * NIX AF Transmit NPC Response Capture Information Register This
8936 * register contains captured NPC response information for a transmit
8937 * packet. See NIX_AF_TX_NPC_CAPTURE_CONFIG.
8939 union nixx_af_tx_npc_capture_info {
8941 struct nixx_af_tx_npc_capture_info_s {
8943 u64 reserved_1_11 : 11;
8949 /* struct nixx_af_tx_npc_capture_info_s cn; */
8952 static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void)
8953 __attribute__ ((pure, always_inline));
8954 static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void)
8960 * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_resp#
8962 * NIX AF Transmit NPC Capture Response Registers These registers contain
8963 * the captured NPC response for a transmit packet when
8964 * NIX_AF_TX_NPC_CAPTURE_INFO[VLD] is set. See also
8965 * NIX_AF_TX_NPC_CAPTURE_CONFIG.
8967 union nixx_af_tx_npc_capture_respx {
8969 struct nixx_af_tx_npc_capture_respx_s {
8972 /* struct nixx_af_tx_npc_capture_respx_s cn; */
8975 static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a)
8976 __attribute__ ((pure, always_inline));
8977 static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a)
8979 return 0x680 + 8 * a;
8983 * Register (RVU_PF_BAR0) nix#_af_tx_tstmp_cfg
8985 * NIX AF Transmit Timestamp Configuration Register
8987 union nixx_af_tx_tstmp_cfg {
8989 struct nixx_af_tx_tstmp_cfg_s {
8990 u64 tstmp_wd_period : 4;
8991 u64 reserved_4_7 : 4;
8993 u64 reserved_24_63 : 40;
8995 /* struct nixx_af_tx_tstmp_cfg_s cn; */
8998 static inline u64 NIXX_AF_TX_TSTMP_CFG(void)
8999 __attribute__ ((pure, always_inline));
9000 static inline u64 NIXX_AF_TX_TSTMP_CFG(void)
9006 * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_ctl
9008 * NIX AF Transmit Vtag Definition Control Registers The transmit Vtag
9009 * definition table specifies Vtag layers (e.g. VLAN, E-TAG) to
9010 * optionally insert or replace in the TX packet header. Indexed by
9011 * NIX_TX_VTAG_ACTION_S[VTAG*_DEF].
9013 union nixx_af_tx_vtag_defx_ctl {
9015 struct nixx_af_tx_vtag_defx_ctl_s {
9017 u64 reserved_1_63 : 63;
9019 /* struct nixx_af_tx_vtag_defx_ctl_s cn; */
9022 static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a)
9023 __attribute__ ((pure, always_inline));
9024 static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a)
9026 return 0x1a00 + 0x10000 * a;
9030 * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_data
9032 * NIX AF Transmit Vtag Definition Data Registers See
9033 * NIX_AF_TX_VTAG_DEF()_CTL.
9035 union nixx_af_tx_vtag_defx_data {
9037 struct nixx_af_tx_vtag_defx_data_s {
9040 /* struct nixx_af_tx_vtag_defx_data_s cn; */
9043 static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a)
9044 __attribute__ ((pure, always_inline));
9045 static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a)
9047 return 0x1a10 + 0x10000 * a;
9051 * Register (RVU_PFVF_BAR2) nix#_lf_cfg
9053 * NIX LF Configuration Register
9057 struct nixx_lf_cfg_s {
9058 u64 tcp_timer_int_ena : 1;
9059 u64 reserved_1_63 : 63;
9061 /* struct nixx_lf_cfg_s cn; */
9064 static inline u64 NIXX_LF_CFG(void)
9065 __attribute__ ((pure, always_inline));
9066 static inline u64 NIXX_LF_CFG(void)
9072 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_cnt
9074 * NIX LF Completion Interrupt Count Registers
9076 union nixx_lf_cintx_cnt {
9078 struct nixx_lf_cintx_cnt_s {
9081 u64 reserved_48_63 : 16;
9083 /* struct nixx_lf_cintx_cnt_s cn; */
9086 static inline u64 NIXX_LF_CINTX_CNT(u64 a)
9087 __attribute__ ((pure, always_inline));
9088 static inline u64 NIXX_LF_CINTX_CNT(u64 a)
9090 return 0xd00 + 0x1000 * a;
9094 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1c
9096 * NIX LF Completion Interrupt Enable Clear Registers This register
9097 * clears interrupt enable bits.
9099 union nixx_lf_cintx_ena_w1c {
9101 struct nixx_lf_cintx_ena_w1c_s {
9103 u64 reserved_1_63 : 63;
9105 /* struct nixx_lf_cintx_ena_w1c_s cn; */
9108 static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a)
9109 __attribute__ ((pure, always_inline));
9110 static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a)
9112 return 0xd50 + 0x1000 * a;
9116 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1s
9118 * NIX LF Completion Interrupt Enable Set Registers This register sets
9119 * interrupt enable bits.
9121 union nixx_lf_cintx_ena_w1s {
9123 struct nixx_lf_cintx_ena_w1s_s {
9125 u64 reserved_1_63 : 63;
9127 /* struct nixx_lf_cintx_ena_w1s_s cn; */
9130 static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a)
9131 __attribute__ ((pure, always_inline));
9132 static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a)
9134 return 0xd40 + 0x1000 * a;
9138 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int
9140 * NIX LF Completion Interrupt Registers
9142 union nixx_lf_cintx_int {
9144 struct nixx_lf_cintx_int_s {
9146 u64 reserved_1_63 : 63;
9148 /* struct nixx_lf_cintx_int_s cn; */
9151 static inline u64 NIXX_LF_CINTX_INT(u64 a)
9152 __attribute__ ((pure, always_inline));
9153 static inline u64 NIXX_LF_CINTX_INT(u64 a)
9155 return 0xd20 + 0x1000 * a;
9159 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int_w1s
9161 * NIX LF Completion Interrupt Set Registers This register sets interrupt
9164 union nixx_lf_cintx_int_w1s {
9166 struct nixx_lf_cintx_int_w1s_s {
9168 u64 reserved_1_63 : 63;
9170 /* struct nixx_lf_cintx_int_w1s_s cn; */
9173 static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a)
9174 __attribute__ ((pure, always_inline));
9175 static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a)
9177 return 0xd30 + 0x1000 * a;
9181 * Register (RVU_PFVF_BAR2) nix#_lf_cint#_wait
9183 * NIX LF Completion Interrupt Count Registers
9185 union nixx_lf_cintx_wait {
9187 struct nixx_lf_cintx_wait_s {
9188 u64 ecount_wait : 32;
9189 u64 qcount_wait : 16;
9191 u64 reserved_56_63 : 8;
9193 /* struct nixx_lf_cintx_wait_s cn; */
9196 static inline u64 NIXX_LF_CINTX_WAIT(u64 a)
9197 __attribute__ ((pure, always_inline));
9198 static inline u64 NIXX_LF_CINTX_WAIT(u64 a)
9200 return 0xd10 + 0x1000 * a;
9204 * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_door
9206 * NIX LF CQ Doorbell Operation Register A write to this register
9207 * dequeues CQEs from a CQ ring within the LF. A read is RAZ. RSL
9208 * accesses to this register are RAZ/WI.
9210 union nixx_lf_cq_op_door {
9212 struct nixx_lf_cq_op_door_s {
9214 u64 reserved_16_31 : 16;
9216 u64 reserved_52_63 : 12;
9218 /* struct nixx_lf_cq_op_door_s cn; */
9221 static inline u64 NIXX_LF_CQ_OP_DOOR(void)
9222 __attribute__ ((pure, always_inline));
9223 static inline u64 NIXX_LF_CQ_OP_DOOR(void)
9229 * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_int
9231 * NIX LF Completion Queue Interrupt Operation Register A 64-bit atomic
9232 * load-and-add to this register reads CQ interrupts and interrupt
9233 * enables. A write optionally sets or clears interrupts and interrupt
9234 * enables. A read is RAZ. RSL accesses to this register are RAZ/WI.
9236 union nixx_lf_cq_op_int {
9238 struct nixx_lf_cq_op_int_s {
9240 u64 cq_err_int_ena : 8;
9241 u64 reserved_16_41 : 26;
9246 /* struct nixx_lf_cq_op_int_s cn; */
9249 static inline u64 NIXX_LF_CQ_OP_INT(void)
9250 __attribute__ ((pure, always_inline));
9251 static inline u64 NIXX_LF_CQ_OP_INT(void)
9257 * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_status
9259 * NIX LF Completion Queue Status Operation Register A 64-bit atomic
9260 * load-and-add to this register reads NIX_CQ_CTX_S[HEAD,TAIL]. The
9261 * atomic write data has format NIX_OP_Q_WDATA_S and selects the CQ
9262 * within LF. All other accesses to this register (e.g. reads and
9263 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
9265 union nixx_lf_cq_op_status {
9267 struct nixx_lf_cq_op_status_s {
9270 u64 reserved_40_45 : 6;
9272 u64 reserved_47_62 : 16;
9275 /* struct nixx_lf_cq_op_status_s cn; */
9278 static inline u64 NIXX_LF_CQ_OP_STATUS(void)
9279 __attribute__ ((pure, always_inline));
9280 static inline u64 NIXX_LF_CQ_OP_STATUS(void)
9286 * Register (RVU_PFVF_BAR2) nix#_lf_err_int
9288 * NIX LF Error Interrupt Register
9290 union nixx_lf_err_int {
9292 struct nixx_lf_err_int_s {
9294 u64 sq_ctx_fault : 1;
9295 u64 rq_ctx_fault : 1;
9296 u64 cq_ctx_fault : 1;
9299 u64 ipsec_dyno_fault : 1;
9300 u64 sq_disabled : 1;
9302 u64 send_jump_fault : 1;
9303 u64 send_sg_fault : 1;
9304 u64 rq_disabled : 1;
9306 u64 rx_wqe_fault : 1;
9308 u64 reserved_15_19 : 5;
9310 u64 reserved_21_23 : 3;
9311 u64 cq_disabled : 1;
9313 u64 reserved_26_27 : 2;
9316 u64 reserved_30_63 : 34;
9318 /* struct nixx_lf_err_int_s cn; */
9321 static inline u64 NIXX_LF_ERR_INT(void)
9322 __attribute__ ((pure, always_inline));
9323 static inline u64 NIXX_LF_ERR_INT(void)
9329 * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1c
9331 * NIX LF Error Interrupt Enable Clear Register This register clears
9332 * interrupt enable bits.
9334 union nixx_lf_err_int_ena_w1c {
9336 struct nixx_lf_err_int_ena_w1c_s {
9338 u64 sq_ctx_fault : 1;
9339 u64 rq_ctx_fault : 1;
9340 u64 cq_ctx_fault : 1;
9343 u64 ipsec_dyno_fault : 1;
9344 u64 sq_disabled : 1;
9346 u64 send_jump_fault : 1;
9347 u64 send_sg_fault : 1;
9348 u64 rq_disabled : 1;
9350 u64 rx_wqe_fault : 1;
9352 u64 reserved_15_19 : 5;
9354 u64 reserved_21_23 : 3;
9355 u64 cq_disabled : 1;
9357 u64 reserved_26_27 : 2;
9360 u64 reserved_30_63 : 34;
9362 /* struct nixx_lf_err_int_ena_w1c_s cn; */
9365 static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void)
9366 __attribute__ ((pure, always_inline));
9367 static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void)
9373 * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1s
9375 * NIX LF Error Interrupt Enable Set Register This register sets
9376 * interrupt enable bits.
9378 union nixx_lf_err_int_ena_w1s {
9380 struct nixx_lf_err_int_ena_w1s_s {
9382 u64 sq_ctx_fault : 1;
9383 u64 rq_ctx_fault : 1;
9384 u64 cq_ctx_fault : 1;
9387 u64 ipsec_dyno_fault : 1;
9388 u64 sq_disabled : 1;
9390 u64 send_jump_fault : 1;
9391 u64 send_sg_fault : 1;
9392 u64 rq_disabled : 1;
9394 u64 rx_wqe_fault : 1;
9396 u64 reserved_15_19 : 5;
9398 u64 reserved_21_23 : 3;
9399 u64 cq_disabled : 1;
9401 u64 reserved_26_27 : 2;
9404 u64 reserved_30_63 : 34;
9406 /* struct nixx_lf_err_int_ena_w1s_s cn; */
9409 static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void)
9410 __attribute__ ((pure, always_inline));
9411 static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void)
9417 * Register (RVU_PFVF_BAR2) nix#_lf_err_int_w1s
9419 * NIX LF Error Interrupt Set Register This register sets interrupt bits.
9421 union nixx_lf_err_int_w1s {
9423 struct nixx_lf_err_int_w1s_s {
9425 u64 sq_ctx_fault : 1;
9426 u64 rq_ctx_fault : 1;
9427 u64 cq_ctx_fault : 1;
9430 u64 ipsec_dyno_fault : 1;
9431 u64 sq_disabled : 1;
9433 u64 send_jump_fault : 1;
9434 u64 send_sg_fault : 1;
9435 u64 rq_disabled : 1;
9437 u64 rx_wqe_fault : 1;
9439 u64 reserved_15_19 : 5;
9441 u64 reserved_21_23 : 3;
9442 u64 cq_disabled : 1;
9444 u64 reserved_26_27 : 2;
9447 u64 reserved_30_63 : 34;
9449 /* struct nixx_lf_err_int_w1s_s cn; */
9452 static inline u64 NIXX_LF_ERR_INT_W1S(void)
9453 __attribute__ ((pure, always_inline));
9454 static inline u64 NIXX_LF_ERR_INT_W1S(void)
9460 * Register (RVU_PFVF_BAR2) nix#_lf_gint
9462 * NIX LF General Interrupt Register
9464 union nixx_lf_gint {
9466 struct nixx_lf_gint_s {
9469 u64 reserved_2_63 : 62;
9471 /* struct nixx_lf_gint_s cn; */
9474 static inline u64 NIXX_LF_GINT(void)
9475 __attribute__ ((pure, always_inline));
9476 static inline u64 NIXX_LF_GINT(void)
9482 * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1c
9484 * NIX LF General Interrupt Enable Clear Register This register clears
9485 * interrupt enable bits.
9487 union nixx_lf_gint_ena_w1c {
9489 struct nixx_lf_gint_ena_w1c_s {
9492 u64 reserved_2_63 : 62;
9494 /* struct nixx_lf_gint_ena_w1c_s cn; */
9497 static inline u64 NIXX_LF_GINT_ENA_W1C(void)
9498 __attribute__ ((pure, always_inline));
9499 static inline u64 NIXX_LF_GINT_ENA_W1C(void)
9505 * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1s
9507 * NIX LF General Interrupt Enable Set Register This register sets
9508 * interrupt enable bits.
9510 union nixx_lf_gint_ena_w1s {
9512 struct nixx_lf_gint_ena_w1s_s {
9515 u64 reserved_2_63 : 62;
9517 /* struct nixx_lf_gint_ena_w1s_s cn; */
9520 static inline u64 NIXX_LF_GINT_ENA_W1S(void)
9521 __attribute__ ((pure, always_inline));
9522 static inline u64 NIXX_LF_GINT_ENA_W1S(void)
9528 * Register (RVU_PFVF_BAR2) nix#_lf_gint_w1s
9530 * NIX LF General Interrupt Set Register This register sets interrupt
9533 union nixx_lf_gint_w1s {
9535 struct nixx_lf_gint_w1s_s {
9538 u64 reserved_2_63 : 62;
9540 /* struct nixx_lf_gint_w1s_s cn; */
9543 static inline u64 NIXX_LF_GINT_W1S(void)
9544 __attribute__ ((pure, always_inline));
9545 static inline u64 NIXX_LF_GINT_W1S(void)
9551 * Register (RVU_PFVF_BAR2) nix#_lf_mnq_err_dbg
9553 * NIX LF Meta-descriptor Enqueue Error Debug Register This register
9554 * captures debug info for an error detected during send meta-descriptor
9555 * enqueue from an SQ to an SMQ. Hardware sets [VALID] when the debug
9556 * info is captured, and subsequent errors are not captured until
9557 * software clears [VALID] by writing a one to it.
9559 union nixx_lf_mnq_err_dbg {
9561 struct nixx_lf_mnq_err_dbg_s {
9566 u64 reserved_45_63 : 19;
9568 /* struct nixx_lf_mnq_err_dbg_s cn; */
9571 static inline u64 NIXX_LF_MNQ_ERR_DBG(void)
9572 __attribute__ ((pure, always_inline));
9573 static inline u64 NIXX_LF_MNQ_ERR_DBG(void)
9579 * Register (RVU_PFVF_BAR2) nix#_lf_op_ipsec_dyno_cnt
9581 * INTERNAL: NIX LF IPSEC Dynamic Ordering Counter Operation Register
9582 * Internal: Not used; no IPSEC fast-path. All accesses are RAZ/WI.
9584 union nixx_lf_op_ipsec_dyno_cnt {
9586 struct nixx_lf_op_ipsec_dyno_cnt_s {
9588 u64 reserved_32_46 : 15;
9593 /* struct nixx_lf_op_ipsec_dyno_cnt_s cn; */
9596 static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void)
9597 __attribute__ ((pure, always_inline));
9598 static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void)
9604 * Register (RVU_PFVF_BAR2) nix#_lf_op_send#
9606 * NIX LF Send Operation Registers An LMTST (or large store from CPT) to
9607 * this address enqueues one or more SQEs to a send queue.
9608 * NIX_SEND_HDR_S[SQ] in the first SQE selects the send queue.The maximum
9609 * size of each SQE is specified by NIX_SQ_CTX_S[MAX_SQE_SIZE]. A read
9610 * to this address is RAZ. An RSL access to this address will fault.
9611 * The endianness of the instruction write data is controlled by
9612 * NIX_AF_LF()_CFG[BE]. When a NIX_SEND_JUMP_S is not present in the
9613 * SQE, the SQE consists of the entire send descriptor. When a
9614 * NIX_SEND_JUMP_S is present in the SQE, the SQE must contain exactly
9615 * the portion of the send descriptor up to and including the
9616 * NIX_SEND_JUMP_S, and the remainder of the send descriptor must be at
9617 * LF IOVA NIX_SEND_JUMP_S[ADDR] in LLC/DRAM. Software must ensure that
9618 * all LLC/DRAM locations that will be referenced by NIX while processing
9619 * this descriptor, including all packet data and post-jump
9620 * subdescriptors contain the latest updates before issuing the LMTST. A
9621 * DMB instruction may be required prior to the LMTST to ensure this. A
9622 * DMB following the LMTST may be useful if SQ descriptor ordering
9623 * matters and more than one CPU core is simultaneously enqueueing to the
9626 union nixx_lf_op_sendx {
9628 struct nixx_lf_op_sendx_s {
9631 /* struct nixx_lf_op_sendx_s cn; */
9634 static inline u64 NIXX_LF_OP_SENDX(u64 a)
9635 __attribute__ ((pure, always_inline));
9636 static inline u64 NIXX_LF_OP_SENDX(u64 a)
9638 return 0x800 + 8 * a;
9642 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_cnt
9644 * NIX LF Queue Interrupt Count Registers
9646 union nixx_lf_qintx_cnt {
9648 struct nixx_lf_qintx_cnt_s {
9650 u64 reserved_22_63 : 42;
9652 /* struct nixx_lf_qintx_cnt_s cn; */
9655 static inline u64 NIXX_LF_QINTX_CNT(u64 a)
9656 __attribute__ ((pure, always_inline));
9657 static inline u64 NIXX_LF_QINTX_CNT(u64 a)
9659 return 0xc00 + 0x1000 * a;
9663 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1c
9665 * NIX LF Queue Interrupt Enable Clear Registers This register clears
9666 * interrupt enable bits.
9668 union nixx_lf_qintx_ena_w1c {
9670 struct nixx_lf_qintx_ena_w1c_s {
9672 u64 reserved_1_63 : 63;
9674 /* struct nixx_lf_qintx_ena_w1c_s cn; */
9677 static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a)
9678 __attribute__ ((pure, always_inline));
9679 static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a)
9681 return 0xc30 + 0x1000 * a;
9685 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1s
9687 * NIX LF Queue Interrupt Enable Set Registers This register sets
9688 * interrupt enable bits.
9690 union nixx_lf_qintx_ena_w1s {
9692 struct nixx_lf_qintx_ena_w1s_s {
9694 u64 reserved_1_63 : 63;
9696 /* struct nixx_lf_qintx_ena_w1s_s cn; */
9699 static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a)
9700 __attribute__ ((pure, always_inline));
9701 static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a)
9703 return 0xc20 + 0x1000 * a;
9707 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int
9709 * NIX LF Queue Interrupt Registers
9711 union nixx_lf_qintx_int {
9713 struct nixx_lf_qintx_int_s {
9715 u64 reserved_1_63 : 63;
9717 /* struct nixx_lf_qintx_int_s cn; */
9720 static inline u64 NIXX_LF_QINTX_INT(u64 a)
9721 __attribute__ ((pure, always_inline));
9722 static inline u64 NIXX_LF_QINTX_INT(u64 a)
9724 return 0xc10 + 0x1000 * a;
9728 * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int_w1s
9730 * INTERNAL: NIX LF Queue Interrupt Set Registers
9732 union nixx_lf_qintx_int_w1s {
9734 struct nixx_lf_qintx_int_w1s_s {
9736 u64 reserved_1_63 : 63;
9738 /* struct nixx_lf_qintx_int_w1s_s cn; */
9741 static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a)
9742 __attribute__ ((pure, always_inline));
9743 static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a)
9745 return 0xc18 + 0x1000 * a;
9749 * Register (RVU_PFVF_BAR2) nix#_lf_ras
9751 * NIX LF RAS Interrupt Register
9755 struct nixx_lf_ras_s {
9757 u64 sq_ctx_poison : 1;
9758 u64 rq_ctx_poison : 1;
9759 u64 cq_ctx_poison : 1;
9761 u64 rsse_poison : 1;
9762 u64 ipsec_dyno_poison : 1;
9763 u64 send_jump_poison : 1;
9764 u64 send_sg_poison : 1;
9765 u64 qint_poison : 1;
9766 u64 cint_poison : 1;
9767 u64 reserved_11_63 : 53;
9769 /* struct nixx_lf_ras_s cn; */
9772 static inline u64 NIXX_LF_RAS(void)
9773 __attribute__ ((pure, always_inline));
9774 static inline u64 NIXX_LF_RAS(void)
9780 * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1c
9782 * NIX LF RAS Interrupt Enable Clear Register This register clears
9783 * interrupt enable bits.
9785 union nixx_lf_ras_ena_w1c {
9787 struct nixx_lf_ras_ena_w1c_s {
9789 u64 sq_ctx_poison : 1;
9790 u64 rq_ctx_poison : 1;
9791 u64 cq_ctx_poison : 1;
9793 u64 rsse_poison : 1;
9794 u64 ipsec_dyno_poison : 1;
9795 u64 send_jump_poison : 1;
9796 u64 send_sg_poison : 1;
9797 u64 qint_poison : 1;
9798 u64 cint_poison : 1;
9799 u64 reserved_11_63 : 53;
9801 /* struct nixx_lf_ras_ena_w1c_s cn; */
9804 static inline u64 NIXX_LF_RAS_ENA_W1C(void)
9805 __attribute__ ((pure, always_inline));
9806 static inline u64 NIXX_LF_RAS_ENA_W1C(void)
9812 * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1s
9814 * NIX LF RAS Interrupt Enable Set Register This register sets interrupt
9817 union nixx_lf_ras_ena_w1s {
9819 struct nixx_lf_ras_ena_w1s_s {
9821 u64 sq_ctx_poison : 1;
9822 u64 rq_ctx_poison : 1;
9823 u64 cq_ctx_poison : 1;
9825 u64 rsse_poison : 1;
9826 u64 ipsec_dyno_poison : 1;
9827 u64 send_jump_poison : 1;
9828 u64 send_sg_poison : 1;
9829 u64 qint_poison : 1;
9830 u64 cint_poison : 1;
9831 u64 reserved_11_63 : 53;
9833 /* struct nixx_lf_ras_ena_w1s_s cn; */
9836 static inline u64 NIXX_LF_RAS_ENA_W1S(void)
9837 __attribute__ ((pure, always_inline));
9838 static inline u64 NIXX_LF_RAS_ENA_W1S(void)
9844 * Register (RVU_PFVF_BAR2) nix#_lf_ras_w1s
9846 * NIX LF RAS Interrupt Set Register This register sets interrupt bits.
9848 union nixx_lf_ras_w1s {
9850 struct nixx_lf_ras_w1s_s {
9852 u64 sq_ctx_poison : 1;
9853 u64 rq_ctx_poison : 1;
9854 u64 cq_ctx_poison : 1;
9856 u64 rsse_poison : 1;
9857 u64 ipsec_dyno_poison : 1;
9858 u64 send_jump_poison : 1;
9859 u64 send_sg_poison : 1;
9860 u64 qint_poison : 1;
9861 u64 cint_poison : 1;
9862 u64 reserved_11_63 : 53;
9864 /* struct nixx_lf_ras_w1s_s cn; */
9867 static inline u64 NIXX_LF_RAS_W1S(void)
9868 __attribute__ ((pure, always_inline));
9869 static inline u64 NIXX_LF_RAS_W1S(void)
9875 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_octs
9877 * NIX LF Receive Queue Dropped Octets Operation Register A 64-bit atomic
9878 * load-and-add to this register reads NIX_RQ_CTX_S[DROP_OCTS]. The
9879 * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ
9880 * within LF. All other accesses to this register (e.g. reads and
9881 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
9883 union nixx_lf_rq_op_drop_octs {
9885 struct nixx_lf_rq_op_drop_octs_s {
9887 u64 reserved_48_62 : 15;
9890 /* struct nixx_lf_rq_op_drop_octs_s cn; */
9893 static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void)
9894 __attribute__ ((pure, always_inline));
9895 static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void)
9901 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_pkts
9903 * NIX LF Receive Queue Dropped Packets Operation Register A 64-bit
9904 * atomic load-and-add to this register reads NIX_RQ_CTX_S[DROP_PKTS].
9905 * The atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ
9906 * within LF. All other accesses to this register (e.g. reads and
9907 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
9909 union nixx_lf_rq_op_drop_pkts {
9911 struct nixx_lf_rq_op_drop_pkts_s {
9913 u64 reserved_48_62 : 15;
9916 /* struct nixx_lf_rq_op_drop_pkts_s cn; */
9919 static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void)
9920 __attribute__ ((pure, always_inline));
9921 static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void)
9927 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_int
9929 * NIX LF Receive Queue Interrupt Operation Register A 64-bit atomic
9930 * load-and-add to this register reads RQ interrupts and interrupt
9931 * enables. A 64-bit write optionally sets or clears interrupts and
9932 * interrupt enables. All other accesses to this register (e.g. reads,
9933 * 128-bit accesses) are RAZ/WI. RSL accesses to this register are
9936 union nixx_lf_rq_op_int {
9938 struct nixx_lf_rq_op_int_s {
9941 u64 reserved_16_41 : 26;
9946 /* struct nixx_lf_rq_op_int_s cn; */
9949 static inline u64 NIXX_LF_RQ_OP_INT(void)
9950 __attribute__ ((pure, always_inline));
9951 static inline u64 NIXX_LF_RQ_OP_INT(void)
9957 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_octs
9959 * NIX LF Receive Queue Octets Operation Register A 64-bit atomic load-
9960 * and-add to this register reads NIX_RQ_CTX_S[OCTS]. The atomic write
9961 * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All
9962 * other accesses to this register (e.g. reads and writes) are RAZ/WI.
9963 * RSL accesses to this register are RAZ/WI.
9965 union nixx_lf_rq_op_octs {
9967 struct nixx_lf_rq_op_octs_s {
9969 u64 reserved_48_62 : 15;
9972 /* struct nixx_lf_rq_op_octs_s cn; */
9975 static inline u64 NIXX_LF_RQ_OP_OCTS(void)
9976 __attribute__ ((pure, always_inline));
9977 static inline u64 NIXX_LF_RQ_OP_OCTS(void)
9983 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_pkts
9985 * NIX LF Receive Queue Packets Operation Register A 64-bit atomic load-
9986 * and-add to this register reads NIX_RQ_CTX_S[PKTS]. The atomic write
9987 * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All
9988 * other accesses to this register (e.g. reads and writes) are RAZ/WI.
9989 * RSL accesses to this register are RAZ/WI.
9991 union nixx_lf_rq_op_pkts {
9993 struct nixx_lf_rq_op_pkts_s {
9995 u64 reserved_48_62 : 15;
9998 /* struct nixx_lf_rq_op_pkts_s cn; */
10001 static inline u64 NIXX_LF_RQ_OP_PKTS(void)
10002 __attribute__ ((pure, always_inline));
10003 static inline u64 NIXX_LF_RQ_OP_PKTS(void)
10009 * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_re_pkts
10011 * NIX LF Receive Queue Errored Packets Operation Register A 64-bit
10012 * atomic load-and-add to this register reads NIX_RQ_CTX_S[RE_PKTS]. The
10013 * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ
10014 * within LF. All other accesses to this register (e.g. reads and
10015 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
10017 union nixx_lf_rq_op_re_pkts {
10019 struct nixx_lf_rq_op_re_pkts_s {
10021 u64 reserved_48_62 : 15;
10024 /* struct nixx_lf_rq_op_re_pkts_s cn; */
10027 static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void)
10028 __attribute__ ((pure, always_inline));
10029 static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void)
10035 * Register (RVU_PFVF_BAR2) nix#_lf_rx_secret#
10037 * NIX LF Receive Secret Key Registers
10039 union nixx_lf_rx_secretx {
10041 struct nixx_lf_rx_secretx_s {
10044 /* struct nixx_lf_rx_secretx_s cn; */
10047 static inline u64 NIXX_LF_RX_SECRETX(u64 a)
10048 __attribute__ ((pure, always_inline));
10049 static inline u64 NIXX_LF_RX_SECRETX(u64 a)
10055 * Register (RVU_PFVF_BAR2) nix#_lf_rx_stat#
10057 * NIX LF Receive Statistics Registers The last dimension indicates which
10058 * statistic, and is enumerated by NIX_STAT_LF_RX_E.
10060 union nixx_lf_rx_statx {
10062 struct nixx_lf_rx_statx_s {
10064 u64 reserved_48_63 : 16;
10066 /* struct nixx_lf_rx_statx_s cn; */
10069 static inline u64 NIXX_LF_RX_STATX(u64 a)
10070 __attribute__ ((pure, always_inline));
10071 static inline u64 NIXX_LF_RX_STATX(u64 a)
10073 return 0x400 + 8 * a;
10077 * Register (RVU_PFVF_BAR2) nix#_lf_send_err_dbg
10079 * NIX LF Send Error Debug Register This register captures debug info an
10080 * error detected on packet send after a meta-descriptor is granted by
10081 * PSE. Hardware sets [VALID] when the debug info is captured, and
10082 * subsequent errors are not captured until software clears [VALID] by
10083 * writing a one to it.
10085 union nixx_lf_send_err_dbg {
10087 struct nixx_lf_send_err_dbg_s {
10092 u64 reserved_45_63 : 19;
10094 /* struct nixx_lf_send_err_dbg_s cn; */
10097 static inline u64 NIXX_LF_SEND_ERR_DBG(void)
10098 __attribute__ ((pure, always_inline));
10099 static inline u64 NIXX_LF_SEND_ERR_DBG(void)
10105 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_octs
10107 * NIX LF Send Queue Dropped Octets Operation Register A 64-bit atomic
10108 * load-and-add to this register reads NIX_SQ_CTX_S[DROP_OCTS]. The
10109 * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ
10110 * within LF. All other accesses to this register (e.g. reads and
10111 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
10113 union nixx_lf_sq_op_drop_octs {
10115 struct nixx_lf_sq_op_drop_octs_s {
10117 u64 reserved_48_62 : 15;
10120 /* struct nixx_lf_sq_op_drop_octs_s cn; */
10123 static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void)
10124 __attribute__ ((pure, always_inline));
10125 static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void)
10131 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_pkts
10133 * NIX LF Send Queue Dropped Packets Operation Register A 64-bit atomic
10134 * load-and-add to this register reads NIX_SQ_CTX_S[DROP_PKTS]. The
10135 * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ
10136 * within LF. All other accesses to this register (e.g. reads and
10137 * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
10139 union nixx_lf_sq_op_drop_pkts {
10141 struct nixx_lf_sq_op_drop_pkts_s {
10143 u64 reserved_48_62 : 15;
10146 /* struct nixx_lf_sq_op_drop_pkts_s cn; */
10149 static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void)
10150 __attribute__ ((pure, always_inline));
10151 static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void)
10157 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_err_dbg
10159 * NIX LF SQ Operation Error Debug Register This register captures debug
10160 * info for an error detected on LMT store to NIX_LF_OP_SEND() or when a
10161 * NIX_LF_SQ_OP_* register is accessed. Hardware sets [VALID] when the
10162 * debug info is captured, and subsequent errors are not captured until
10163 * software clears [VALID] by writing a one to it.
10165 union nixx_lf_sq_op_err_dbg {
10167 struct nixx_lf_sq_op_err_dbg_s {
10172 u64 reserved_45_63 : 19;
10174 /* struct nixx_lf_sq_op_err_dbg_s cn; */
10177 static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void)
10178 __attribute__ ((pure, always_inline));
10179 static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void)
10185 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_int
10187 * NIX LF Send Queue Interrupt Operation Register A 64-bit atomic load-
10188 * and-add to this register reads SQ interrupts, interrupt enables and
10189 * XOFF status. A write optionally sets or clears interrupts, interrupt
10190 * enables and XOFF status. A read is RAZ. RSL accesses to this register
10193 union nixx_lf_sq_op_int {
10195 struct nixx_lf_sq_op_int_s {
10197 u64 sq_int_ena : 8;
10199 u64 reserved_17_41 : 25;
10204 /* struct nixx_lf_sq_op_int_s cn; */
10207 static inline u64 NIXX_LF_SQ_OP_INT(void)
10208 __attribute__ ((pure, always_inline));
10209 static inline u64 NIXX_LF_SQ_OP_INT(void)
10215 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_octs
10217 * NIX LF Send Queue Octets Operation Register A 64-bit atomic load-and-
10218 * add to this register reads NIX_SQ_CTX_S[OCTS]. The atomic write data
10219 * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other
10220 * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL
10221 * accesses to this register are RAZ/WI.
10223 union nixx_lf_sq_op_octs {
10225 struct nixx_lf_sq_op_octs_s {
10227 u64 reserved_48_62 : 15;
10230 /* struct nixx_lf_sq_op_octs_s cn; */
10233 static inline u64 NIXX_LF_SQ_OP_OCTS(void)
10234 __attribute__ ((pure, always_inline));
10235 static inline u64 NIXX_LF_SQ_OP_OCTS(void)
10241 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_pkts
10243 * NIX LF Send Queue Packets Operation Register A 64-bit atomic load-and-
10244 * add to this register reads NIX_SQ_CTX_S[PKTS]. The atomic write data
10245 * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other
10246 * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL
10247 * accesses to this register are RAZ/WI.
10249 union nixx_lf_sq_op_pkts {
10251 struct nixx_lf_sq_op_pkts_s {
10253 u64 reserved_48_62 : 15;
10256 /* struct nixx_lf_sq_op_pkts_s cn; */
10259 static inline u64 NIXX_LF_SQ_OP_PKTS(void)
10260 __attribute__ ((pure, always_inline));
10261 static inline u64 NIXX_LF_SQ_OP_PKTS(void)
10267 * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_status
10269 * NIX LF Send Queue Status Operation Register A 64-bit atomic load-and-
10270 * add to this register reads status fields in NIX_SQ_CTX_S. The atomic
10271 * write data has format NIX_OP_Q_WDATA_S and selects the SQ within LF.
10272 * Completion of the load-and-add operation also ensures that all
10273 * previously issued LMT stores to NIX_LF_OP_SEND() have completed. All
10274 * other accesses to this register (e.g. reads and writes) are RAZ/WI.
10275 * RSL accesses to this register are RAZ/WI.
10277 union nixx_lf_sq_op_status {
10279 struct nixx_lf_sq_op_status_s {
10280 u64 sqb_count : 16;
10281 u64 reserved_16_19 : 4;
10282 u64 head_offset : 6;
10283 u64 reserved_26_27 : 2;
10284 u64 tail_offset : 6;
10285 u64 reserved_34_62 : 29;
10288 struct nixx_lf_sq_op_status_cn {
10289 u64 sqb_count : 16;
10290 u64 reserved_16_19 : 4;
10291 u64 head_offset : 6;
10292 u64 reserved_26_27 : 2;
10293 u64 tail_offset : 6;
10294 u64 reserved_34_35 : 2;
10295 u64 reserved_36_62 : 27;
10300 static inline u64 NIXX_LF_SQ_OP_STATUS(void)
10301 __attribute__ ((pure, always_inline));
10302 static inline u64 NIXX_LF_SQ_OP_STATUS(void)
10308 * Register (RVU_PFVF_BAR2) nix#_lf_tx_stat#
10310 * NIX LF Transmit Statistics Registers The last dimension indicates
10311 * which statistic, and is enumerated by NIX_STAT_LF_TX_E.
10313 union nixx_lf_tx_statx {
10315 struct nixx_lf_tx_statx_s {
10317 u64 reserved_48_63 : 16;
10319 /* struct nixx_lf_tx_statx_s cn; */
10322 static inline u64 NIXX_LF_TX_STATX(u64 a)
10323 __attribute__ ((pure, always_inline));
10324 static inline u64 NIXX_LF_TX_STATX(u64 a)
10326 return 0x300 + 8 * a;
10330 * Register (RVU_PF_BAR0) nix#_priv_af_int_cfg
10332 * NIX Privileged Admin Function Interrupt Configuration Register
10334 union nixx_priv_af_int_cfg {
10336 struct nixx_priv_af_int_cfg_s {
10337 u64 msix_offset : 11;
10338 u64 reserved_11 : 1;
10340 u64 reserved_20_63 : 44;
10342 /* struct nixx_priv_af_int_cfg_s cn; */
10345 static inline u64 NIXX_PRIV_AF_INT_CFG(void)
10346 __attribute__ ((pure, always_inline));
10347 static inline u64 NIXX_PRIV_AF_INT_CFG(void)
10353 * Register (RVU_PF_BAR0) nix#_priv_lf#_cfg
10355 * NIX Privileged Local Function Configuration Registers These registers
10356 * allow each NIX local function (LF) to be provisioned to a VF/PF for
10357 * RVU. See also NIX_AF_RVU_LF_CFG_DEBUG. Software should read this
10358 * register after write to ensure that the LF is mapped to [PF_FUNC]
10359 * before issuing transactions to the mapped PF and function. [SLOT]
10360 * must be zero. Internal: Hardware ignores [SLOT] and always assumes
10363 union nixx_priv_lfx_cfg {
10365 struct nixx_priv_lfx_cfg_s {
10368 u64 reserved_24_62 : 39;
10371 /* struct nixx_priv_lfx_cfg_s cn; */
10374 static inline u64 NIXX_PRIV_LFX_CFG(u64 a)
10375 __attribute__ ((pure, always_inline));
10376 static inline u64 NIXX_PRIV_LFX_CFG(u64 a)
10378 return 0x8000010 + 0x100 * a;
10382 * Register (RVU_PF_BAR0) nix#_priv_lf#_int_cfg
10384 * NIX Privileged LF Interrupt Configuration Registers
10386 union nixx_priv_lfx_int_cfg {
10388 struct nixx_priv_lfx_int_cfg_s {
10389 u64 msix_offset : 11;
10390 u64 reserved_11 : 1;
10392 u64 reserved_20_63 : 44;
10394 /* struct nixx_priv_lfx_int_cfg_s cn; */
10397 static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a)
10398 __attribute__ ((pure, always_inline));
10399 static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a)
10401 return 0x8000020 + 0x100 * a;
10404 #endif /* __CSRS_NIX_H__ */