1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Marvell International Ltd.
5 * https://spdx.org/licenses
11 #include <asm/arch/soc.h>
14 #define RST_BOOT 0x87E006001600ULL
16 #define CPC_BOOT_OWNERX(a) 0x86D000000160ULL + (8 * (a))
18 /** Structure definitions */
20 * Register (NCB32b) cpc_boot_owner#
22 * CPC Boot Owner Registers These registers control an external arbiter
23 * for the boot device (SPI/eMMC) across multiple external devices. There
24 * is a register for each requester: _ \<0\> - SCP - reset on
25 * SCP reset _ \<1\> - MCP - reset on MCP reset _ \<2\> - AP
26 * Secure - reset on core reset _ \<3\> - AP Nonsecure - reset on core
27 * reset These register is only writable to the corresponding
28 * requestor(s) permitted with CPC_PERMIT.
30 union cpc_boot_ownerx {
32 struct cpc_boot_ownerx_s {
36 u32 reserved_9_31 : 23;
41 * Register (RSL) rst_boot
43 * RST Boot Register This register is not accessible through ROM scripts;
44 * see SCR_WRITE32_S[ADDR].
51 u64 reserved_2_32 : 31;
55 u64 reserved_47_52 : 6;
64 u64 reserved_61_62 : 2;
67 struct rst_boot_cn96xx {
70 u64 reserved_2_23 : 22;
72 u64 reserved_31_32 : 2;
76 u64 reserved_47_52 : 6;
82 u64 reserved_58_59 : 2;
88 struct rst_boot_cnf95xx {
97 u64 reserved_31_32 : 2;
101 u64 reserved_47_52 : 6;
107 u64 reserved_58_59 : 2;
108 u64 trusted_mode : 1;
115 extern unsigned long fdt_base_addr;
117 /** Function definitions */
118 void mem_map_fill(void);
119 int fdt_get_board_mac_cnt(void);
120 u64 fdt_get_board_mac_addr(void);
121 const char *fdt_get_board_model(void);
122 const char *fdt_get_board_serial(void);
123 const char *fdt_get_board_revision(void);
124 void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr);
125 void board_acquire_flash_arb(bool acquire);
126 void cgx_intf_shutdown(void);
128 #endif /* __BOARD_H__ */