1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Marvell International Ltd.
5 * https://spdx.org/licenses
7 #ifndef __CSRS_MIO_EMM_H__
8 #define __CSRS_MIO_EMM_H__
13 * Configuration and status register (CSR) address and type definitions for
16 * This file is auto generated. Do not edit.
21 * Enumeration mio_emm_bar_e
23 * eMMC Base Address Register Enumeration Enumerates the base address
26 #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8 (0x87e009000000ll)
27 #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8_SIZE 0x800000ull
28 #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9 (0x87e009000000ll)
29 #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9_SIZE 0x10000ull
30 #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4 (0x87e009f00000ll)
31 #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4_SIZE 0x100000ull
34 * Enumeration mio_emm_int_vec_e
36 * eMMC MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors.
38 #define MIO_EMM_INT_VEC_E_DMA_INT_DONE (8)
39 #define MIO_EMM_INT_VEC_E_DMA_INT_FIFO (7)
40 #define MIO_EMM_INT_VEC_E_EMM_BUF_DONE (0)
41 #define MIO_EMM_INT_VEC_E_EMM_CMD_DONE (1)
42 #define MIO_EMM_INT_VEC_E_EMM_CMD_ERR (3)
43 #define MIO_EMM_INT_VEC_E_EMM_DMA_DONE (2)
44 #define MIO_EMM_INT_VEC_E_EMM_DMA_ERR (4)
45 #define MIO_EMM_INT_VEC_E_EMM_SWITCH_DONE (5)
46 #define MIO_EMM_INT_VEC_E_EMM_SWITCH_ERR (6)
47 #define MIO_EMM_INT_VEC_E_NCB_FLT (9)
48 #define MIO_EMM_INT_VEC_E_NCB_RAS (0xa)
51 * Register (RSL) mio_emm_access_wdog
53 * eMMC Access Watchdog Register
55 union mio_emm_access_wdog {
57 struct mio_emm_access_wdog_s {
59 u64 reserved_32_63 : 32;
61 /* struct mio_emm_access_wdog_s cn; */
64 static inline u64 MIO_EMM_ACCESS_WDOG(void)
65 __attribute__ ((pure, always_inline));
66 static inline u64 MIO_EMM_ACCESS_WDOG(void)
72 * Register (RSL) mio_emm_buf_dat
74 * eMMC Data Buffer Access Register
76 union mio_emm_buf_dat {
78 struct mio_emm_buf_dat_s {
81 /* struct mio_emm_buf_dat_s cn; */
84 static inline u64 MIO_EMM_BUF_DAT(void)
85 __attribute__ ((pure, always_inline));
86 static inline u64 MIO_EMM_BUF_DAT(void)
92 * Register (RSL) mio_emm_buf_idx
94 * eMMC Data Buffer Address Register
96 union mio_emm_buf_idx {
98 struct mio_emm_buf_idx_s {
101 u64 reserved_7_15 : 9;
103 u64 reserved_17_63 : 47;
105 /* struct mio_emm_buf_idx_s cn; */
108 static inline u64 MIO_EMM_BUF_IDX(void)
109 __attribute__ ((pure, always_inline));
110 static inline u64 MIO_EMM_BUF_IDX(void)
116 * Register (RSL) mio_emm_calb
118 * eMMC Calbration Register This register initiates delay line
123 struct mio_emm_calb_s {
125 u64 reserved_1_63 : 63;
127 /* struct mio_emm_calb_s cn; */
130 static inline u64 MIO_EMM_CALB(void)
131 __attribute__ ((pure, always_inline));
132 static inline u64 MIO_EMM_CALB(void)
138 * Register (RSL) mio_emm_cfg
140 * eMMC Configuration Register
144 struct mio_emm_cfg_s {
146 u64 reserved_4_63 : 60;
148 /* struct mio_emm_cfg_s cn; */
151 static inline u64 MIO_EMM_CFG(void)
152 __attribute__ ((pure, always_inline));
153 static inline u64 MIO_EMM_CFG(void)
159 * Register (RSL) mio_emm_cmd
161 * eMMC Command Register
165 struct mio_emm_cmd_s {
170 u64 reserved_43_48 : 6;
173 u64 reserved_56_58 : 3;
179 /* struct mio_emm_cmd_s cn; */
182 static inline u64 MIO_EMM_CMD(void)
183 __attribute__ ((pure, always_inline));
184 static inline u64 MIO_EMM_CMD(void)
190 * Register (RSL) mio_emm_comp
192 * eMMC Compensation Register
196 struct mio_emm_comp_s {
198 u64 reserved_3_7 : 5;
200 u64 reserved_11_63 : 53;
202 /* struct mio_emm_comp_s cn; */
205 static inline u64 MIO_EMM_COMP(void)
206 __attribute__ ((pure, always_inline));
207 static inline u64 MIO_EMM_COMP(void)
213 * Register (RSL) mio_emm_debug
215 * eMMC Debug Register
217 union mio_emm_debug {
219 struct mio_emm_debug_s {
221 u64 reserved_1_7 : 7;
225 u64 emmc_clk_disable : 1;
227 u64 reserved_22_63 : 42;
229 struct mio_emm_debug_cn96xxp1 {
231 u64 reserved_1_7 : 7;
235 u64 reserved_20_63 : 44;
237 /* struct mio_emm_debug_s cn96xxp3; */
238 /* struct mio_emm_debug_cn96xxp1 cnf95xx; */
241 static inline u64 MIO_EMM_DEBUG(void)
242 __attribute__ ((pure, always_inline));
243 static inline u64 MIO_EMM_DEBUG(void)
249 * Register (RSL) mio_emm_dma
251 * eMMC External DMA Configuration Register
255 struct mio_emm_dma_s {
269 struct mio_emm_dma_cn8 {
283 struct mio_emm_dma_cn9 {
299 static inline u64 MIO_EMM_DMA(void)
300 __attribute__ ((pure, always_inline));
301 static inline u64 MIO_EMM_DMA(void)
307 * Register (RSL) mio_emm_dma_adr
309 * eMMC DMA Address Register This register sets the address for eMMC/SD
310 * flash transfers to/from memory. Sixty-four-bit operations must be used
311 * to access this register. This register is updated by the DMA hardware
312 * and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR.
314 union mio_emm_dma_adr {
316 struct mio_emm_dma_adr_s {
318 u64 reserved_53_63 : 11;
320 struct mio_emm_dma_adr_cn8 {
322 u64 reserved_49_63 : 15;
324 /* struct mio_emm_dma_adr_s cn9; */
327 static inline u64 MIO_EMM_DMA_ADR(void)
328 __attribute__ ((pure, always_inline));
329 static inline u64 MIO_EMM_DMA_ADR(void)
335 * Register (RSL) mio_emm_dma_arg
337 * eMMC External DMA Extra Arguments Register
339 union mio_emm_dma_arg {
341 struct mio_emm_dma_arg_s {
349 u64 skip_blk_cmd : 1;
350 u64 reserved_23_31 : 9;
351 u64 alt_cmd_arg : 32;
353 /* struct mio_emm_dma_arg_s cn; */
356 static inline u64 MIO_EMM_DMA_ARG(void)
357 __attribute__ ((pure, always_inline));
358 static inline u64 MIO_EMM_DMA_ARG(void)
364 * Register (RSL) mio_emm_dma_cfg
366 * eMMC DMA Configuration Register This register controls the internal
367 * DMA engine used with the eMMC/SD flash controller. Sixty- four-bit
368 * operations must be used to access this register. This register is
369 * updated by the hardware DMA engine and can also be reloaded by writes
370 * to the MIO_EMM_DMA_FIFO_CMD register.
372 union mio_emm_dma_cfg {
374 struct mio_emm_dma_cfg_s {
375 u64 reserved_0_35 : 36;
386 /* struct mio_emm_dma_cfg_s cn; */
389 static inline u64 MIO_EMM_DMA_CFG(void)
390 __attribute__ ((pure, always_inline));
391 static inline u64 MIO_EMM_DMA_CFG(void)
397 * Register (RSL) mio_emm_dma_fifo_adr
399 * eMMC Internal DMA FIFO Address Register This register specifies the
400 * internal address that is loaded into the eMMC internal DMA FIFO. The
401 * FIFO is used to queue up operations for the
402 * MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes successfully.
404 union mio_emm_dma_fifo_adr {
406 struct mio_emm_dma_fifo_adr_s {
407 u64 reserved_0_2 : 3;
409 u64 reserved_53_63 : 11;
411 struct mio_emm_dma_fifo_adr_cn8 {
412 u64 reserved_0_2 : 3;
414 u64 reserved_49_63 : 15;
416 /* struct mio_emm_dma_fifo_adr_s cn9; */
419 static inline u64 MIO_EMM_DMA_FIFO_ADR(void)
420 __attribute__ ((pure, always_inline));
421 static inline u64 MIO_EMM_DMA_FIFO_ADR(void)
427 * Register (RSL) mio_emm_dma_fifo_cfg
429 * eMMC Internal DMA FIFO Configuration Register This register controls
430 * DMA FIFO operations.
432 union mio_emm_dma_fifo_cfg {
434 struct mio_emm_dma_fifo_cfg_s {
436 u64 reserved_5_7 : 3;
438 u64 reserved_13_15 : 3;
440 u64 reserved_17_63 : 47;
442 /* struct mio_emm_dma_fifo_cfg_s cn; */
445 static inline u64 MIO_EMM_DMA_FIFO_CFG(void)
446 __attribute__ ((pure, always_inline));
447 static inline u64 MIO_EMM_DMA_FIFO_CFG(void)
453 * Register (RSL) mio_emm_dma_fifo_cmd
455 * eMMC Internal DMA FIFO Command Register This register specifies a
456 * command that is loaded into the eMMC internal DMA FIFO. The FIFO is
457 * used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR
458 * when the DMA completes successfully. Writes to this register store
459 * both the MIO_EMM_DMA_FIFO_CMD and the MIO_EMM_DMA_FIFO_ADR contents
460 * into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT] field.
461 * Note: This register has a similar format to MIO_EMM_DMA_CFG with the
462 * exception that the EN and CLR fields are absent. These are supported
463 * in MIO_EMM_DMA_FIFO_CFG.
465 union mio_emm_dma_fifo_cmd {
467 struct mio_emm_dma_fifo_cmd_s {
468 u64 reserved_0_35 : 36;
479 /* struct mio_emm_dma_fifo_cmd_s cn; */
482 static inline u64 MIO_EMM_DMA_FIFO_CMD(void)
483 __attribute__ ((pure, always_inline));
484 static inline u64 MIO_EMM_DMA_FIFO_CMD(void)
490 * Register (RSL) mio_emm_dma_int
492 * eMMC DMA Interrupt Register Sixty-four-bit operations must be used to
493 * access this register.
495 union mio_emm_dma_int {
497 struct mio_emm_dma_int_s {
500 u64 reserved_2_63 : 62;
502 /* struct mio_emm_dma_int_s cn; */
505 static inline u64 MIO_EMM_DMA_INT(void)
506 __attribute__ ((pure, always_inline));
507 static inline u64 MIO_EMM_DMA_INT(void)
513 * Register (RSL) mio_emm_dma_int_ena_w1c
515 * eMMC DMA Interrupt Enable Clear Register This register clears
516 * interrupt enable bits.
518 union mio_emm_dma_int_ena_w1c {
520 struct mio_emm_dma_int_ena_w1c_s {
523 u64 reserved_2_63 : 62;
525 /* struct mio_emm_dma_int_ena_w1c_s cn; */
528 static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void)
529 __attribute__ ((pure, always_inline));
530 static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void)
536 * Register (RSL) mio_emm_dma_int_ena_w1s
538 * eMMC DMA Interrupt Enable Set Register This register sets interrupt
541 union mio_emm_dma_int_ena_w1s {
543 struct mio_emm_dma_int_ena_w1s_s {
546 u64 reserved_2_63 : 62;
548 /* struct mio_emm_dma_int_ena_w1s_s cn; */
551 static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void)
552 __attribute__ ((pure, always_inline));
553 static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void)
559 * Register (RSL) mio_emm_dma_int_w1s
561 * eMMC DMA Interrupt Set Register This register sets interrupt bits.
563 union mio_emm_dma_int_w1s {
565 struct mio_emm_dma_int_w1s_s {
568 u64 reserved_2_63 : 62;
570 /* struct mio_emm_dma_int_w1s_s cn; */
573 static inline u64 MIO_EMM_DMA_INT_W1S(void)
574 __attribute__ ((pure, always_inline));
575 static inline u64 MIO_EMM_DMA_INT_W1S(void)
581 * Register (RSL) mio_emm_int
583 * eMMC Interrupt Register
587 struct mio_emm_int_s {
597 u64 reserved_9_63 : 55;
599 struct mio_emm_int_cn8 {
607 u64 reserved_7_63 : 57;
609 /* struct mio_emm_int_s cn9; */
612 static inline u64 MIO_EMM_INT(void)
613 __attribute__ ((pure, always_inline));
614 static inline u64 MIO_EMM_INT(void)
620 * Register (RSL) mio_emm_int_ena_w1c
622 * eMMC Interrupt Enable Clear Register This register clears interrupt
625 union mio_emm_int_ena_w1c {
627 struct mio_emm_int_ena_w1c_s {
637 u64 reserved_9_63 : 55;
639 struct mio_emm_int_ena_w1c_cn8 {
647 u64 reserved_7_63 : 57;
649 /* struct mio_emm_int_ena_w1c_s cn9; */
652 static inline u64 MIO_EMM_INT_ENA_W1C(void)
653 __attribute__ ((pure, always_inline));
654 static inline u64 MIO_EMM_INT_ENA_W1C(void)
660 * Register (RSL) mio_emm_int_ena_w1s
662 * eMMC Interrupt Enable Set Register This register sets interrupt enable
665 union mio_emm_int_ena_w1s {
667 struct mio_emm_int_ena_w1s_s {
677 u64 reserved_9_63 : 55;
679 struct mio_emm_int_ena_w1s_cn8 {
687 u64 reserved_7_63 : 57;
689 /* struct mio_emm_int_ena_w1s_s cn9; */
692 static inline u64 MIO_EMM_INT_ENA_W1S(void)
693 __attribute__ ((pure, always_inline));
694 static inline u64 MIO_EMM_INT_ENA_W1S(void)
700 * Register (RSL) mio_emm_int_w1s
702 * eMMC Interrupt Set Register This register sets interrupt bits.
704 union mio_emm_int_w1s {
706 struct mio_emm_int_w1s_s {
716 u64 reserved_9_63 : 55;
718 struct mio_emm_int_w1s_cn8 {
726 u64 reserved_7_63 : 57;
728 /* struct mio_emm_int_w1s_s cn9; */
731 static inline u64 MIO_EMM_INT_W1S(void)
732 __attribute__ ((pure, always_inline));
733 static inline u64 MIO_EMM_INT_W1S(void)
739 * Register (RSL) mio_emm_io_ctl
741 * eMMC I/O Control Register
743 union mio_emm_io_ctl {
745 struct mio_emm_io_ctl_s {
749 u64 reserved_4_63 : 60;
751 /* struct mio_emm_io_ctl_s cn; */
754 static inline u64 MIO_EMM_IO_CTL(void)
755 __attribute__ ((pure, always_inline));
756 static inline u64 MIO_EMM_IO_CTL(void)
762 * Register (RSL) mio_emm_mode#
764 * eMMC Operating Mode Register
766 union mio_emm_modex {
768 struct mio_emm_modex_s {
773 u64 reserved_37_39 : 3;
775 u64 reserved_43_47 : 5;
777 u64 hs200_timing : 1;
778 u64 hs400_timing : 1;
779 u64 reserved_51_63 : 13;
781 struct mio_emm_modex_cn8 {
785 u64 reserved_36_39 : 4;
787 u64 reserved_43_47 : 5;
789 u64 reserved_49_63 : 15;
791 struct mio_emm_modex_cn96xxp1 {
795 u64 reserved_36_39 : 4;
797 u64 reserved_43_47 : 5;
799 u64 hs200_timing : 1;
800 u64 hs400_timing : 1;
801 u64 reserved_51_63 : 13;
803 /* struct mio_emm_modex_s cn96xxp3; */
804 /* struct mio_emm_modex_s cnf95xx; */
807 static inline u64 MIO_EMM_MODEX(u64 a)
808 __attribute__ ((pure, always_inline));
809 static inline u64 MIO_EMM_MODEX(u64 a)
811 return 0x2008 + 8 * a;
815 * Register (RSL) mio_emm_msix_pba#
817 * eMMC MSI-X Pending Bit Array Registers This register is the MSI-X PBA
818 * table; the bit number is indexed by the MIO_EMM_INT_VEC_E enumeration.
820 union mio_emm_msix_pbax {
822 struct mio_emm_msix_pbax_s {
825 /* struct mio_emm_msix_pbax_s cn; */
828 static inline u64 MIO_EMM_MSIX_PBAX(u64 a)
829 __attribute__ ((pure, always_inline));
830 static inline u64 MIO_EMM_MSIX_PBAX(u64 a)
832 return 0xf0000 + 8 * a;
836 * Register (RSL) mio_emm_msix_vec#_addr
838 * eMMC MSI-X Vector-Table Address Register This register is the MSI-X
839 * vector table, indexed by the MIO_EMM_INT_VEC_E enumeration.
841 union mio_emm_msix_vecx_addr {
843 struct mio_emm_msix_vecx_addr_s {
847 u64 reserved_53_63 : 11;
849 struct mio_emm_msix_vecx_addr_cn8 {
853 u64 reserved_49_63 : 15;
855 /* struct mio_emm_msix_vecx_addr_s cn9; */
858 static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a)
859 __attribute__ ((pure, always_inline));
860 static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a)
866 * Register (RSL) mio_emm_msix_vec#_ctl
868 * eMMC MSI-X Vector-Table Control and Data Register This register is the
869 * MSI-X vector table, indexed by the MIO_EMM_INT_VEC_E enumeration.
871 union mio_emm_msix_vecx_ctl {
873 struct mio_emm_msix_vecx_ctl_s {
876 u64 reserved_33_63 : 31;
878 struct mio_emm_msix_vecx_ctl_cn8 {
880 u64 reserved_20_31 : 12;
882 u64 reserved_33_63 : 31;
884 /* struct mio_emm_msix_vecx_ctl_s cn9; */
887 static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a)
888 __attribute__ ((pure, always_inline));
889 static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a)
895 * Register (RSL) mio_emm_rca
897 * eMMC Relative Card Address Register
901 struct mio_emm_rca_s {
903 u64 reserved_16_63 : 48;
905 /* struct mio_emm_rca_s cn; */
908 static inline u64 MIO_EMM_RCA(void)
909 __attribute__ ((pure, always_inline));
910 static inline u64 MIO_EMM_RCA(void)
916 * Register (RSL) mio_emm_rsp_hi
918 * eMMC Response Data High Register
920 union mio_emm_rsp_hi {
922 struct mio_emm_rsp_hi_s {
925 /* struct mio_emm_rsp_hi_s cn; */
928 static inline u64 MIO_EMM_RSP_HI(void)
929 __attribute__ ((pure, always_inline));
930 static inline u64 MIO_EMM_RSP_HI(void)
936 * Register (RSL) mio_emm_rsp_lo
938 * eMMC Response Data Low Register
940 union mio_emm_rsp_lo {
942 struct mio_emm_rsp_lo_s {
945 /* struct mio_emm_rsp_lo_s cn; */
948 static inline u64 MIO_EMM_RSP_LO(void)
949 __attribute__ ((pure, always_inline));
950 static inline u64 MIO_EMM_RSP_LO(void)
956 * Register (RSL) mio_emm_rsp_sts
958 * eMMC Response Status Register
960 union mio_emm_rsp_sts {
962 struct mio_emm_rsp_sts_s {
979 u64 reserved_24_27 : 4;
981 u64 reserved_29_54 : 26;
988 u64 reserved_62_63 : 2;
990 /* struct mio_emm_rsp_sts_s cn; */
993 static inline u64 MIO_EMM_RSP_STS(void)
994 __attribute__ ((pure, always_inline));
995 static inline u64 MIO_EMM_RSP_STS(void)
1001 * Register (RSL) mio_emm_sample
1003 * eMMC Sampling Register
1005 union mio_emm_sample {
1007 struct mio_emm_sample_s {
1009 u64 reserved_10_15 : 6;
1011 u64 reserved_26_63 : 38;
1013 /* struct mio_emm_sample_s cn; */
1016 static inline u64 MIO_EMM_SAMPLE(void)
1017 __attribute__ ((pure, always_inline));
1018 static inline u64 MIO_EMM_SAMPLE(void)
1024 * Register (RSL) mio_emm_sts_mask
1026 * eMMC Status Mask Register
1028 union mio_emm_sts_mask {
1030 struct mio_emm_sts_mask_s {
1032 u64 reserved_32_63 : 32;
1034 /* struct mio_emm_sts_mask_s cn; */
1037 static inline u64 MIO_EMM_STS_MASK(void)
1038 __attribute__ ((pure, always_inline));
1039 static inline u64 MIO_EMM_STS_MASK(void)
1045 * Register (RSL) mio_emm_switch
1047 * eMMC Operating Mode Switch Register This register allows software to
1048 * change eMMC related parameters associated with a specific BUS_ID. The
1049 * MIO_EMM_MODE() registers contain the current setting for each BUS.
1050 * This register is also used to switch the [CLK_HI] and [CLK_LO]
1051 * settings associated with the common EMMC_CLK. These settings can only
1052 * be changed when [BUS_ID] = 0.
1054 union mio_emm_switch {
1056 struct mio_emm_switch_s {
1059 u64 power_class : 4;
1061 u64 reserved_37_39 : 3;
1063 u64 reserved_43_47 : 5;
1065 u64 hs200_timing : 1;
1066 u64 hs400_timing : 1;
1067 u64 reserved_51_55 : 5;
1068 u64 switch_err2 : 1;
1069 u64 switch_err1 : 1;
1070 u64 switch_err0 : 1;
1073 u64 reserved_62_63 : 2;
1075 struct mio_emm_switch_cn8 {
1078 u64 power_class : 4;
1079 u64 reserved_36_39 : 4;
1081 u64 reserved_43_47 : 5;
1083 u64 reserved_49_55 : 7;
1084 u64 switch_err2 : 1;
1085 u64 switch_err1 : 1;
1086 u64 switch_err0 : 1;
1089 u64 reserved_62_63 : 2;
1091 struct mio_emm_switch_cn96xxp1 {
1094 u64 power_class : 4;
1095 u64 reserved_36_39 : 4;
1097 u64 reserved_43_47 : 5;
1099 u64 hs200_timing : 1;
1100 u64 hs400_timing : 1;
1101 u64 reserved_51_55 : 5;
1102 u64 switch_err2 : 1;
1103 u64 switch_err1 : 1;
1104 u64 switch_err0 : 1;
1107 u64 reserved_62_63 : 2;
1109 /* struct mio_emm_switch_s cn96xxp3; */
1110 /* struct mio_emm_switch_s cnf95xx; */
1113 static inline u64 MIO_EMM_SWITCH(void)
1114 __attribute__ ((pure, always_inline));
1115 static inline u64 MIO_EMM_SWITCH(void)
1121 * Register (RSL) mio_emm_tap
1123 * eMMC TAP Delay Register This register indicates the delay line
1128 struct mio_emm_tap_s {
1130 u64 reserved_8_63 : 56;
1132 /* struct mio_emm_tap_s cn; */
1135 static inline u64 MIO_EMM_TAP(void)
1136 __attribute__ ((pure, always_inline));
1137 static inline u64 MIO_EMM_TAP(void)
1143 * Register (RSL) mio_emm_timing
1145 * eMMC Timing Register This register determines the number of tap delays
1146 * the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in
1147 * relation to EMM_CLK. These values should only be changed when the eMMC
1150 union mio_emm_timing {
1152 struct mio_emm_timing_s {
1153 u64 data_out_tap : 6;
1154 u64 reserved_6_15 : 10;
1155 u64 data_in_tap : 6;
1156 u64 reserved_22_31 : 10;
1157 u64 cmd_out_tap : 6;
1158 u64 reserved_38_47 : 10;
1160 u64 reserved_54_63 : 10;
1162 /* struct mio_emm_timing_s cn; */
1165 static inline u64 MIO_EMM_TIMING(void)
1166 __attribute__ ((pure, always_inline));
1167 static inline u64 MIO_EMM_TIMING(void)
1173 * Register (RSL) mio_emm_wdog
1175 * eMMC Watchdog Register
1177 union mio_emm_wdog {
1179 struct mio_emm_wdog_s {
1181 u64 reserved_26_63 : 38;
1183 /* struct mio_emm_wdog_s cn; */
1186 static inline u64 MIO_EMM_WDOG(void)
1187 __attribute__ ((pure, always_inline));
1188 static inline u64 MIO_EMM_WDOG(void)
1193 #endif /* __CSRS_MIO_EMM_H__ */