2 * Freescale i.MX23/i.MX28 specific functions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __SYS_PROTO_H__
11 #define __SYS_PROTO_H__
13 #include <asm/imx-common/regs-common.h>
14 #include <../arch-imx/cpu.h>
16 int mxs_reset_block(struct mxs_register_32 *reg);
17 int mxs_wait_mask_set(struct mxs_register_32 *reg,
19 unsigned int timeout);
20 int mxs_wait_mask_clr(struct mxs_register_32 *reg,
22 unsigned int timeout);
24 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
26 #ifdef CONFIG_SPL_BUILD
28 #if defined(CONFIG_MX23)
29 #include <asm/arch/iomux-mx23.h>
30 #elif defined(CONFIG_MX28)
31 #include <asm/arch/iomux-mx28.h>
34 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
35 const iomux_cfg_t *iomux_setup,
36 const unsigned int iomux_size);
45 static const struct mxs_pair mxs_boot_modes[] = {
46 #if defined(CONFIG_MX23)
47 { 0x00, 0x0f, "USB" },
48 { 0x01, 0x1f, "I2C, master" },
49 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
50 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
51 { 0x04, 0x1f, "NAND" },
52 { 0x06, 0x1f, "JTAG" },
53 { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
54 { 0x09, 0x1f, "SSP SD/MMC #0" },
55 { 0x0a, 0x1f, "SSP SD/MMC #1" },
56 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
57 #elif defined(CONFIG_MX28)
58 { 0x00, 0x0f, "USB #0" },
59 { 0x01, 0x1f, "I2C #0, master, 3V3" },
60 { 0x11, 0x1f, "I2C #0, master, 1V8" },
61 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
62 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
63 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
64 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
65 { 0x04, 0x1f, "NAND, 3V3" },
66 { 0x14, 0x1f, "NAND, 1V8" },
67 { 0x06, 0x1f, "JTAG" },
68 { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
69 { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
70 { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
71 { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
72 { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
73 { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
74 { 0x00, 0x00, "Reserved/Unknown/Wrong" },
78 #define MXS_BM_USB 0x00
79 #define MXS_BM_I2C_MASTER_3V3 0x01
80 #define MXS_BM_I2C_MASTER_1V8 0x11
81 #define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
82 #define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
83 #define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
84 #define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
85 #define MXS_BM_NAND_3V3 0x04
86 #define MXS_BM_NAND_1V8 0x14
87 #define MXS_BM_JTAG 0x06
88 #define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
89 #define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
90 #define MXS_BM_SDMMC0_3V3 0x09
91 #define MXS_BM_SDMMC0_1V8 0x19
92 #define MXS_BM_SDMMC1_3V3 0x0a
93 #define MXS_BM_SDMMC1_1V8 0x1a
96 uint8_t boot_mode_idx;
97 uint32_t mem_dram_size;
100 int mxs_dram_init(void);
102 #endif /* __SYS_PROTO_H__ */