1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Peng Fan <peng.fan@nxp.com>
8 #ifndef _ASM_ARCH_IMX8M_CLOCK_H
9 #define _ASM_ARCH_IMX8M_CLOCK_H
11 #include <linux/bitops.h>
41 GPU_CORE_CLK_ROOT = 3,
42 GPU_SHADER_CLK_ROOT = 4,
43 MAIN_AXI_CLK_ROOT = 16,
44 ENET_AXI_CLK_ROOT = 17,
45 NAND_USDHC_BUS_CLK_ROOT = 18,
46 VPU_BUS_CLK_ROOT = 19,
47 DISPLAY_AXI_CLK_ROOT = 20,
48 DISPLAY_APB_CLK_ROOT = 21,
49 DISPLAY_RTRM_CLK_ROOT = 22,
50 USB_BUS_CLK_ROOT = 23,
51 GPU_AXI_CLK_ROOT = 24,
52 GPU_AHB_CLK_ROOT = 25,
54 NOC_APB_CLK_ROOT = 27,
58 AUDIO_AHB_CLK_ROOT = 34,
59 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
62 DRAM_ALT_CLK_ROOT = 64,
63 DRAM_APB_CLK_ROOT = 65,
66 DISPLAY_DTRC_CLK_ROOT = 68,
67 DISPLAY_DC8000_CLK_ROOT = 69,
68 PCIE1_CTRL_CLK_ROOT = 70,
69 PCIE1_PHY_CLK_ROOT = 71,
70 PCIE1_AUX_CLK_ROOT = 72,
71 DC_PIXEL_CLK_ROOT = 73,
72 LCDIF_PIXEL_CLK_ROOT = 74,
81 ENET_REF_CLK_ROOT = 83,
82 ENET_TIMER_CLK_ROOT = 84,
83 ENET_PHY_REF_CLK_ROOT = 85,
99 USB_CORE_REF_CLK_ROOT = 98,
100 USB_PHY_REF_CLK_ROOT = 99,
102 ECSPI1_CLK_ROOT = 101,
103 ECSPI2_CLK_ROOT = 102,
114 TRACE_CLK_ROOT = 113,
116 WRCLK_CLK_ROOT = 115,
119 MIPI_DSI_CORE_CLK_ROOT = 118,
120 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
121 MIPI_DSI_DBI_CLK_ROOT = 120,
122 OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
123 MIPI_CSI1_CORE_CLK_ROOT = 122,
124 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
125 MIPI_CSI1_ESC_CLK_ROOT = 124,
126 MIPI_CSI2_CORE_CLK_ROOT = 125,
127 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
128 MIPI_CSI2_ESC_CLK_ROOT = 127,
129 PCIE2_CTRL_CLK_ROOT = 128,
130 PCIE2_PHY_CLK_ROOT = 129,
131 PCIE2_AUX_CLK_ROOT = 130,
132 ECSPI3_CLK_ROOT = 131,
133 OLD_MIPI_DSI_ESC_RX_ROOT = 132,
134 DISPLAY_HDMI_CLK_ROOT = 133,
145 SYSTEM_PLL1_800M_CLK,
146 SYSTEM_PLL1_400M_CLK,
147 SYSTEM_PLL1_266M_CLK,
148 SYSTEM_PLL1_200M_CLK,
149 SYSTEM_PLL1_160M_CLK,
150 SYSTEM_PLL1_133M_CLK,
151 SYSTEM_PLL1_100M_CLK,
154 SYSTEM_PLL2_1000M_CLK,
155 SYSTEM_PLL2_500M_CLK,
156 SYSTEM_PLL2_333M_CLK,
157 SYSTEM_PLL2_250M_CLK,
158 SYSTEM_PLL2_200M_CLK,
159 SYSTEM_PLL2_166M_CLK,
160 SYSTEM_PLL2_125M_CLK,
161 SYSTEM_PLL2_100M_CLK,
176 enum clk_ccgr_index {
182 CCGR_DRAM2_OBSOLETE = 6,
239 CCGR_SIM_DISPLAY = 63,
244 CCGR_SIM_WAKEUP = 68,
267 CCGR_HEVC_INTER = 91,
277 CCGR_MIPI_CSI1 = 101,
278 CCGR_MIPI_CSI2 = 102,
284 CLK_SRC_CKIL_SYNC_REQ = 0,
285 CLK_SRC_ARM_PLL_EN = 1,
286 CLK_SRC_GPU_PLL_EN = 2,
287 CLK_SRC_VPU_PLL_EN = 3,
288 CLK_SRC_DRAM_PLL_EN = 4,
289 CLK_SRC_SYSTEM_PLL1_EN = 5,
290 CLK_SRC_SYSTEM_PLL2_EN = 6,
291 CLK_SRC_SYSTEM_PLL3_EN = 7,
292 CLK_SRC_AUDIO_PLL1_EN = 8,
293 CLK_SRC_AUDIO_PLL2_EN = 9,
294 CLK_SRC_VIDEO_PLL1_EN = 10,
295 CLK_SRC_VIDEO_PLL2_EN = 11,
296 CLK_SRC_ARM_PLL = 12,
297 CLK_SRC_GPU_PLL = 13,
298 CLK_SRC_VPU_PLL = 14,
299 CLK_SRC_DRAM_PLL = 15,
300 CLK_SRC_SYSTEM_PLL1_800M = 16,
301 CLK_SRC_SYSTEM_PLL1_400M = 17,
302 CLK_SRC_SYSTEM_PLL1_266M = 18,
303 CLK_SRC_SYSTEM_PLL1_200M = 19,
304 CLK_SRC_SYSTEM_PLL1_160M = 20,
305 CLK_SRC_SYSTEM_PLL1_133M = 21,
306 CLK_SRC_SYSTEM_PLL1_100M = 22,
307 CLK_SRC_SYSTEM_PLL1_80M = 23,
308 CLK_SRC_SYSTEM_PLL1_40M = 24,
309 CLK_SRC_SYSTEM_PLL2_1000M = 25,
310 CLK_SRC_SYSTEM_PLL2_500M = 26,
311 CLK_SRC_SYSTEM_PLL2_333M = 27,
312 CLK_SRC_SYSTEM_PLL2_250M = 28,
313 CLK_SRC_SYSTEM_PLL2_200M = 29,
314 CLK_SRC_SYSTEM_PLL2_166M = 30,
315 CLK_SRC_SYSTEM_PLL2_125M = 31,
316 CLK_SRC_SYSTEM_PLL2_100M = 32,
317 CLK_SRC_SYSTEM_PLL2_50M = 33,
318 CLK_SRC_SYSTEM_PLL3 = 34,
319 CLK_SRC_AUDIO_PLL1 = 35,
320 CLK_SRC_AUDIO_PLL2 = 36,
321 CLK_SRC_VIDEO_PLL1 = 37,
322 CLK_SRC_VIDEO_PLL2 = 38,
323 CLK_SRC_OSC_25M = 39,
324 CLK_SRC_OSC_27M = 40,
328 CLK_ROOT_PRE_DIV1 = 0,
339 CLK_ROOT_POST_DIV1 = 0,
405 struct clk_root_map {
406 enum clk_root_index entry;
407 enum clk_slice_type slice_type;
429 u32 nm_post_root_set;
430 u32 nm_post_root_clr;
431 u32 nm_post_root_tog;
437 u32 db_post_root_set;
438 u32 db_post_root_clr;
439 u32 db_post_root_tog;
446 u32 access_ctrl_root_set;
447 u32 access_ctrl_root_clr;
448 u32 access_ctrl_root_tog;
452 u32 reserved_0[4096];
453 struct ccm_ccgr ccgr_array[192];
454 u32 reserved_1[3328];
455 struct ccm_root core_root[5];
457 struct ccm_root bus_root[12];
459 struct ccm_root ahb_ipg_root[4];
461 struct ccm_root dram_sel;
462 struct ccm_root core_sel;
464 struct ccm_root ip_root[78];
467 #define CCGR_CLK_ON_MASK 0x03
468 #define CLK_SRC_ON_MASK 0x03
470 #define CLK_ROOT_ON BIT(28)
471 #define CLK_ROOT_OFF (0 << 28)
472 #define CLK_ROOT_ENABLE_MASK BIT(28)
473 #define CLK_ROOT_ENABLE_SHIFT 28
474 #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
476 /* For SEL, only use 1 bit */
477 #define CLK_ROOT_SRC_MUX_MASK 0x07000000
478 #define CLK_ROOT_SRC_MUX_SHIFT 24
479 #define CLK_ROOT_SRC_0 0x00000000
480 #define CLK_ROOT_SRC_1 0x01000000
481 #define CLK_ROOT_SRC_2 0x02000000
482 #define CLK_ROOT_SRC_3 0x03000000
483 #define CLK_ROOT_SRC_4 0x04000000
484 #define CLK_ROOT_SRC_5 0x05000000
485 #define CLK_ROOT_SRC_6 0x06000000
486 #define CLK_ROOT_SRC_7 0x07000000
488 #define CLK_ROOT_PRE_DIV_MASK (0x00070000)
489 #define CLK_ROOT_PRE_DIV_SHIFT 16
490 #define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
492 #define CLK_ROOT_AUDO_SLOW_EN 0x1000
494 #define CLK_ROOT_AUDO_DIV_MASK 0x700
495 #define CLK_ROOT_AUDO_DIV_SHIFT 0x8
496 #define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
498 /* For CORE: mask is 0x7; For IPG: mask is 0x3 */
499 #define CLK_ROOT_POST_DIV_MASK 0x3f
500 #define CLK_ROOT_CORE_POST_DIV_MASK 0x7
501 #define CLK_ROOT_IPG_POST_DIV_MASK 0x3
502 #define CLK_ROOT_POST_DIV_SHIFT 0
503 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
505 /* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
506 #define FRAC_PLL_LOCK_MASK BIT(31)
507 #define FRAC_PLL_CLKE_MASK BIT(21)
508 #define FRAC_PLL_PD_MASK BIT(19)
509 #define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
510 #define FRAC_PLL_LOCK_SEL_MASK BIT(15)
511 #define FRAC_PLL_BYPASS_MASK BIT(14)
512 #define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
513 #define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
514 #define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
515 #define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
516 #define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
517 #define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
518 #define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
519 #define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
521 #define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
522 #define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
523 #define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
524 #define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
526 #define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
527 #define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
528 #define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
529 #define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
531 /* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
532 #define SSCG_PLL_LOCK_MASK BIT(31)
533 #define SSCG_PLL_CLKE_MASK BIT(25)
534 #define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
535 #define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
536 #define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
537 #define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
538 #define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
539 #define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
540 #define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
541 #define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
542 #define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
543 #define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
544 #define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
545 #define SSCG_PLL_PD_MASK BIT(7)
546 #define SSCG_PLL_BYPASS1_MASK BIT(5)
547 #define SSCG_PLL_BYPASS2_MASK BIT(4)
548 #define SSCG_PLL_LOCK_SEL_MASK BIT(3)
549 #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
550 #define SSCG_PLL_REFCLK_SEL_MASK 0x3
551 #define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
552 #define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
553 #define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
554 #define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
556 #define SSCG_PLL_SSDS_MASK BIT(8)
557 #define SSCG_PLL_SSMD_MASK (0x7 << 5)
558 #define SSCG_PLL_SSMF_MASK (0xf << 1)
559 #define SSCG_PLL_SSE_MASK 0x1
561 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
562 #define SSCG_PLL_REF_DIVR1_SHIFT 25
563 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
564 #define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
565 #define SSCG_PLL_REF_DIVR2_SHIFT 19
566 #define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
567 #define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
568 #define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
569 #define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
570 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
571 #define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
572 #define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
573 #define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
574 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
575 #define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
576 #define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
577 #define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
578 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
579 #define SSCG_PLL_FILTER_RANGE_MASK 0x1
581 #define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
582 #define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
583 #define HW_DIGPROG_MINOR_MASK 0xff
585 #define HW_OSC_27M_CLKE_MASK BIT(4)
586 #define HW_OSC_25M_CLKE_MASK BIT(2)
587 #define HW_OSC_32K_SEL_MASK 0x1
588 #define HW_OSC_32K_SEL_RTC 0x1
589 #define HW_OSC_32K_SEL_25M_DIV800 0x0
591 #define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
592 #define HW_FRAC_ARM_PLL_DIV_SHIFT 20
593 #define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
594 #define HW_FRAC_VPU_PLL_DIV_SHIFT 16
595 #define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
596 #define HW_FRAC_GPU_PLL_DIV_SHIFT 12
597 #define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
598 #define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
599 #define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
600 #define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
601 #define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
602 #define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
604 #define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
605 #define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
606 #define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
607 #define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
608 #define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
609 #define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
610 #define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
611 #define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
612 #define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
613 #define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
615 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
616 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
617 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
618 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
619 #define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
620 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
621 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
629 enum frac_pll_out_val {
634 u32 imx_get_fecclk(void);
635 u32 imx_get_uartclk(void);
636 int clock_init(void);
637 void init_clk_usdhc(u32 index);
638 void init_uart_clk(u32 index);
639 void init_wdog_clk(void);
640 unsigned int mxc_get_clock(enum clk_root_index clk);
641 int clock_enable(enum clk_ccgr_index index, bool enable);
642 int clock_root_enabled(enum clk_root_index clock_id);
643 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
644 enum root_post_div post_div, enum clk_root_src clock_src);
645 int clock_set_target_val(enum clk_root_index clock_id, u32 val);
646 int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
647 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
648 int clock_get_postdiv(enum clk_root_index clock_id,
649 enum root_post_div *post_div);
650 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
651 void mxs_set_lcdclk(u32 base_addr, u32 freq);
652 int set_clk_qspi(void);
653 void enable_ocotp_clk(unsigned char enable);
654 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
655 int set_clk_enet(enum enet_freq type);