arch/arm/include/asm/arch-mx6/mx6sx_rdc.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:  GPL-2.0+
   5  */
   6
   7 #ifndef __MX6SX_RDC_H__
   8 #define __MX6SX_RDC_H__
   9
  10 #define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
  11
  12 enum {
  13         RDC_PER_PWM1 = 0,
  14         RDC_PER_PWM2,
  15         RDC_PER_PWM3,
  16         RDC_PER_PWM4,
  17         RDC_PER_CAN1,
  18         RDC_PER_CAN2,
  19         RDC_PER_GPT,
  20         RDC_PER_GPIO1,
  21         RDC_PER_GPIO2,
  22         RDC_PER_GPIO3,
  23         RDC_PER_GPIO4,
  24         RDC_PER_GPIO5,
  25         RDC_PER_GPIO6,
  26         RDC_PER_GPIO7,
  27         RDC_PER_KPP,
  28         RDC_PER_WDOG1,
  29         RDC_PER_WODG2,
  30         RDC_PER_CCM,
  31         RDC_PER_ANATOPDIG,
  32         RDC_PER_SNVSHP,
  33         RDC_PER_EPIT1,
  34         RDC_PER_EPIT2,
  35         RDC_PER_SRC,
  36         RDC_PER_GPC,
  37         RDC_PER_IOMUXC,
  38         RDC_PER_IOMUXCGPR,
  39         RDC_PER_CANFD1,
  40         RDC_PER_SDMA,
  41         RDC_PER_CANFD2,
  42         RDC_PER_SEMA1,
  43         RDC_PER_SEMA2,
  44         RDC_PER_RDC,
  45         RDC_PER_AIPSTZ1_GE1,
  46         RDC_PER_AIPSTZ2_GE2,
  47         RDC_PER_USBO2H_PL301,
  48         RDC_PER_USBO2H_USB,
  49         RDC_PER_ENET1,
  50         RDC_PER_MLB25,
  51         RDC_PER_USDHC1,
  52         RDC_PER_USDHC2,
  53         RDC_PER_USDHC3,
  54         RDC_PER_USDHC4,
  55         RDC_PER_I2C1,
  56         RDC_PER_I2C2,
  57         RDC_PER_I2C3,
  58         RDC_PER_ROMCP,
  59         RDC_PER_MMDC,
  60         RDC_PER_ENET2,
  61         RDC_PER_EIM,
  62         RDC_PER_OCOTP,
  63         RDC_PER_CSU,
  64         RDC_PER_PERFMON1,
  65         RDC_PER_PERFMON2,
  66         RDC_PER_AXIMON,
  67         RDC_PER_TZASC1,
  68         RDC_PER_SAI1,
  69         RDC_PER_AUDMUX,
  70         RDC_PER_SAI2,
  71         RDC_PER_QSPI1,
  72         RDC_PER_QSPI2,
  73         RDC_PER_UART2,
  74         RDC_PER_UART3,
  75         RDC_PER_UART4,
  76         RDC_PER_UART5,
  77         RDC_PER_I2C4,
  78         RDC_PER_QOSC,
  79         RDC_PER_CAAM,
  80         RDC_PER_DAP,
  81         RDC_PER_ADC1,
  82         RDC_PER_ADC2,
  83         RDC_PER_WDOG3,
  84         RDC_PER_ECSPI5,
  85         RDC_PER_SEMA4,
  86         RDC_PER_MUPORT1,
  87         RDC_PER_CANFD_CPU,
  88         RDC_PER_MUPORT2,
  89         RDC_PER_UART6,
  90         RDC_PER_PWM5,
  91         RDC_PER_PWM6,
  92         RDC_PER_PWM7,
  93         RDC_PER_PWM8,
  94         RDC_PER_AIPSTZ3_GE0,
  95         RDC_PER_AIPSTZ3_GE1,
  96         RDC_PER_RESERVED1,
  97         RDC_PER_SPDIF,
  98         RDC_PER_ECSPI1,
  99         RDC_PER_ECSPI2,
 100         RDC_PER_ECSPI3,
 101         RDC_PER_ECSPI4,
 102         RDC_PER_RESERVED2,
 103         RDC_PER_RESERVED3,
 104         RDC_PER_UART1,
 105         RDC_PER_ESAI,
 106         RDC_PER_SSI1,
 107         RDC_PER_SSI2,
 108         RDC_PER_SSI3,
 109         RDC_PER_ASRC,
 110         RDC_PER_RESERVED4,
 111         RDC_PER_SPBA_MA,
 112         RDC_PER_GIS,
 113         RDC_PER_DCIC1,
 114         RDC_PER_DCIC2,
 115         RDC_PER_CSI1,
 116         RDC_PER_PXP,
 117         RDC_PER_CSI2,
 118         RDC_PER_LCDIF1,
 119         RDC_PER_LCDIF2,
 120         RDC_PER_VADC,
 121         RDC_PER_VDEC,
 122         RDC_PER_SPBA_DISPLAYMIX,
 123 };
 124
 125 enum {
 126         RDC_MA_A9_L2CACHE = 0,
 127         RDC_MA_M4,
 128         RDC_MA_GPU,
 129         RDC_MA_CSI1,
 130         RDC_MA_CSI2,
 131         RDC_MA_LCDIF1,
 132         RDC_MA_LCDIF2,
 133         RDC_MA_PXP,
 134         RDC_MA_PCIE_CTRL,
 135         RDC_MA_DAP,
 136         RDC_MA_CAAM,
 137         RDC_MA_SDMA_PERI,
 138         RDC_MA_SDMA_BURST,
 139         RDC_MA_APBHDMA,
 140         RDC_MA_RAWNAND,
 141         RDC_MA_USDHC1,
 142         RDC_MA_USDHC2,
 143         RDC_MA_USDHC3,
 144         RDC_MA_USDHC4,
 145         RDC_MA_USB,
 146         RDC_MA_MLB,
 147         RDC_MA_TEST,
 148         RDC_MA_ENET1_TX,
 149         RDC_MA_ENET1_RX,
 150         RDC_MA_ENET2_TX,
 151         RDC_MA_ENET2_RX,
 152         RDC_MA_SDMA,
 153 };
 154
 155 #endif  /* __MX6SX_RDC_H__*/