imx:mx6 update fuse_bank0_regs
[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h
1 /*
2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
9
10 #define ARCH_MXC
11
12 #define CONFIG_SYS_CACHELINE_SIZE       32
13
14 #define ROMCP_ARB_BASE_ADDR             0x00000000
15 #define ROMCP_ARB_END_ADDR              0x000FFFFF
16
17 #ifdef CONFIG_MX6SL
18 #define GPU_2D_ARB_BASE_ADDR            0x02200000
19 #define GPU_2D_ARB_END_ADDR             0x02203FFF
20 #define OPENVG_ARB_BASE_ADDR            0x02204000
21 #define OPENVG_ARB_END_ADDR             0x02207FFF
22 #elif CONFIG_MX6SX
23 #define CAAM_ARB_BASE_ADDR              0x00100000
24 #define CAAM_ARB_END_ADDR               0x00107FFF
25 #define GPU_ARB_BASE_ADDR               0x01800000
26 #define GPU_ARB_END_ADDR                0x01803FFF
27 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
28 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
29 #define M4_BOOTROM_BASE_ADDR                    0x007F8000
30
31 #define MXS_APBH_BASE                   APBH_DMA_ARB_BASE_ADDR
32 #define MXS_GPMI_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x02000)
33 #define MXS_BCH_BASE                    (APBH_DMA_ARB_BASE_ADDR + 0x04000)
34
35 #else
36 #define CAAM_ARB_BASE_ADDR              0x00100000
37 #define CAAM_ARB_END_ADDR               0x00103FFF
38 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
39 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
40 #define HDMI_ARB_BASE_ADDR              0x00120000
41 #define HDMI_ARB_END_ADDR               0x00128FFF
42 #define GPU_3D_ARB_BASE_ADDR            0x00130000
43 #define GPU_3D_ARB_END_ADDR             0x00133FFF
44 #define GPU_2D_ARB_BASE_ADDR            0x00134000
45 #define GPU_2D_ARB_END_ADDR             0x00137FFF
46 #define DTCP_ARB_BASE_ADDR              0x00138000
47 #define DTCP_ARB_END_ADDR               0x0013BFFF
48 #endif  /* CONFIG_MX6SL */
49
50 #define MXS_APBH_BASE                   APBH_DMA_ARB_BASE_ADDR
51 #define MXS_GPMI_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x02000)
52 #define MXS_BCH_BASE                    (APBH_DMA_ARB_BASE_ADDR + 0x04000)
53
54 /* GPV - PL301 configuration ports */
55 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
56 #define GPV2_BASE_ADDR                  0x00D00000
57 #else
58 #define GPV2_BASE_ADDR                  0x00200000
59 #endif
60
61 #ifdef CONFIG_MX6SX
62 #define GPV3_BASE_ADDR                  0x00E00000
63 #define GPV4_BASE_ADDR                  0x00F00000
64 #define GPV5_BASE_ADDR                  0x01000000
65 #define GPV6_BASE_ADDR                  0x01100000
66 #define PCIE_ARB_BASE_ADDR              0x08000000
67 #define PCIE_ARB_END_ADDR               0x08FFFFFF
68
69 #else
70 #define GPV3_BASE_ADDR                  0x00300000
71 #define GPV4_BASE_ADDR                  0x00800000
72 #define PCIE_ARB_BASE_ADDR              0x01000000
73 #define PCIE_ARB_END_ADDR               0x01FFFFFF
74 #endif
75
76 #define IRAM_BASE_ADDR                  0x00900000
77 #define SCU_BASE_ADDR                   0x00A00000
78 #define IC_INTERFACES_BASE_ADDR         0x00A00100
79 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
80 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
81 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
82 #define L2_PL310_BASE                   0x00A02000
83 #define GPV0_BASE_ADDR                  0x00B00000
84 #define GPV1_BASE_ADDR                  0x00C00000
85
86 #define AIPS1_ARB_BASE_ADDR             0x02000000
87 #define AIPS1_ARB_END_ADDR              0x020FFFFF
88 #define AIPS2_ARB_BASE_ADDR             0x02100000
89 #define AIPS2_ARB_END_ADDR              0x021FFFFF
90 #ifdef CONFIG_MX6SX
91 #define AIPS3_BASE_ADDR                 0x02200000
92 #define AIPS3_END_ADDR                  0x022FFFFF
93 #define WEIM_ARB_BASE_ADDR              0x50000000
94 #define WEIM_ARB_END_ADDR               0x57FFFFFF
95 #define QSPI0_AMBA_BASE                0x60000000
96 #define QSPI0_AMBA_END                 0x6FFFFFFF
97 #define QSPI1_AMBA_BASE                0x70000000
98 #define QSPI1_AMBA_END                 0x7FFFFFFF
99 #else
100 #define SATA_ARB_BASE_ADDR              0x02200000
101 #define SATA_ARB_END_ADDR               0x02203FFF
102 #define OPENVG_ARB_BASE_ADDR            0x02204000
103 #define OPENVG_ARB_END_ADDR             0x02207FFF
104 #define HSI_ARB_BASE_ADDR               0x02208000
105 #define HSI_ARB_END_ADDR                0x0220BFFF
106 #define IPU1_ARB_BASE_ADDR              0x02400000
107 #define IPU1_ARB_END_ADDR               0x027FFFFF
108 #define IPU2_ARB_BASE_ADDR              0x02800000
109 #define IPU2_ARB_END_ADDR               0x02BFFFFF
110 #define WEIM_ARB_BASE_ADDR              0x08000000
111 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
112 #endif
113
114 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
115 #define MMDC0_ARB_BASE_ADDR             0x80000000
116 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
117 #define MMDC1_ARB_BASE_ADDR             0xC0000000
118 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
119 #else
120 #define MMDC0_ARB_BASE_ADDR             0x10000000
121 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
122 #define MMDC1_ARB_BASE_ADDR             0x80000000
123 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
124 #endif
125
126 #ifndef CONFIG_MX6SX
127 #define IPU_SOC_BASE_ADDR               IPU1_ARB_BASE_ADDR
128 #define IPU_SOC_OFFSET                  0x00200000
129 #endif
130
131 /* Defines for Blocks connected via AIPS (SkyBlue) */
132 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
133 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
134 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
135 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
136
137 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
138 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
139 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
140 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
141 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
142 #ifdef CONFIG_MX6SL
143 #define UART5_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x18000)
144 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
145 #define UART2_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x24000)
146 #define SSI1_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x28000)
147 #define SSI2_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x2C000)
148 #define SSI3_IPS_BASE_ADDR          (ATZ1_BASE_ADDR + 0x30000)
149 #define UART3_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x34000)
150 #define UART4_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x38000)
151 #else
152 #ifndef CONFIG_MX6SX
153 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
154 #endif
155 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
156 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
157 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
158 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
159 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
160 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
161 #endif
162
163 #ifndef CONFIG_MX6SX
164 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
165 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
166 #endif
167 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
168
169 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
170 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
171 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
172 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
173 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
174 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
175 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
176 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
177 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
178 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
179 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
180 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
181 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
182 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
183 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
184 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
185 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
186 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
187 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
188 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
189 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
190 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
191 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
192 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
193 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
194 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
195 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
196 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
197 #ifdef CONFIG_MX6SL
198 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
199 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
200 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
201 #elif CONFIG_MX6SX
202 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
203 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
204 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
205 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
206 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
207 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
208 #else
209 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
210 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
211 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
212 #endif
213
214 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
215 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
216 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
217 #define ARM_BASE_ADDR               (ATZ2_BASE_ADDR + 0x40000)
218 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
219 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
220
221 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
222 #ifdef CONFIG_MX6SL
223 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
224 #else
225 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
226 #endif
227
228 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
229 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
230 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
231 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
232 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
233 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
234 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
235 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
236 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
237 #ifdef CONFIG_MX6SL
238 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
239 #elif CONFIG_MX6SX
240 #define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
241 #else
242 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
243 #endif
244
245 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
246 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
247 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
248 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
249 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
250 #ifdef CONFIG_MX6SX
251 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
252 #else
253 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
254 #endif
255 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
256 #ifdef CONFIG_MX6SX
257 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
258 #else
259 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
260 #endif
261 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
262 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
263 #ifdef CONFIG_MX6SX
264 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
265 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
266 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
267 #else
268 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
269 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
270 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
271 #endif
272 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
273 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
274 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
275 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
276 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
277 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
278
279 #ifdef CONFIG_MX6SX
280 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
281 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
282 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
283 #define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
284 #define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
285 #define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
286 #define LCDIF1_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x20000)
287 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
288 #define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
289 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
290 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
291 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
292 #define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
293 #define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
294 #define WDOG3_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x88000)
295 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
296 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
297 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
298 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
299 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
300 #define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
301 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
302 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
303 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
304 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
305 #endif
306
307 #define CHIP_REV_1_0                 0x10
308 #define CHIP_REV_1_2                 0x12
309 #define CHIP_REV_1_5                 0x15
310 #ifndef CONFIG_MX6SX
311 #define IRAM_SIZE                    0x00040000
312 #else
313 #define IRAM_SIZE                    0x00020000
314 #endif
315 #define FEC_QUIRK_ENET_MAC
316
317 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
318 #include <asm/types.h>
319
320 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
321
322 #define SRC_SCR_CORE_1_RESET_OFFSET     14
323 #define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
324 #define SRC_SCR_CORE_2_RESET_OFFSET     15
325 #define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
326 #define SRC_SCR_CORE_3_RESET_OFFSET     16
327 #define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
328 #define SRC_SCR_CORE_1_ENABLE_OFFSET    22
329 #define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
330 #define SRC_SCR_CORE_2_ENABLE_OFFSET    23
331 #define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
332 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
333 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
334
335 /* WEIM registers */
336 struct weim {
337         u32 cs0gcr1;
338         u32 cs0gcr2;
339         u32 cs0rcr1;
340         u32 cs0rcr2;
341         u32 cs0wcr1;
342         u32 cs0wcr2;
343
344         u32 cs1gcr1;
345         u32 cs1gcr2;
346         u32 cs1rcr1;
347         u32 cs1rcr2;
348         u32 cs1wcr1;
349         u32 cs1wcr2;
350
351         u32 cs2gcr1;
352         u32 cs2gcr2;
353         u32 cs2rcr1;
354         u32 cs2rcr2;
355         u32 cs2wcr1;
356         u32 cs2wcr2;
357
358         u32 cs3gcr1;
359         u32 cs3gcr2;
360         u32 cs3rcr1;
361         u32 cs3rcr2;
362         u32 cs3wcr1;
363         u32 cs3wcr2;
364
365         u32 unused[12];
366
367         u32 wcr;
368         u32 wiar;
369         u32 ear;
370 };
371
372 /* System Reset Controller (SRC) */
373 struct src {
374         u32     scr;
375         u32     sbmr1;
376         u32     srsr;
377         u32     reserved1[2];
378         u32     sisr;
379         u32     simr;
380         u32     sbmr2;
381         u32     gpr1;
382         u32     gpr2;
383         u32     gpr3;
384         u32     gpr4;
385         u32     gpr5;
386         u32     gpr6;
387         u32     gpr7;
388         u32     gpr8;
389         u32     gpr9;
390         u32     gpr10;
391 };
392
393 /* GPR1 bitfields */
394 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET         21
395 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK           (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
396 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET           13
397 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK         (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
398
399 /* GPR3 bitfields */
400 #define IOMUXC_GPR3_GPU_DBG_OFFSET              29
401 #define IOMUXC_GPR3_GPU_DBG_MASK                (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
402 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET     28
403 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
404 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET     27
405 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
406 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET  26
407 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
408 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET  25
409 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
410 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET            21
411 #define IOMUXC_GPR3_OCRAM_CTL_MASK              (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
412 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET         17
413 #define IOMUXC_GPR3_OCRAM_STATUS_MASK           (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
414 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET     16
415 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
416 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET     15
417 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
418 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET     14
419 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
420 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET     13
421 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
422 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET     12
423 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
424 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET     11
425 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
426 #define IOMUXC_GPR3_IPU_DIAG_OFFSET             10
427 #define IOMUXC_GPR3_IPU_DIAG_MASK               (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
428
429 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0    0
430 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1    1
431 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0    2
432 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1    3
433
434 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET        8
435 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
436
437 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET        6
438 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
439
440 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET         4
441 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
442
443 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET         2
444 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
445
446
447 struct iomuxc {
448 #ifdef CONFIG_MX6SX
449         u8 reserved[0x4000];
450 #endif
451         u32 gpr[14];
452 };
453
454 struct gpc {
455         u32     cntr;
456         u32     pgr;
457         u32     imr1;
458         u32     imr2;
459         u32     imr3;
460         u32     imr4;
461         u32     isr1;
462         u32     isr2;
463         u32     isr3;
464         u32     isr4;
465 };
466
467 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET            20
468 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK              (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
469 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET               16
470 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                 (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
471
472 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET                 15
473 #define IOMUXC_GPR2_BGREF_RRMODE_MASK                   (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
474 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES           (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
475 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES           (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
476 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH   0
477 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW    1
478
479 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET              10
480 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
481 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
482 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
483
484 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET              9
485 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
486 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
487 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
488
489 #define IOMUXC_GPR2_BITMAP_SPWG 0
490 #define IOMUXC_GPR2_BITMAP_JEIDA        1
491
492 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET              8
493 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
494 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
495 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
496
497 #define IOMUXC_GPR2_DATA_WIDTH_18       0
498 #define IOMUXC_GPR2_DATA_WIDTH_24       1
499
500 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET               7
501 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
502 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
503 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
504
505 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET              6
506 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
507 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
508 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
509
510 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET               5
511 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
512 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
513 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
514
515 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET                4
516 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                  (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
517
518 #define IOMUXC_GPR2_MODE_DISABLED       0
519 #define IOMUXC_GPR2_MODE_ENABLED_DI0    1
520 #define IOMUXC_GPR2_MODE_ENABLED_DI1    3
521
522 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET                2
523 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
524 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
525 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
526 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
527
528 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET                0
529 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
530 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
531 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
532 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
533
534 /* ECSPI registers */
535 struct cspi_regs {
536         u32 rxdata;
537         u32 txdata;
538         u32 ctrl;
539         u32 cfg;
540         u32 intr;
541         u32 dma;
542         u32 stat;
543         u32 period;
544 };
545
546 /*
547  * CSPI register definitions
548  */
549 #define MXC_ECSPI
550 #define MXC_CSPICTRL_EN         (1 << 0)
551 #define MXC_CSPICTRL_MODE       (1 << 1)
552 #define MXC_CSPICTRL_XCH        (1 << 2)
553 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
554 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
555 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
556 #define MXC_CSPICTRL_PREDIV(x)  (((x) & 0xF) << 12)
557 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
558 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
559 #define MXC_CSPICTRL_MAXBITS    0xfff
560 #define MXC_CSPICTRL_TC         (1 << 7)
561 #define MXC_CSPICTRL_RXOVF      (1 << 6)
562 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
563 #define MAX_SPI_BYTES   32
564 #define SPI_MAX_NUM     4
565
566 /* Bit position inside CTRL register to be associated with SS */
567 #define MXC_CSPICTRL_CHAN       18
568
569 /* Bit position inside CON register to be associated with SS */
570 #define MXC_CSPICON_PHA         0  /* SCLK phase control */
571 #define MXC_CSPICON_POL         4  /* SCLK polarity */
572 #define MXC_CSPICON_SSPOL       12 /* SS polarity */
573 #define MXC_CSPICON_CTL         20 /* inactive state of SCLK */
574 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
575 #define MXC_SPI_BASE_ADDRESSES \
576         ECSPI1_BASE_ADDR, \
577         ECSPI2_BASE_ADDR, \
578         ECSPI3_BASE_ADDR, \
579         ECSPI4_BASE_ADDR
580 #else
581 #define MXC_SPI_BASE_ADDRESSES \
582         ECSPI1_BASE_ADDR, \
583         ECSPI2_BASE_ADDR, \
584         ECSPI3_BASE_ADDR, \
585         ECSPI4_BASE_ADDR, \
586         ECSPI5_BASE_ADDR
587 #endif
588
589 struct ocotp_regs {
590         u32     ctrl;
591         u32     ctrl_set;
592         u32     ctrl_clr;
593         u32     ctrl_tog;
594         u32     timing;
595         u32     rsvd0[3];
596         u32     data;
597         u32     rsvd1[3];
598         u32     read_ctrl;
599         u32     rsvd2[3];
600         u32     read_fuse_data;
601         u32     rsvd3[3];
602         u32     sw_sticky;
603         u32     rsvd4[3];
604         u32     scs;
605         u32     scs_set;
606         u32     scs_clr;
607         u32     scs_tog;
608         u32     crc_addr;
609         u32     rsvd5[3];
610         u32     crc_value;
611         u32     rsvd6[3];
612         u32     version;
613         u32     rsvd7[0xdb];
614
615         struct fuse_bank {
616                 u32     fuse_regs[0x20];
617         } bank[16];
618 };
619
620 struct fuse_bank0_regs {
621         u32     lock;
622         u32     rsvd0[3];
623         u32     uid_low;
624         u32     rsvd1[3];
625         u32     uid_high;
626         u32     rsvd2[3];
627         u32     cfg2;
628         u32     rsvd3[3];
629         u32     cfg3;
630         u32     rsvd4[3];
631         u32     cfg4;
632         u32     rsvd5[3];
633         u32     cfg5;
634         u32     rsvd6[3];
635         u32     cfg6;
636         u32     rsvd7[3];
637 };
638
639 #ifdef CONFIG_MX6SX
640 struct fuse_bank4_regs {
641         u32 sjc_resp_low;
642         u32 rsvd0[3];
643         u32 sjc_resp_high;
644         u32 rsvd1[3];
645         u32 mac_addr_low;
646         u32 rsvd2[3];
647         u32 mac_addr_high;
648         u32 rsvd3[3];
649         u32 mac_addr2;
650         u32 rsvd4[7];
651         u32 gp1;
652         u32 rsvd5[7];
653 };
654 #else
655 struct fuse_bank4_regs {
656         u32     sjc_resp_low;
657         u32     rsvd0[3];
658         u32     sjc_resp_high;
659         u32     rsvd1[3];
660         u32     mac_addr_low;
661         u32     rsvd2[3];
662         u32     mac_addr_high;
663         u32     rsvd3[0xb];
664         u32     gp1;
665         u32     rsvd4[3];
666         u32     gp2;
667         u32     rsvd5[3];
668 };
669 #endif
670
671 struct aipstz_regs {
672         u32     mprot0;
673         u32     mprot1;
674         u32     rsvd[0xe];
675         u32     opacr0;
676         u32     opacr1;
677         u32     opacr2;
678         u32     opacr3;
679         u32     opacr4;
680 };
681
682 struct anatop_regs {
683         u32     pll_sys;                /* 0x000 */
684         u32     pll_sys_set;            /* 0x004 */
685         u32     pll_sys_clr;            /* 0x008 */
686         u32     pll_sys_tog;            /* 0x00c */
687         u32     usb1_pll_480_ctrl;      /* 0x010 */
688         u32     usb1_pll_480_ctrl_set;  /* 0x014 */
689         u32     usb1_pll_480_ctrl_clr;  /* 0x018 */
690         u32     usb1_pll_480_ctrl_tog;  /* 0x01c */
691         u32     usb2_pll_480_ctrl;      /* 0x020 */
692         u32     usb2_pll_480_ctrl_set;  /* 0x024 */
693         u32     usb2_pll_480_ctrl_clr;  /* 0x028 */
694         u32     usb2_pll_480_ctrl_tog;  /* 0x02c */
695         u32     pll_528;                /* 0x030 */
696         u32     pll_528_set;            /* 0x034 */
697         u32     pll_528_clr;            /* 0x038 */
698         u32     pll_528_tog;            /* 0x03c */
699         u32     pll_528_ss;             /* 0x040 */
700         u32     rsvd0[3];
701         u32     pll_528_num;            /* 0x050 */
702         u32     rsvd1[3];
703         u32     pll_528_denom;          /* 0x060 */
704         u32     rsvd2[3];
705         u32     pll_audio;              /* 0x070 */
706         u32     pll_audio_set;          /* 0x074 */
707         u32     pll_audio_clr;          /* 0x078 */
708         u32     pll_audio_tog;          /* 0x07c */
709         u32     pll_audio_num;          /* 0x080 */
710         u32     rsvd3[3];
711         u32     pll_audio_denom;        /* 0x090 */
712         u32     rsvd4[3];
713         u32     pll_video;              /* 0x0a0 */
714         u32     pll_video_set;          /* 0x0a4 */
715         u32     pll_video_clr;          /* 0x0a8 */
716         u32     pll_video_tog;          /* 0x0ac */
717         u32     pll_video_num;          /* 0x0b0 */
718         u32     rsvd5[3];
719         u32     pll_video_denom;        /* 0x0c0 */
720         u32     rsvd6[3];
721         u32     pll_mlb;                /* 0x0d0 */
722         u32     pll_mlb_set;            /* 0x0d4 */
723         u32     pll_mlb_clr;            /* 0x0d8 */
724         u32     pll_mlb_tog;            /* 0x0dc */
725         u32     pll_enet;               /* 0x0e0 */
726         u32     pll_enet_set;           /* 0x0e4 */
727         u32     pll_enet_clr;           /* 0x0e8 */
728         u32     pll_enet_tog;           /* 0x0ec */
729         u32     pfd_480;                /* 0x0f0 */
730         u32     pfd_480_set;            /* 0x0f4 */
731         u32     pfd_480_clr;            /* 0x0f8 */
732         u32     pfd_480_tog;            /* 0x0fc */
733         u32     pfd_528;                /* 0x100 */
734         u32     pfd_528_set;            /* 0x104 */
735         u32     pfd_528_clr;            /* 0x108 */
736         u32     pfd_528_tog;            /* 0x10c */
737         u32     reg_1p1;                /* 0x110 */
738         u32     reg_1p1_set;            /* 0x114 */
739         u32     reg_1p1_clr;            /* 0x118 */
740         u32     reg_1p1_tog;            /* 0x11c */
741         u32     reg_3p0;                /* 0x120 */
742         u32     reg_3p0_set;            /* 0x124 */
743         u32     reg_3p0_clr;            /* 0x128 */
744         u32     reg_3p0_tog;            /* 0x12c */
745         u32     reg_2p5;                /* 0x130 */
746         u32     reg_2p5_set;            /* 0x134 */
747         u32     reg_2p5_clr;            /* 0x138 */
748         u32     reg_2p5_tog;            /* 0x13c */
749         u32     reg_core;               /* 0x140 */
750         u32     reg_core_set;           /* 0x144 */
751         u32     reg_core_clr;           /* 0x148 */
752         u32     reg_core_tog;           /* 0x14c */
753         u32     ana_misc0;              /* 0x150 */
754         u32     ana_misc0_set;          /* 0x154 */
755         u32     ana_misc0_clr;          /* 0x158 */
756         u32     ana_misc0_tog;          /* 0x15c */
757         u32     ana_misc1;              /* 0x160 */
758         u32     ana_misc1_set;          /* 0x164 */
759         u32     ana_misc1_clr;          /* 0x168 */
760         u32     ana_misc1_tog;          /* 0x16c */
761         u32     ana_misc2;              /* 0x170 */
762         u32     ana_misc2_set;          /* 0x174 */
763         u32     ana_misc2_clr;          /* 0x178 */
764         u32     ana_misc2_tog;          /* 0x17c */
765         u32     tempsense0;             /* 0x180 */
766         u32     tempsense0_set;         /* 0x184 */
767         u32     tempsense0_clr;         /* 0x188 */
768         u32     tempsense0_tog;         /* 0x18c */
769         u32     tempsense1;             /* 0x190 */
770         u32     tempsense1_set;         /* 0x194 */
771         u32     tempsense1_clr;         /* 0x198 */
772         u32     tempsense1_tog;         /* 0x19c */
773         u32     usb1_vbus_detect;       /* 0x1a0 */
774         u32     usb1_vbus_detect_set;   /* 0x1a4 */
775         u32     usb1_vbus_detect_clr;   /* 0x1a8 */
776         u32     usb1_vbus_detect_tog;   /* 0x1ac */
777         u32     usb1_chrg_detect;       /* 0x1b0 */
778         u32     usb1_chrg_detect_set;   /* 0x1b4 */
779         u32     usb1_chrg_detect_clr;   /* 0x1b8 */
780         u32     usb1_chrg_detect_tog;   /* 0x1bc */
781         u32     usb1_vbus_det_stat;     /* 0x1c0 */
782         u32     usb1_vbus_det_stat_set; /* 0x1c4 */
783         u32     usb1_vbus_det_stat_clr; /* 0x1c8 */
784         u32     usb1_vbus_det_stat_tog; /* 0x1cc */
785         u32     usb1_chrg_det_stat;     /* 0x1d0 */
786         u32     usb1_chrg_det_stat_set; /* 0x1d4 */
787         u32     usb1_chrg_det_stat_clr; /* 0x1d8 */
788         u32     usb1_chrg_det_stat_tog; /* 0x1dc */
789         u32     usb1_loopback;          /* 0x1e0 */
790         u32     usb1_loopback_set;      /* 0x1e4 */
791         u32     usb1_loopback_clr;      /* 0x1e8 */
792         u32     usb1_loopback_tog;      /* 0x1ec */
793         u32     usb1_misc;              /* 0x1f0 */
794         u32     usb1_misc_set;          /* 0x1f4 */
795         u32     usb1_misc_clr;          /* 0x1f8 */
796         u32     usb1_misc_tog;          /* 0x1fc */
797         u32     usb2_vbus_detect;       /* 0x200 */
798         u32     usb2_vbus_detect_set;   /* 0x204 */
799         u32     usb2_vbus_detect_clr;   /* 0x208 */
800         u32     usb2_vbus_detect_tog;   /* 0x20c */
801         u32     usb2_chrg_detect;       /* 0x210 */
802         u32     usb2_chrg_detect_set;   /* 0x214 */
803         u32     usb2_chrg_detect_clr;   /* 0x218 */
804         u32     usb2_chrg_detect_tog;   /* 0x21c */
805         u32     usb2_vbus_det_stat;     /* 0x220 */
806         u32     usb2_vbus_det_stat_set; /* 0x224 */
807         u32     usb2_vbus_det_stat_clr; /* 0x228 */
808         u32     usb2_vbus_det_stat_tog; /* 0x22c */
809         u32     usb2_chrg_det_stat;     /* 0x230 */
810         u32     usb2_chrg_det_stat_set; /* 0x234 */
811         u32     usb2_chrg_det_stat_clr; /* 0x238 */
812         u32     usb2_chrg_det_stat_tog; /* 0x23c */
813         u32     usb2_loopback;          /* 0x240 */
814         u32     usb2_loopback_set;      /* 0x244 */
815         u32     usb2_loopback_clr;      /* 0x248 */
816         u32     usb2_loopback_tog;      /* 0x24c */
817         u32     usb2_misc;              /* 0x250 */
818         u32     usb2_misc_set;          /* 0x254 */
819         u32     usb2_misc_clr;          /* 0x258 */
820         u32     usb2_misc_tog;          /* 0x25c */
821         u32     digprog;                /* 0x260 */
822         u32     reserved1[7];
823         u32     digprog_sololite;       /* 0x280 */
824 };
825
826 #define ANATOP_PFD_FRAC_SHIFT(n)        ((n)*8)
827 #define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
828 #define ANATOP_PFD_STABLE_SHIFT(n)      (6+((n)*8))
829 #define ANATOP_PFD_STABLE_MASK(n)       (1<<ANATOP_PFD_STABLE_SHIFT(n))
830 #define ANATOP_PFD_CLKGATE_SHIFT(n)     (7+((n)*8))
831 #define ANATOP_PFD_CLKGATE_MASK(n)      (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
832
833 struct wdog_regs {
834         u16     wcr;    /* Control */
835         u16     wsr;    /* Service */
836         u16     wrsr;   /* Reset Status */
837         u16     wicr;   /* Interrupt Control */
838         u16     wmcr;   /* Miscellaneous Control */
839 };
840
841 #define PWMCR_PRESCALER(x)      (((x - 1) & 0xFFF) << 4)
842 #define PWMCR_DOZEEN            (1 << 24)
843 #define PWMCR_WAITEN            (1 << 23)
844 #define PWMCR_DBGEN             (1 << 22)
845 #define PWMCR_CLKSRC_IPG_HIGH   (2 << 16)
846 #define PWMCR_CLKSRC_IPG        (1 << 16)
847 #define PWMCR_EN                (1 << 0)
848
849 struct pwm_regs {
850         u32     cr;
851         u32     sr;
852         u32     ir;
853         u32     sar;
854         u32     pr;
855         u32     cnr;
856 };
857 #endif /* __ASSEMBLER__*/
858 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */