1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
11 #include <linux/bitops.h>
19 #define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
20 #define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
22 #define MESON_SD_EMMC_CLOCK 0x00
23 #define CLK_MAX_DIV 63
24 #define CLK_SRC_24M (0 << 6)
25 #define CLK_SRC_DIV2 (1 << 6)
26 #define CLK_CO_PHASE_000 (0 << 8)
27 #define CLK_CO_PHASE_090 (1 << 8)
28 #define CLK_CO_PHASE_180 (2 << 8)
29 #define CLK_CO_PHASE_270 (3 << 8)
30 #define CLK_TX_PHASE_000 (0 << 10)
31 #define CLK_TX_PHASE_090 (1 << 10)
32 #define CLK_TX_PHASE_180 (2 << 10)
33 #define CLK_TX_PHASE_270 (3 << 10)
34 #define CLK_ALWAYS_ON BIT(24)
36 #define MESON_SD_EMMC_CFG 0x44
37 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
38 #define CFG_BUS_WIDTH_1 0
39 #define CFG_BUS_WIDTH_4 1
40 #define CFG_BUS_WIDTH_8 2
41 #define CFG_BL_LEN_MASK GENMASK(7, 4)
42 #define CFG_BL_LEN_SHIFT 4
43 #define CFG_BL_LEN_512 (9 << 4)
44 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
45 #define CFG_RESP_TIMEOUT_256 (8 << 8)
46 #define CFG_RC_CC_MASK GENMASK(15, 12)
47 #define CFG_RC_CC_16 (4 << 12)
48 #define CFG_SDCLK_ALWAYS_ON BIT(18)
49 #define CFG_AUTO_CLK BIT(23)
51 #define MESON_SD_EMMC_STATUS 0x48
52 #define STATUS_MASK GENMASK(15, 0)
53 #define STATUS_ERR_MASK GENMASK(12, 0)
54 #define STATUS_RXD_ERR_MASK GENMASK(7, 0)
55 #define STATUS_TXD_ERR BIT(8)
56 #define STATUS_DESC_ERR BIT(9)
57 #define STATUS_RESP_ERR BIT(10)
58 #define STATUS_RESP_TIMEOUT BIT(11)
59 #define STATUS_DESC_TIMEOUT BIT(12)
60 #define STATUS_END_OF_CHAIN BIT(13)
62 #define MESON_SD_EMMC_IRQ_EN 0x4c
64 #define MESON_SD_EMMC_CMD_CFG 0x50
65 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
66 #define CMD_CFG_BLOCK_MODE BIT(9)
67 #define CMD_CFG_R1B BIT(10)
68 #define CMD_CFG_END_OF_CHAIN BIT(11)
69 #define CMD_CFG_TIMEOUT_4S (12 << 12)
70 #define CMD_CFG_NO_RESP BIT(16)
71 #define CMD_CFG_DATA_IO BIT(18)
72 #define CMD_CFG_DATA_WR BIT(19)
73 #define CMD_CFG_RESP_NOCRC BIT(20)
74 #define CMD_CFG_RESP_128 BIT(21)
75 #define CMD_CFG_CMD_INDEX_SHIFT 24
76 #define CMD_CFG_OWNER BIT(31)
78 #define MESON_SD_EMMC_CMD_ARG 0x54
79 #define MESON_SD_EMMC_CMD_DAT 0x58
80 #define MESON_SD_EMMC_CMD_RSP 0x5c
81 #define MESON_SD_EMMC_CMD_RSP1 0x60
82 #define MESON_SD_EMMC_CMD_RSP2 0x64
83 #define MESON_SD_EMMC_CMD_RSP3 0x68
85 struct meson_mmc_platdata {
86 struct mmc_config cfg;