Merge branch 'master' of git://git.denx.de/u-boot-arm
[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-ls102xa / immap_ls102xa.h
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
8 #define __ASM_ARCH_LS102XA_IMMAP_H_
9
10 #define SVR_MAJ(svr)            (((svr) >>  4) & 0xf)
11 #define SVR_MIN(svr)            (((svr) >>  0) & 0xf)
12 #define SVR_SOC_VER(svr)        (((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr)     (svr & 0x80000)
14
15 #define SOC_VER_SLS1020         0x00
16 #define SOC_VER_LS1020          0x10
17 #define SOC_VER_LS1021          0x11
18 #define SOC_VER_LS1022          0x12
19
20 #define RCWSR0_SYS_PLL_RAT_SHIFT        25
21 #define RCWSR0_SYS_PLL_RAT_MASK         0x1f
22 #define RCWSR0_MEM_PLL_RAT_SHIFT        16
23 #define RCWSR0_MEM_PLL_RAT_MASK         0x3f
24
25 #define RCWSR4_SRDS1_PRTCL_SHIFT        24
26 #define RCWSR4_SRDS1_PRTCL_MASK         0xff000000
27
28 #define TIMER_COMP_VAL                  0xffffffff
29 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
30 #define SYS_COUNTER_CTRL_ENABLE         (1 << 24)
31
32 struct sys_info {
33         unsigned long freq_processor[CONFIG_MAX_CPUS];
34         unsigned long freq_systembus;
35         unsigned long freq_ddrbus;
36         unsigned long freq_localbus;
37 };
38
39 /* Device Configuration and Pin Control */
40 struct ccsr_gur {
41         u32     porsr1;         /* POR status 1 */
42         u32     porsr2;         /* POR status 2 */
43         u8      res_008[0x20-0x8];
44         u32     gpporcr1;       /* General-purpose POR configuration */
45         u32     gpporcr2;
46         u32     dcfg_fusesr;    /* Fuse status register */
47         u8      res_02c[0x70-0x2c];
48         u32     devdisr;        /* Device disable control */
49         u32     devdisr2;       /* Device disable control 2 */
50         u32     devdisr3;       /* Device disable control 3 */
51         u32     devdisr4;       /* Device disable control 4 */
52         u32     devdisr5;       /* Device disable control 5 */
53         u8      res_084[0x94-0x84];
54         u32     coredisru;      /* uppper portion for support of 64 cores */
55         u32     coredisrl;      /* lower portion for support of 64 cores */
56         u8      res_09c[0xa4-0x9c];
57         u32     svr;            /* System version */
58         u8      res_0a8[0xb0-0xa8];
59         u32     rstcr;          /* Reset control */
60         u32     rstrqpblsr;     /* Reset request preboot loader status */
61         u8      res_0b8[0xc0-0xb8];
62         u32     rstrqmr1;       /* Reset request mask */
63         u8      res_0c4[0xc8-0xc4];
64         u32     rstrqsr1;       /* Reset request status */
65         u8      res_0cc[0xd4-0xcc];
66         u32     rstrqwdtmrl;    /* Reset request WDT mask */
67         u8      res_0d8[0xdc-0xd8];
68         u32     rstrqwdtsrl;    /* Reset request WDT status */
69         u8      res_0e0[0xe4-0xe0];
70         u32     brrl;           /* Boot release */
71         u8      res_0e8[0x100-0xe8];
72         u32     rcwsr[16];      /* Reset control word status */
73         u8      res_140[0x200-0x140];
74         u32     scratchrw[4];  /* Scratch Read/Write */
75         u8      res_210[0x300-0x210];
76         u32     scratchw1r[4];  /* Scratch Read (Write once) */
77         u8      res_310[0x400-0x310];
78         u32     crstsr;
79         u8      res_404[0x550-0x404];
80         u32     sataliodnr;
81         u8      res_554[0x604-0x554];
82         u32     pamubypenr;
83         u32     dmacr1;
84         u8      res_60c[0x740-0x60c];   /* add more registers when needed */
85         u32     tp_ityp[64];    /* Topology Initiator Type Register */
86         struct {
87                 u32     upper;
88                 u32     lower;
89         } tp_cluster[1];        /* Core Cluster n Topology Register */
90         u8      res_848[0xe60-0x848];
91         u32     ddrclkdr;
92         u8      res_e60[0xe68-0xe64];
93         u32     ifcclkdr;
94         u8      res_e68[0xe80-0xe6c];
95         u32     sdhcpcr;
96 };
97
98 #define SCFG_SCFGREVCR_REV              0xffffffff
99 #define SCFG_SCFGREVCR_NOREV            0
100 #define SCFG_ETSECDMAMCR_LE_BD_FR       0xf8001a0f
101 #define SCFG_ETSECCMCR_GE2_CLK125       0x04000000
102 #define SCFG_PIXCLKCR_PXCKEN            0x80000000
103
104 /* Supplemental Configuration Unit */
105 struct ccsr_scfg {
106         u32 dpslpcr;
107         u32 resv0[2];
108         u32 etsecclkdpslpcr;
109         u32 resv1[5];
110         u32 fuseovrdcr;
111         u32 pixclkcr;
112         u32 resv2[5];
113         u32 spimsicr;
114         u32 resv3[6];
115         u32 pex1pmwrcr;
116         u32 pex1pmrdsr;
117         u32 resv4[3];
118         u32 usb3prm1cr;
119         u32 usb4prm2cr;
120         u32 pex1rdmsgpldlsbsr;
121         u32 pex1rdmsgpldmsbsr;
122         u32 pex2rdmsgpldlsbsr;
123         u32 pex2rdmsgpldmsbsr;
124         u32 pex1rdmmsgrqsr;
125         u32 pex2rdmmsgrqsr;
126         u32 spimsiclrcr;
127         u32 pex1mscportsr;
128         u32 pex2mscportsr;
129         u32 pex2pmwrcr;
130         u32 resv5[24];
131         u32 mac1_streamid;
132         u32 mac2_streamid;
133         u32 mac3_streamid;
134         u32 pex1_streamid;
135         u32 pex2_streamid;
136         u32 dma_streamid;
137         u32 sata_streamid;
138         u32 usb3_streamid;
139         u32 qe_streamid;
140         u32 sdhc_streamid;
141         u32 adma_streamid;
142         u32 letechsftrstcr;
143         u32 core0_sft_rst;
144         u32 core1_sft_rst;
145         u32 resv6[1];
146         u32 usb_hi_addr;
147         u32 etsecclkadjcr;
148         u32 sai_clk;
149         u32 resv7[1];
150         u32 dcu_streamid;
151         u32 usb2_streamid;
152         u32 ftm_reset;
153         u32 altcbar;
154         u32 qspi_cfg;
155         u32 pmcintecr;
156         u32 pmcintlecr;
157         u32 pmcintsr;
158         u32 qos1;
159         u32 qos2;
160         u32 qos3;
161         u32 cci_cfg;
162         u32 resv8[1];
163         u32 etsecdmamcr;
164         u32 usb3prm3cr;
165         u32 resv9[1];
166         u32 debug_streamid;
167         u32 resv10[5];
168         u32 snpcnfgcr;
169         u32 resv11[1];
170         u32 intpcr;
171         u32 resv12[20];
172         u32 scfgrevcr;
173         u32 coresrencr;
174         u32 pex2pmrdsr;
175         u32 ddrc1cr;
176         u32 ddrc2cr;
177         u32 ddrc3cr;
178         u32 ddrc4cr;
179         u32 ddrgcr;
180         u32 resv13[120];
181         u32 qeioclkcr;
182         u32 etsecmcr;
183         u32 sdhciovserlcr;
184         u32 resv14[61];
185         u32 sparecr;
186 };
187
188 /* Clocking */
189 struct ccsr_clk {
190         struct {
191                 u32 clkcncsr;   /* core cluster n clock control status */
192                 u8  res_004[0x1c];
193         } clkcsr[2];
194         u8      res_040[0x7c0]; /* 0x100 */
195         struct {
196                 u32 pllcngsr;
197                 u8 res_804[0x1c];
198         } pllcgsr[2];
199         u8      res_840[0x1c0];
200         u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
201         u8      res_a04[0x1fc];
202         u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
203         u8      res_c04[0x1c];
204         u32     plldgsr;        /* 0xc20 DDR PLL General Status */
205         u8      res_c24[0x3dc];
206 };
207
208 /* System Counter */
209 struct sctr_regs {
210         u32 cntcr;
211         u32 cntsr;
212         u32 cntcv1;
213         u32 cntcv2;
214         u32 resv1[4];
215         u32 cntfid0;
216         u32 cntfid1;
217         u32 resv2[1002];
218         u32 counterid[12];
219 };
220
221 #define MAX_SERDES                      1
222 #define SRDS_MAX_LANES                  4
223 #define SRDS_MAX_BANK                   2
224
225 #define SRDS_RSTCTL_RST                 0x80000000
226 #define SRDS_RSTCTL_RSTDONE             0x40000000
227 #define SRDS_RSTCTL_RSTERR              0x20000000
228 #define SRDS_RSTCTL_SWRST               0x10000000
229 #define SRDS_RSTCTL_SDEN                0x00000020
230 #define SRDS_RSTCTL_SDRST_B             0x00000040
231 #define SRDS_RSTCTL_PLLRST_B            0x00000080
232 #define SRDS_PLLCR0_POFF                0x80000000
233 #define SRDS_PLLCR0_RFCK_SEL_MASK       0x70000000
234 #define SRDS_PLLCR0_RFCK_SEL_100        0x00000000
235 #define SRDS_PLLCR0_RFCK_SEL_125        0x10000000
236 #define SRDS_PLLCR0_RFCK_SEL_156_25     0x20000000
237 #define SRDS_PLLCR0_RFCK_SEL_150        0x30000000
238 #define SRDS_PLLCR0_RFCK_SEL_161_13     0x40000000
239 #define SRDS_PLLCR0_RFCK_SEL_122_88     0x50000000
240 #define SRDS_PLLCR0_PLL_LCK             0x00800000
241 #define SRDS_PLLCR0_FRATE_SEL_MASK      0x000f0000
242 #define SRDS_PLLCR0_FRATE_SEL_5         0x00000000
243 #define SRDS_PLLCR0_FRATE_SEL_3_75      0x00050000
244 #define SRDS_PLLCR0_FRATE_SEL_5_15      0x00060000
245 #define SRDS_PLLCR0_FRATE_SEL_4         0x00070000
246 #define SRDS_PLLCR0_FRATE_SEL_3_12      0x00090000
247 #define SRDS_PLLCR0_FRATE_SEL_3         0x000a0000
248 #define SRDS_PLLCR1_PLL_BWSEL           0x08000000
249
250 struct ccsr_serdes {
251         struct {
252                 u32     rstctl; /* Reset Control Register */
253
254                 u32     pllcr0; /* PLL Control Register 0 */
255
256                 u32     pllcr1; /* PLL Control Register 1 */
257                 u32     res_0c; /* 0x00c */
258                 u32     pllcr3;
259                 u32     pllcr4;
260                 u8      res_18[0x20-0x18];
261         } bank[2];
262         u8      res_40[0x90-0x40];
263         u32     srdstcalcr;     /* 0x90 TX Calibration Control */
264         u8      res_94[0xa0-0x94];
265         u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
266         u8      res_a4[0xb0-0xa4];
267         u32     srdsgr0;        /* 0xb0 General Register 0 */
268         u8      res_b4[0xe0-0xb4];
269         u32     srdspccr0;      /* 0xe0 Protocol Converter Config 0 */
270         u32     srdspccr1;      /* 0xe4 Protocol Converter Config 1 */
271         u32     srdspccr2;      /* 0xe8 Protocol Converter Config 2 */
272         u32     srdspccr3;      /* 0xec Protocol Converter Config 3 */
273         u32     srdspccr4;      /* 0xf0 Protocol Converter Config 4 */
274         u8      res_f4[0x100-0xf4];
275         struct {
276                 u32     lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
277                 u8      res_104[0x120-0x104];
278         } srdslnpssr[4];
279         u8      res_180[0x300-0x180];
280         u32     srdspexeqcr;
281         u32     srdspexeqpcr[11];
282         u8      res_330[0x400-0x330];
283         u32     srdspexapcr;
284         u8      res_404[0x440-0x404];
285         u32     srdspexbpcr;
286         u8      res_444[0x800-0x444];
287         struct {
288                 u32     gcr0;   /* 0x800 General Control Register 0 */
289                 u32     gcr1;   /* 0x804 General Control Register 1 */
290                 u32     gcr2;   /* 0x808 General Control Register 2 */
291                 u32     sscr0;
292                 u32     recr0;  /* 0x810 Receive Equalization Control */
293                 u32     recr1;
294                 u32     tecr0;  /* 0x818 Transmit Equalization Control */
295                 u32     sscr1;
296                 u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
297                 u8      res_824[0x83c-0x824];
298                 u32     tcsr3;
299         } lane[4];      /* Lane A, B, C, D, E, F, G, H */
300         u8      res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
301 };
302
303 #define DDR_SDRAM_CFG                   0x470c0008
304 #define DDR_CS0_BNDS                    0x008000bf
305 #define DDR_CS0_CONFIG                  0x80014302
306 #define DDR_TIMING_CFG_0                0x50550004
307 #define DDR_TIMING_CFG_1                0xbcb38c56
308 #define DDR_TIMING_CFG_2                0x0040d120
309 #define DDR_TIMING_CFG_3                0x010e1000
310 #define DDR_TIMING_CFG_4                0x00000001
311 #define DDR_TIMING_CFG_5                0x03401400
312 #define DDR_SDRAM_CFG_2                 0x00401010
313 #define DDR_SDRAM_MODE                  0x00061c60
314 #define DDR_SDRAM_MODE_2                0x00180000
315 #define DDR_SDRAM_INTERVAL              0x18600618
316 #define DDR_DDR_WRLVL_CNTL              0x8655f605
317 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
318 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
319 #define DDR_DDR_CDR1                    0x80040000
320 #define DDR_DDR_CDR2                    0x00000001
321 #define DDR_SDRAM_CLK_CNTL              0x02000000
322 #define DDR_DDR_ZQ_CNTL                 0x89080600
323 #define DDR_CS0_CONFIG_2                0
324 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
325
326 /* DDR memory controller registers */
327 struct ccsr_ddr {
328         u32 cs0_bnds;                   /* Chip Select 0 Memory Bounds */
329         u32 resv1[1];
330         u32 cs1_bnds;                   /* Chip Select 1 Memory Bounds */
331         u32 resv2[1];
332         u32 cs2_bnds;                   /* Chip Select 2 Memory Bounds */
333         u32 resv3[1];
334         u32 cs3_bnds;                   /* Chip Select 3 Memory Bounds */
335         u32 resv4[25];
336         u32 cs0_config;                 /* Chip Select Configuration */
337         u32 cs1_config;                 /* Chip Select Configuration */
338         u32 cs2_config;                 /* Chip Select Configuration */
339         u32 cs3_config;                 /* Chip Select Configuration */
340         u32 resv5[12];
341         u32 cs0_config_2;               /* Chip Select Configuration 2 */
342         u32 cs1_config_2;               /* Chip Select Configuration 2 */
343         u32 cs2_config_2;               /* Chip Select Configuration 2 */
344         u32 cs3_config_2;               /* Chip Select Configuration 2 */
345         u32 resv6[12];
346         u32 timing_cfg_3;               /* SDRAM Timing Configuration 3 */
347         u32 timing_cfg_0;               /* SDRAM Timing Configuration 0 */
348         u32 timing_cfg_1;               /* SDRAM Timing Configuration 1 */
349         u32 timing_cfg_2;               /* SDRAM Timing Configuration 2 */
350         u32 sdram_cfg;                  /* SDRAM Control Configuration */
351         u32 sdram_cfg_2;                /* SDRAM Control Configuration 2 */
352         u32 sdram_mode;                 /* SDRAM Mode Configuration */
353         u32 sdram_mode_2;               /* SDRAM Mode Configuration 2 */
354         u32 sdram_md_cntl;              /* SDRAM Mode Control */
355         u32 sdram_interval;             /* SDRAM Interval Configuration */
356         u32 sdram_data_init;            /* SDRAM Data initialization */
357         u32 resv7[1];
358         u32 sdram_clk_cntl;             /* SDRAM Clock Control */
359         u32 resv8[5];
360         u32 init_addr;                  /* training init addr */
361         u32 init_ext_addr;              /* training init extended addr */
362         u32 resv9[4];
363         u32 timing_cfg_4;               /* SDRAM Timing Configuration 4 */
364         u32 timing_cfg_5;               /* SDRAM Timing Configuration 5 */
365         u32 timing_cfg_6;               /* SDRAM Timing Configuration 6 */
366         u32 timing_cfg_7;               /* SDRAM Timing Configuration 7 */
367         u32 ddr_zq_cntl;                /* ZQ calibration control*/
368         u32 ddr_wrlvl_cntl;             /* write leveling control*/
369         u32 resv10[1];
370         u32 ddr_sr_cntr;                /* self refresvh counter */
371         u32 ddr_sdram_rcw_1;            /* Control Words 1 */
372         u32 ddr_sdram_rcw_2;            /* Control Words 2 */
373         u32 resv11[2];
374         u32 ddr_wrlvl_cntl_2;           /* write leveling control 2 */
375         u32 ddr_wrlvl_cntl_3;           /* write leveling control 3 */
376         u32 resv12[2];
377         u32 ddr_sdram_rcw_3;            /* Control Words 3 */
378         u32 ddr_sdram_rcw_4;            /* Control Words 4 */
379         u32 ddr_sdram_rcw_5;            /* Control Words 5 */
380         u32 ddr_sdram_rcw_6;            /* Control Words 6 */
381         u32 resv13[20];
382         u32 sdram_mode_3;               /* SDRAM Mode Configuration 3 */
383         u32 sdram_mode_4;               /* SDRAM Mode Configuration 4 */
384         u32 sdram_mode_5;               /* SDRAM Mode Configuration 5 */
385         u32 sdram_mode_6;               /* SDRAM Mode Configuration 6 */
386         u32 sdram_mode_7;               /* SDRAM Mode Configuration 7 */
387         u32 sdram_mode_8;               /* SDRAM Mode Configuration 8 */
388         u32 sdram_mode_9;               /* SDRAM Mode Configuration 9 */
389         u32 sdram_mode_10;              /* SDRAM Mode Configuration 10 */
390         u32 sdram_mode_11;              /* SDRAM Mode Configuration 11 */
391         u32 sdram_mode_12;              /* SDRAM Mode Configuration 12 */
392         u32 sdram_mode_13;              /* SDRAM Mode Configuration 13 */
393         u32 sdram_mode_14;              /* SDRAM Mode Configuration 14 */
394         u32 sdram_mode_15;              /* SDRAM Mode Configuration 15 */
395         u32 sdram_mode_16;              /* SDRAM Mode Configuration 16 */
396         u32 resv14[4];
397         u32 timing_cfg_8;               /* SDRAM Timing Configuration 8 */
398         u32 timing_cfg_9;               /* SDRAM Timing Configuration 9 */
399         u32 resv15[2];
400         u32 sdram_cfg_3;                /* SDRAM Control Configuration 3 */
401         u32 resv16[15];
402         u32 deskew_cntl;                /* SDRAM Deskew Control */
403         u32 resv17[545];
404         u32 ddr_dsr1;                   /* Debug Status 1 */
405         u32 ddr_dsr2;                   /* Debug Status 2 */
406         u32 ddr_cdr1;                   /* Control Driver 1 */
407         u32 ddr_cdr2;                   /* Control Driver 2 */
408         u32 resv18[50];
409         u32 ip_rev1;                    /* IP Block Revision 1 */
410         u32 ip_rev2;                    /* IP Block Revision 2 */
411         u32 eor;                        /* Enhanced Optimization Register */
412         u32 resv19[63];
413         u32 mtcr;                       /* Memory Test Control Register */
414         u32 resv20[7];
415         u32 mtp1;                       /* Memory Test Pattern 1 */
416         u32 mtp2;                       /* Memory Test Pattern 2 */
417         u32 mtp3;                       /* Memory Test Pattern 3 */
418         u32 mtp4;                       /* Memory Test Pattern 4 */
419         u32 mtp5;                       /* Memory Test Pattern 5 */
420         u32 mtp6;                       /* Memory Test Pattern 6 */
421         u32 mtp7;                       /* Memory Test Pattern 7 */
422         u32 mtp8;                       /* Memory Test Pattern 8 */
423         u32 mtp9;                       /* Memory Test Pattern 9 */
424         u32 mtp10;                      /* Memory Test Pattern 10 */
425         u32 resv21[6];
426         u32 ddr_mt_st_ext_addr;         /* Memory Test Start Extended Address */
427         u32 ddr_mt_st_addr;             /* Memory Test Start Address */
428         u32 ddr_mt_end_ext_addr;        /* Memory Test End Extended Address */
429         u32 ddr_mt_end_addr;            /* Memory Test End Address */
430         u32 resv22[36];
431         u32 data_err_inject_hi;         /* Data Path Err Injection Mask High */
432         u32 data_err_inject_lo;         /* Data Path Err Injection Mask Low */
433         u32 ecc_err_inject;             /* Data Path Err Injection Mask ECC */
434         u32 resv23[5];
435         u32 capture_data_hi;            /* Data Path Read Capture High */
436         u32 capture_data_lo;            /* Data Path Read Capture Low */
437         u32 capture_ecc;                /* Data Path Read Capture ECC */
438         u32 resv24[5];
439         u32 err_detect;                 /* Error Detect */
440         u32 err_disable;                /* Error Disable */
441         u32 err_int_en;
442         u32 capture_attributes;         /* Error Attrs Capture */
443         u32 capture_address;            /* Error Addr Capture */
444         u32 capture_ext_address;        /* Error Extended Addr Capture */
445         u32 err_sbe;                    /* Single-Bit ECC Error Management */
446         u32 resv25[105];
447 };
448
449 #define CCI400_CTRLORD_TERM_BARRIER     0x00000008
450 #define CCI400_CTRLORD_EN_BARRIER       0
451
452 /* CCI-400 registers */
453 struct ccsr_cci400 {
454         u32 ctrl_ord;                   /* Control Override */
455         u32 spec_ctrl;                  /* Speculation Control */
456         u32 secure_access;              /* Secure Access */
457         u32 status;                     /* Status */
458         u32 impr_err;                   /* Imprecise Error */
459         u8 res_14[0x100 - 0x14];
460         u32 pmcr;                       /* Performance Monitor Control */
461         u8 res_104[0xfd0 - 0x104];
462         u32 pid[8];                     /* Peripheral ID */
463         u32 cid[4];                     /* Component ID */
464         struct {
465                 u32 snoop_ctrl;         /* Snoop Control */
466                 u32 sha_ord;            /* Shareable Override */
467                 u8 res_1008[0x1100 - 0x1008];
468                 u32 rc_qos_ord;         /* read channel QoS Value Override */
469                 u32 wc_qos_ord;         /* read channel QoS Value Override */
470                 u8 res_1108[0x110c - 0x1108];
471                 u32 qos_ctrl;           /* QoS Control */
472                 u32 max_ot;             /* Max OT */
473                 u8 res_1114[0x1130 - 0x1114];
474                 u32 target_lat;         /* Target Latency */
475                 u32 latency_regu;       /* Latency Regulation */
476                 u32 qos_range;          /* QoS Range */
477                 u8 res_113c[0x2000 - 0x113c];
478         } slave[5];                     /* Slave Interface */
479         u8 res_6000[0x9004 - 0x6000];
480         u32 cycle_counter;              /* Cycle counter */
481         u32 count_ctrl;                 /* Count Control */
482         u32 overflow_status;            /* Overflow Flag Status */
483         u8 res_9010[0xa000 - 0x9010];
484         struct {
485                 u32 event_select;       /* Event Select */
486                 u32 event_count;        /* Event Count */
487                 u32 counter_ctrl;       /* Counter Control */
488                 u32 overflow_status;    /* Overflow Flag Status */
489                 u8 res_a010[0xb000 - 0xa010];
490         } pcounter[4];                  /* Performance Counter */
491         u8 res_e004[0x10000 - 0xe004];
492 };
493 #endif  /* __ASM_ARCH_LS102XA_IMMAP_H_ */