arch/arm/include/asm/arch-keystone/emac_defs.h

   1 /*
   2  * emac definitions for keystone2 devices
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _EMAC_DEFS_H_
  11 #define _EMAC_DEFS_H_
  12
  13 #include <asm/arch/hardware.h>
  14 #include <asm/io.h>
  15
  16 /* EMAC */
  17 #ifdef KS2_NETCP_V1_0
  18
  19 #define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00090900)
  20 #define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00090300)
  21 #define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00090100)
  22 #define DEVICE_EMACSL_BASE(x)           (EMAC_EMACSL_BASE_ADDR + (x)*0x040)
  23
  24 /* Register offsets */
  25 #define CPGMACSL_REG_CTL                0x04
  26 #define CPGMACSL_REG_STATUS             0x08
  27 #define CPGMACSL_REG_RESET              0x0c
  28 #define CPGMACSL_REG_MAXLEN             0x10
  29
  30 #elif defined KS2_NETCP_V1_5
  31
  32 #define CPGMACSL_REG_RX_PRI_MAP         0x020
  33 #define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00222000)
  34 #define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00200f00)
  35 #define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00200100)
  36 #define DEVICE_EMACSL_BASE(x)           (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
  37
  38 /* Register offsets */
  39 #define CPGMACSL_REG_CTL                0x330
  40 #define CPGMACSL_REG_STATUS             0x334
  41 #define CPGMACSL_REG_RESET              0x338
  42 #define CPGMACSL_REG_MAXLEN             0x024
  43
  44 #endif
  45
  46 #define KEYSTONE2_EMAC_GIG_ENABLE
  47
  48 #define MAC_ID_BASE_ADDR                (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
  49
  50 /* MDIO module input frequency */
  51 #define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
  52 /* MDIO clock output frequency */
  53 #define EMAC_MDIO_CLOCK_FREQ            1000000         /* 1.0 MHz */
  54
  55 /* MII Status Register */
  56 #define MII_STATUS_REG                  1
  57 #define MII_STATUS_LINK_MASK            (0x4)
  58
  59 /* Marvell 88E1111 PHY ID */
  60 #define PHY_MARVELL_88E1111             (0x01410cc0)
  61
  62 #define MDIO_CONTROL_IDLE               (0x80000000)
  63 #define MDIO_CONTROL_ENABLE             (0x40000000)
  64 #define MDIO_CONTROL_FAULT_ENABLE       (0x40000)
  65 #define MDIO_CONTROL_FAULT              (0x80000)
  66 #define MDIO_USERACCESS0_GO             (0x80000000)
  67 #define MDIO_USERACCESS0_WRITE_READ     (0x0)
  68 #define MDIO_USERACCESS0_WRITE_WRITE    (0x40000000)
  69 #define MDIO_USERACCESS0_ACK            (0x20000000)
  70
  71 #define EMAC_MACCONTROL_MIIEN_ENABLE       (0x20)
  72 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  (0x1)
  73 #define EMAC_MACCONTROL_GIGABIT_ENABLE     (1 << 7)
  74 #define EMAC_MACCONTROL_GIGFORCE           (1 << 17)
  75 #define EMAC_MACCONTROL_RMIISPEED_100      (1 << 15)
  76
  77 #define EMAC_MIN_ETHERNET_PKT_SIZE         60
  78
  79 struct mac_sl_cfg {
  80         u_int32_t max_rx_len;   /* Maximum receive packet length. */
  81         u_int32_t ctl;          /* Control bitfield */
  82 };
  83
  84 /*
  85  * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
  86  */
  87 #define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES       (1 << 24)
  88 #define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES         (1 << 23)
  89 #define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES         (1 << 22)
  90 #define GMACSL_RX_ENABLE_EXT_CTL                  (1 << 18)
  91 #define GMACSL_RX_ENABLE_GIG_FORCE                (1 << 17)
  92 #define GMACSL_RX_ENABLE_IFCTL_B                  (1 << 16)
  93 #define GMACSL_RX_ENABLE_IFCTL_A                  (1 << 15)
  94 #define GMACSL_RX_ENABLE_CMD_IDLE                 (1 << 11)
  95 #define GMACSL_TX_ENABLE_SHORT_GAP                (1 << 10)
  96 #define GMACSL_ENABLE_GIG_MODE                    (1 <<  7)
  97 #define GMACSL_TX_ENABLE_PACE                     (1 <<  6)
  98 #define GMACSL_ENABLE                             (1 <<  5)
  99 #define GMACSL_TX_ENABLE_FLOW_CTL                 (1 <<  4)
 100 #define GMACSL_RX_ENABLE_FLOW_CTL                 (1 <<  3)
 101 #define GMACSL_ENABLE_LOOPBACK                    (1 <<  1)
 102 #define GMACSL_ENABLE_FULL_DUPLEX                 (1 <<  0)
 103
 104 /*
 105  * DEFINTITION: function return values
 106  */
 107 #define GMACSL_RET_OK                        0
 108 #define GMACSL_RET_INVALID_PORT             -1
 109 #define GMACSL_RET_WARN_RESET_INCOMPLETE    -2
 110 #define GMACSL_RET_WARN_MAXLEN_TOO_BIG      -3
 111 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
 112
 113 /* EMAC SL register definitions */
 114 #define DEVICE_EMACSL_RESET_POLL_COUNT            100
 115
 116 /* Soft reset register values */
 117 #define CPGMAC_REG_RESET_VAL_RESET_MASK      (1 << 0)
 118 #define CPGMAC_REG_RESET_VAL_RESET           (1 << 0)
 119
 120 /* Maxlen register values */
 121 #define CPGMAC_REG_MAXLEN_LEN                0x3fff
 122
 123 /* CPSW */
 124 /* Control bitfields */
 125 #define CPSW_CTL_P2_PASS_PRI_TAGGED     (1 << 5)
 126 #define CPSW_CTL_P1_PASS_PRI_TAGGED     (1 << 4)
 127 #define CPSW_CTL_P0_PASS_PRI_TAGGED     (1 << 3)
 128 #define CPSW_CTL_P0_ENABLE              (1 << 2)
 129 #define CPSW_CTL_VLAN_AWARE             (1 << 1)
 130 #define CPSW_CTL_FIFO_LOOPBACK          (1 << 0)
 131
 132 #define DEVICE_CPSW_NUM_PORTS           CONFIG_KSNET_CPSW_NUM_PORTS
 133 #define DEVICE_N_GMACSL_PORTS           (DEVICE_CPSW_NUM_PORTS - 1)
 134
 135 #ifdef KS2_NETCP_V1_0
 136
 137 #define DEVICE_CPSW_BASE                (KS2_PASS_BASE + 0x00090800)
 138 #define CPSW_REG_CTL                    0x004
 139 #define CPSW_REG_STAT_PORT_EN           0x00c
 140 #define CPSW_REG_MAXLEN                 0x040
 141 #define CPSW_REG_ALE_CONTROL            0x608
 142 #define CPSW_REG_ALE_PORTCTL(x)         (0x640 + (x)*4)
 143 #define CPSW_REG_VAL_STAT_ENABLE_ALL     0xf
 144
 145 #elif defined KS2_NETCP_V1_5
 146
 147 #define DEVICE_CPSW_BASE                 (KS2_PASS_BASE + 0x00220000)
 148 #define CPSW_REG_CTL                     0x00004
 149 #define CPSW_REG_STAT_PORT_EN            0x00014
 150 #define CPSW_REG_MAXLEN                  0x01024
 151 #define CPSW_REG_ALE_CONTROL             0x1e008
 152 #define CPSW_REG_ALE_PORTCTL(x)          (0x1e040 + (x) * 4)
 153 #define CPSW_REG_VAL_STAT_ENABLE_ALL     0x1ff
 154
 155 #endif
 156
 157 #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE    ((u_int32_t)0xc0000000)
 158 #define CPSW_REG_VAL_ALE_CTL_BYPASS              ((u_int32_t)0x00000010)
 159 #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE        0x3
 160
 161 #define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
 162 #define SWITCH_MAX_PKT_SIZE         9000
 163
 164 /* SGMII */
 165 #define SGMII_REG_STATUS_LOCK           BIT(4)
 166 #define SGMII_REG_STATUS_LINK           BIT(0)
 167 #define SGMII_REG_STATUS_AUTONEG        BIT(2)
 168 #define SGMII_REG_CONTROL_AUTONEG       BIT(0)
 169 #define SGMII_REG_CONTROL_MASTER        BIT(5)
 170 #define SGMII_REG_MR_ADV_ENABLE         BIT(0)
 171 #define SGMII_REG_MR_ADV_LINK           BIT(15)
 172 #define SGMII_REG_MR_ADV_FULL_DUPLEX    BIT(12)
 173 #define SGMII_REG_MR_ADV_GIG_MODE       BIT(11)
 174
 175 #define SGMII_LINK_MAC_MAC_AUTONEG      0
 176 #define SGMII_LINK_MAC_PHY              1
 177 #define SGMII_LINK_MAC_MAC_FORCED       2
 178 #define SGMII_LINK_MAC_FIBER            3
 179 #define SGMII_LINK_MAC_PHY_FORCED       4
 180
 181 #ifdef KS2_NETCP_V1_0
 182 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
 183 #elif defined KS2_NETCP_V1_5
 184 #define SGMII_OFFSET(x)                 ((x) * 0x100)
 185 #endif
 186
 187 #define SGMII_IDVER_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
 188 #define SGMII_SRESET_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
 189 #define SGMII_CTL_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
 190 #define SGMII_STATUS_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
 191 #define SGMII_MRADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
 192 #define SGMII_LPADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
 193 #define SGMII_TXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
 194 #define SGMII_RXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
 195 #define SGMII_AUXCFG_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
 196
 197 /* PSS */
 198 #ifdef KS2_NETCP_V1_0
 199
 200 #define DEVICE_PSTREAM_CFG_REG_ADDR             (KS2_PASS_BASE + 0x604)
 201 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI       0x06060606
 202 #define hw_config_streaming_switch()\
 203         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
 204
 205 #elif defined KS2_NETCP_V1_5
 206
 207 #define DEVICE_PSTREAM_CFG_REG_ADDR             (KS2_PASS_BASE + 0x500)
 208 #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI       0x0
 209
 210 #define hw_config_streaming_switch()\
 211         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 212                DEVICE_PSTREAM_CFG_REG_ADDR);\
 213         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 214                DEVICE_PSTREAM_CFG_REG_ADDR+4);\
 215         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 216                DEVICE_PSTREAM_CFG_REG_ADDR+8);\
 217         writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
 218                DEVICE_PSTREAM_CFG_REG_ADDR+12);
 219
 220 #endif
 221
 222 /* EMAC MDIO Registers Structure */
 223 struct mdio_regs {
 224         dv_reg          version;
 225         dv_reg          control;
 226         dv_reg          alive;
 227         dv_reg          link;
 228         dv_reg          linkintraw;
 229         dv_reg          linkintmasked;
 230         u_int8_t        rsvd0[8];
 231         dv_reg          userintraw;
 232         dv_reg          userintmasked;
 233         dv_reg          userintmaskset;
 234         dv_reg          userintmaskclear;
 235         u_int8_t        rsvd1[80];
 236         dv_reg          useraccess0;
 237         dv_reg          userphysel0;
 238         dv_reg          useraccess1;
 239         dv_reg          userphysel1;
 240 };
 241
 242 struct eth_priv_t {
 243         char    int_name[32];
 244         int     rx_flow;
 245         int     phy_addr;
 246         int     slave_port;
 247         int     sgmii_link_type;
 248 };
 249
 250 int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
 251 void sgmii_serdes_setup_156p25mhz(void);
 252 void sgmii_serdes_shutdown(void);
 253
 254 #endif  /* _EMAC_DEFS_H_ */