arch/arm/include/asm/arch-imx8ulp/imx-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 NXP
   4  */
   5
   6 #ifndef _IMX8ULP_REGS_H_
   7 #define _IMX8ULP_REGS_H_
   8 #define ARCH_MXC
   9
  10 #include <linux/bitops.h>
  11 #include <linux/sizes.h>
  12
  13 #define PBRIDGE0_BASE           0x28000000
  14
  15 #define CMC0_RBASE              0x28025000
  16
  17 #define CMC1_BASE_ADDR          0x29240000
  18
  19 #define SIM1_BASE_ADDR          0x29290000
  20
  21 #define WDG3_RBASE              0x292a0000UL
  22
  23 #define SIM_SEC_BASE_ADDR       0x2802B000
  24
  25 #define CGC1_SOSCDIV_ADDR       0x292C0108
  26 #define CGC1_FRODIV_ADDR        0x292C0208
  27
  28 #define CFG1_PLL2CSR_ADDR       0x292C0500
  29 #define CFG1_PLL2CFG_ADDR       0x292C0510
  30
  31 #define PCC_XRDC_MGR_ADDR       0x292d00bc
  32
  33 #define PCC3_RBASE              0x292d0000
  34 #define PCC4_RBASE              0x29800000
  35 #define PCC5_RBASE              0x2da70000
  36
  37 #define IOMUXC_BASE_ADDR        0x298c0000
  38
  39 #define LPUART4_RBASE           0x29390000
  40 #define LPUART5_RBASE           0x293a0000
  41 #define LPUART6_RBASE           0x29860000
  42 #define LPUART7_RBASE           0x29870000
  43
  44 #define LPUART_BASE             LPUART5_RBASE
  45
  46 #define FSB_BASE_ADDR           0x27010000
  47
  48 #define USBOTG0_RBASE           0x29900000
  49 #define USB_PHY0_BASE_ADDR      0x29910000
  50 #define USBOTG1_RBASE           0x29920000
  51 #define USB_PHY1_BASE_ADDR      0x29930000
  52 #define USB_BASE_ADDR           USBOTG0_RBASE
  53
  54 #define DDR_CTL_BASE_ADDR       0x2E060000
  55 #define DDR_PI_BASE_ADDR        0x2E062000
  56 #define DDR_PHY_BASE_ADDR       0x2E064000
  57 #define AVD_SIM_BASE_ADDR       0x2DA50000
  58 #define AVD_SIM_LPDDR_CTRL      (AVD_SIM_BASE_ADDR + 0x14)
  59 #define AVD_SIM_LPDDR_CTRL2     (AVD_SIM_BASE_ADDR + 0x18)
  60
  61 #define FEC_QUIRK_ENET_MAC
  62
  63 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  64 #include <asm/types.h>
  65
  66 struct mu_type {
  67         u32 ver;
  68         u32 par;
  69         u32 cr;
  70         u32 sr;
  71         u32 reserved0[60];
  72         u32 fcr;
  73         u32 fsr;
  74         u32 reserved1[2];
  75         u32 gier;
  76         u32 gcr;
  77         u32 gsr;
  78         u32 reserved2;
  79         u32 tcr;
  80         u32 tsr;
  81         u32 rcr;
  82         u32 rsr;
  83         u32 reserved3[52];
  84         u32 tr[16];
  85         u32 reserved4[16];
  86         u32 rr[16];
  87         u32 reserved5[14];
  88         u32 mu_attr;
  89 };
  90
  91 struct usbphy_regs {
  92         u32     usbphy_pwd;                     /* 0x000 */
  93         u32     usbphy_pwd_set;                 /* 0x004 */
  94         u32     usbphy_pwd_clr;                 /* 0x008 */
  95         u32     usbphy_pwd_tog;                 /* 0x00c */
  96         u32     usbphy_tx;                      /* 0x010 */
  97         u32     usbphy_tx_set;                  /* 0x014 */
  98         u32     usbphy_tx_clr;                  /* 0x018 */
  99         u32     usbphy_tx_tog;                  /* 0x01c */
 100         u32     usbphy_rx;                      /* 0x020 */
 101         u32     usbphy_rx_set;                  /* 0x024 */
 102         u32     usbphy_rx_clr;                  /* 0x028 */
 103         u32     usbphy_rx_tog;                  /* 0x02c */
 104         u32     usbphy_ctrl;                    /* 0x030 */
 105         u32     usbphy_ctrl_set;                /* 0x034 */
 106         u32     usbphy_ctrl_clr;                /* 0x038 */
 107         u32     usbphy_ctrl_tog;                /* 0x03c */
 108         u32     usbphy_status;                  /* 0x040 */
 109         u32     reserved0[3];
 110         u32     usbphy_debug;                   /* 0x050 */
 111         u32     usbphy_debug_set;               /* 0x054 */
 112         u32     usbphy_debug_clr;               /* 0x058 */
 113         u32     usbphy_debug_tog;               /* 0x05c */
 114         u32     usbphy_debug0_status;   /* 0x060 */
 115         u32     reserved1[3];
 116         u32     usbphy_debug1;                  /* 0x070 */
 117         u32     usbphy_debug1_set;              /* 0x074 */
 118         u32     usbphy_debug1_clr;              /* 0x078 */
 119         u32     usbphy_debug1_tog;              /* 0x07c */
 120         u32     usbphy_version;                 /* 0x080 */
 121         u32     reserved2[7];
 122         u32     usb1_pll_480_ctrl;              /* 0x0a0 */
 123         u32     usb1_pll_480_ctrl_set;          /* 0x0a4 */
 124         u32     usb1_pll_480_ctrl_clr;          /* 0x0a8 */
 125         u32     usb1_pll_480_ctrl_tog;          /* 0x0ac */
 126         u32     reserved3[4];
 127         u32     usb1_vbus_detect;               /* 0xc0 */
 128         u32     usb1_vbus_detect_set;           /* 0xc4 */
 129         u32     usb1_vbus_detect_clr;           /* 0xc8 */
 130         u32     usb1_vbus_detect_tog;           /* 0xcc */
 131         u32     usb1_vbus_det_stat;             /* 0xd0 */
 132         u32     reserved4[3];
 133         u32     usb1_chrg_detect;               /* 0xe0 */
 134         u32     usb1_chrg_detect_set;           /* 0xe4 */
 135         u32     usb1_chrg_detect_clr;           /* 0xe8 */
 136         u32     usb1_chrg_detect_tog;           /* 0xec */
 137         u32     usb1_chrg_det_stat;             /* 0xf0 */
 138         u32     reserved5[3];
 139         u32     usbphy_anactrl;                 /* 0x100 */
 140         u32     usbphy_anactrl_set;             /* 0x104 */
 141         u32     usbphy_anactrl_clr;             /* 0x108 */
 142         u32     usbphy_anactrl_tog;             /* 0x10c */
 143         u32     usb1_loopback;                  /* 0x110 */
 144         u32     usb1_loopback_set;              /* 0x114 */
 145         u32     usb1_loopback_clr;              /* 0x118 */
 146         u32     usb1_loopback_tog;              /* 0x11c */
 147         u32     usb1_loopback_hsfscnt;          /* 0x120 */
 148         u32     usb1_loopback_hsfscnt_set;      /* 0x124 */
 149         u32     usb1_loopback_hsfscnt_clr;      /* 0x128 */
 150         u32     usb1_loopback_hsfscnt_tog;      /* 0x12c */
 151         u32     usphy_trim_override_en;         /* 0x130 */
 152         u32     usphy_trim_override_en_set;     /* 0x134 */
 153         u32     usphy_trim_override_en_clr;     /* 0x138 */
 154         u32     usphy_trim_override_en_tog;     /* 0x13c */
 155         u32     usb1_pfda_ctrl1;                /* 0x140 */
 156         u32     usb1_pfda_ctrl1_set;            /* 0x144 */
 157         u32     usb1_pfda_ctrl1_clr;            /* 0x148 */
 158         u32     usb1_pfda_ctrl1_tog;            /* 0x14c */
 159 };
 160 #endif
 161
 162 #endif