arch/arm/include/asm/arch-imx8m/lpddr4_define.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __LPDDR4_DEFINE_H_
   7 #define __LPDDR4_DEFINE_H_
   8
   9 #define LPDDR4_DVFS_DBI
  10 #define DDR_ONE_RANK
  11 /* #define LPDDR4_DBI_ON */
  12 #define DFI_BUG_WR
  13 #define M845S_4GBx2
  14 #define PRETRAIN
  15
  16 /* DRAM MR setting */
  17 #ifdef LPDDR4_DBI_ON
  18 #define LPDDR4_MR3                      0xf1
  19 #define LPDDR4_PHY_DMIPinPresent        0x1
  20 #else
  21 #define LPDDR4_MR3                      0x31
  22 #define LPDDR4_PHY_DMIPinPresent        0x0
  23 #endif
  24
  25 #ifdef DDR_ONE_RANK
  26 #define LPDDR4_CS                       0x1
  27 #else
  28 #define LPDDR4_CS                       0x3
  29 #endif
  30
  31 /* PHY training feature */
  32 #define LPDDR4_HDT_CTL_2D               0xC8
  33 #define LPDDR4_HDT_CTL_3200_1D          0xC8
  34 #define LPDDR4_HDT_CTL_400_1D           0xC8
  35 #define LPDDR4_HDT_CTL_100_1D           0xC8
  36
  37 /* 400/100 training seq */
  38 #define LPDDR4_TRAIN_SEQ_P2             0x121f
  39 #define LPDDR4_TRAIN_SEQ_P1             0x121f
  40 #define LPDDR4_TRAIN_SEQ_P0             0x121f
  41 #define LPDDR4_TRAIN_SEQ_100            0x121f
  42 #define LPDDR4_TRAIN_SEQ_400            0x121f
  43
  44 /* 2D share & weight */
  45 #define LPDDR4_2D_WEIGHT                0x1f7f
  46 #define LPDDR4_2D_SHARE                 1
  47 #define LPDDR4_CATRAIN_3200_1d          0
  48 #define LPDDR4_CATRAIN_400              0
  49 #define LPDDR4_CATRAIN_100              0
  50 #define LPDDR4_CATRAIN_3200_2d          0
  51
  52 /* MRS parameter */
  53 /* for LPDDR4 Rtt */
  54 #define LPDDR4_RTT40                    6
  55 #define LPDDR4_RTT48                    5
  56 #define LPDDR4_RTT60                    4
  57 #define LPDDR4_RTT80                    3
  58 #define LPDDR4_RTT120                   2
  59 #define LPDDR4_RTT240                   1
  60 #define LPDDR4_RTT_DIS                  0
  61
  62 /* for LPDDR4 Ron */
  63 #define LPDDR4_RON34                    7
  64 #define LPDDR4_RON40                    6
  65 #define LPDDR4_RON48                    5
  66 #define LPDDR4_RON60                    4
  67 #define LPDDR4_RON80                    3
  68
  69 #define LPDDR4_PHY_ADDR_RON60           0x1
  70 #define LPDDR4_PHY_ADDR_RON40           0x3
  71 #define LPDDR4_PHY_ADDR_RON30           0x7
  72 #define LPDDR4_PHY_ADDR_RON24           0xf
  73 #define LPDDR4_PHY_ADDR_RON20           0x1f
  74
  75 /* for read channel */
  76 #define LPDDR4_RON                      LPDDR4_RON40
  77 #define LPDDR4_PHY_RTT                  30
  78 #define LPDDR4_PHY_VREF_VALUE           17
  79
  80 /* for write channel */
  81 #define LPDDR4_PHY_RON                  30
  82 #define LPDDR4_PHY_ADDR_RON             LPDDR4_PHY_ADDR_RON40
  83 #define LPDDR4_RTT_DQ                   LPDDR4_RTT40
  84 #define LPDDR4_RTT_CA                   LPDDR4_RTT40
  85 #define LPDDR4_RTT_CA_BANK0             LPDDR4_RTT40
  86 #define LPDDR4_RTT_CA_BANK1             LPDDR4_RTT40
  87 #define LPDDR4_VREF_VALUE_CA            ((1 << 6) | (0xd))
  88 #define LPDDR4_VREF_VALUE_DQ_RANK0      ((1 << 6) | (0xd))
  89 #define LPDDR4_VREF_VALUE_DQ_RANK1      ((1 << 6) | (0xd))
  90 #define LPDDR4_MR22_RANK0               ((0 << 5) | (1 << 4) | (0 << 3) | \
  91                                         (LPDDR4_RTT40))
  92 #define LPDDR4_MR22_RANK1               ((1 << 5) | (1 << 4) | (1 << 3) | \
  93                                         (LPDDR4_RTT40))
  94
  95 #define LPDDR4_MR3_PU_CAL               1
  96
  97 #endif /* __LPDDR4_DEFINE_H__ */