arch/arm/include/asm/arch-imx8m/imx-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
   7 #define __ASM_ARCH_IMX8M_REGS_H__
   8
   9 #define ARCH_MXC
  10
  11 #include <asm/mach-imx/regs-lcdif.h>
  12
  13 #define ROM_VERSION_A0          IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
  14 #define ROM_VERSION_B0          IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
  15
  16 #define M4_BOOTROM_BASE_ADDR   0x007E0000
  17
  18 #define GPIO1_BASE_ADDR         0X30200000
  19 #define GPIO2_BASE_ADDR         0x30210000
  20 #define GPIO3_BASE_ADDR         0x30220000
  21 #define GPIO4_BASE_ADDR         0x30230000
  22 #define GPIO5_BASE_ADDR         0x30240000
  23 #define WDOG1_BASE_ADDR         0x30280000
  24 #define WDOG2_BASE_ADDR         0x30290000
  25 #define WDOG3_BASE_ADDR         0x302A0000
  26 #define IOMUXC_BASE_ADDR        0x30330000
  27 #define IOMUXC_GPR_BASE_ADDR    0x30340000
  28 #define OCOTP_BASE_ADDR         0x30350000
  29 #define ANATOP_BASE_ADDR        0x30360000
  30 #define CCM_BASE_ADDR           0x30380000
  31 #define SRC_BASE_ADDR           0x30390000
  32 #define GPC_BASE_ADDR           0x303A0000
  33
  34 #define SYSCNT_RD_BASE_ADDR     0x306A0000
  35 #define SYSCNT_CMP_BASE_ADDR    0x306B0000
  36 #define SYSCNT_CTRL_BASE_ADDR   0x306C0000
  37
  38 #define UART1_BASE_ADDR         0x30860000
  39 #define UART3_BASE_ADDR         0x30880000
  40 #define UART2_BASE_ADDR         0x30890000
  41 #define I2C1_BASE_ADDR          0x30A20000
  42 #define I2C2_BASE_ADDR          0x30A30000
  43 #define I2C3_BASE_ADDR          0x30A40000
  44 #define I2C4_BASE_ADDR          0x30A50000
  45 #define UART4_BASE_ADDR         0x30A60000
  46 #define USDHC1_BASE_ADDR        0x30B40000
  47 #define USDHC2_BASE_ADDR        0x30B50000
  48 #ifdef CONFIG_IMX8MM
  49 #define USDHC3_BASE_ADDR        0x30B60000
  50 #endif
  51
  52 #define TZASC_BASE_ADDR         0x32F80000
  53
  54 #define MXS_LCDIF_BASE          IS_ENABLED(CONFIG_IMX8MQ) ? \
  55                                         0x30320000 : 0x32e00000
  56
  57 #define SRC_IPS_BASE_ADDR       0x30390000
  58 #define SRC_DDRC_RCR_ADDR       0x30391000
  59 #define SRC_DDRC2_RCR_ADDR      0x30391004
  60
  61 #define DDRC_DDR_SS_GPR0        0x3d000000
  62 #define DDRC_IPS_BASE_ADDR(X)   (0x3d400000 + ((X) * 0x2000000))
  63 #define DDR_CSD1_BASE_ADDR      0x40000000
  64
  65 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
  66 #define FEC_QUIRK_ENET_MAC
  67
  68 #if !defined(__ASSEMBLY__)
  69 #include <asm/types.h>
  70 #include <linux/bitops.h>
  71 #include <stdbool.h>
  72
  73 #define GPR_TZASC_EN            BIT(0)
  74 #define GPR_TZASC_EN_LOCK       BIT(16)
  75
  76 #define SRC_SCR_M4_ENABLE_OFFSET        3
  77 #define SRC_SCR_M4_ENABLE_MASK          BIT(3)
  78 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
  79 #define SRC_SCR_M4C_NON_SCLR_RST_MASK   BIT(0)
  80 #define SRC_DDR1_ENABLE_MASK            0x8F000000UL
  81 #define SRC_DDR2_ENABLE_MASK            0x8F000000UL
  82 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
  83 #define SRC_DDR1_RCR_PHY_RESET_MASK     BIT(2)
  84 #define SRC_DDR1_RCR_CORE_RESET_N_MASK  BIT(1)
  85 #define SRC_DDR1_RCR_PRESET_N_MASK      BIT(0)
  86
  87 struct iomuxc_gpr_base_regs {
  88         u32 gpr[47];
  89 };
  90
  91 struct ocotp_regs {
  92         u32     ctrl;
  93         u32     ctrl_set;
  94         u32     ctrl_clr;
  95         u32     ctrl_tog;
  96         u32     timing;
  97         u32     rsvd0[3];
  98         u32     data;
  99         u32     rsvd1[3];
 100         u32     read_ctrl;
 101         u32     rsvd2[3];
 102         u32     read_fuse_data;
 103         u32     rsvd3[3];
 104         u32     sw_sticky;
 105         u32     rsvd4[3];
 106         u32     scs;
 107         u32     scs_set;
 108         u32     scs_clr;
 109         u32     scs_tog;
 110         u32     crc_addr;
 111         u32     rsvd5[3];
 112         u32     crc_value;
 113         u32     rsvd6[3];
 114         u32     version;
 115         u32     rsvd7[0xdb];
 116
 117         /* fuse banks */
 118         struct fuse_bank {
 119                 u32     fuse_regs[0x10];
 120         } bank[0];
 121 };
 122
 123 struct fuse_bank0_regs {
 124         u32 lock;
 125         u32 rsvd0[3];
 126         u32 uid_low;
 127         u32 rsvd1[3];
 128         u32 uid_high;
 129         u32 rsvd2[7];
 130 };
 131
 132 struct fuse_bank1_regs {
 133         u32 tester3;
 134         u32 rsvd0[3];
 135         u32 tester4;
 136         u32 rsvd1[3];
 137         u32 tester5;
 138         u32 rsvd2[3];
 139         u32 cfg0;
 140         u32 rsvd3[3];
 141 };
 142
 143 struct fuse_bank3_regs {
 144         u32 mem_trim0;
 145         u32 rsvd0[3];
 146         u32 mem_trim1;
 147         u32 rsvd1[3];
 148         u32 mem_trim2;
 149         u32 rsvd2[3];
 150         u32 ana0;
 151         u32 rsvd3[3];
 152 };
 153
 154 struct fuse_bank9_regs {
 155         u32 mac_addr0;
 156         u32 rsvd0[3];
 157         u32 mac_addr1;
 158         u32 rsvd1[11];
 159 };
 160
 161 struct fuse_bank38_regs {
 162         u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
 163         u32 rsvd0[3];
 164         u32 ana_trim2;
 165         u32 rsvd1[3];
 166         u32 ana_trim3;
 167         u32 rsvd2[3];
 168         u32 ana_trim4;
 169         u32 rsvd3[3];
 170 };
 171
 172 struct fuse_bank39_regs {
 173         u32 ana_trim5;
 174         u32 rsvd[15];
 175 };
 176
 177 #ifdef CONFIG_IMX8MQ
 178 struct anamix_pll {
 179         u32 audio_pll1_cfg0;
 180         u32 audio_pll1_cfg1;
 181         u32 audio_pll2_cfg0;
 182         u32 audio_pll2_cfg1;
 183         u32 video_pll_cfg0;
 184         u32 video_pll_cfg1;
 185         u32 gpu_pll_cfg0;
 186         u32 gpu_pll_cfg1;
 187         u32 vpu_pll_cfg0;
 188         u32 vpu_pll_cfg1;
 189         u32 arm_pll_cfg0;
 190         u32 arm_pll_cfg1;
 191         u32 sys_pll1_cfg0;
 192         u32 sys_pll1_cfg1;
 193         u32 sys_pll1_cfg2;
 194         u32 sys_pll2_cfg0;
 195         u32 sys_pll2_cfg1;
 196         u32 sys_pll2_cfg2;
 197         u32 sys_pll3_cfg0;
 198         u32 sys_pll3_cfg1;
 199         u32 sys_pll3_cfg2;
 200         u32 video_pll2_cfg0;
 201         u32 video_pll2_cfg1;
 202         u32 video_pll2_cfg2;
 203         u32 dram_pll_cfg0;
 204         u32 dram_pll_cfg1;
 205         u32 dram_pll_cfg2;
 206         u32 digprog;
 207         u32 osc_misc_cfg;
 208         u32 pllout_monitor_cfg;
 209         u32 frac_pllout_div_cfg;
 210         u32 sscg_pllout_div_cfg;
 211 };
 212 #else
 213 struct anamix_pll {
 214         u32 audio_pll1_gnrl_ctl;
 215         u32 audio_pll1_fdiv_ctl0;
 216         u32 audio_pll1_fdiv_ctl1;
 217         u32 audio_pll1_sscg_ctl;
 218         u32 audio_pll1_mnit_ctl;
 219         u32 audio_pll2_gnrl_ctl;
 220         u32 audio_pll2_fdiv_ctl0;
 221         u32 audio_pll2_fdiv_ctl1;
 222         u32 audio_pll2_sscg_ctl;
 223         u32 audio_pll2_mnit_ctl;
 224         u32 video_pll1_gnrl_ctl;
 225         u32 video_pll1_fdiv_ctl0;
 226         u32 video_pll1_fdiv_ctl1;
 227         u32 video_pll1_sscg_ctl;
 228         u32 video_pll1_mnit_ctl;
 229         u32 reserved[5];
 230         u32 dram_pll_gnrl_ctl;
 231         u32 dram_pll_fdiv_ctl0;
 232         u32 dram_pll_fdiv_ctl1;
 233         u32 dram_pll_sscg_ctl;
 234         u32 dram_pll_mnit_ctl;
 235         u32 gpu_pll_gnrl_ctl;
 236         u32 gpu_pll_div_ctl;
 237         u32 gpu_pll_locked_ctl1;
 238         u32 gpu_pll_mnit_ctl;
 239         u32 vpu_pll_gnrl_ctl;
 240         u32 vpu_pll_div_ctl;
 241         u32 vpu_pll_locked_ctl1;
 242         u32 vpu_pll_mnit_ctl;
 243         u32 arm_pll_gnrl_ctl;
 244         u32 arm_pll_div_ctl;
 245         u32 arm_pll_locked_ctl1;
 246         u32 arm_pll_mnit_ctl;
 247         u32 sys_pll1_gnrl_ctl;
 248         u32 sys_pll1_div_ctl;
 249         u32 sys_pll1_locked_ctl1;
 250         u32 reserved2[24];
 251         u32 sys_pll1_mnit_ctl;
 252         u32 sys_pll2_gnrl_ctl;
 253         u32 sys_pll2_div_ctl;
 254         u32 sys_pll2_locked_ctl1;
 255         u32 sys_pll2_mnit_ctl;
 256         u32 sys_pll3_gnrl_ctl;
 257         u32 sys_pll3_div_ctl;
 258         u32 sys_pll3_locked_ctl1;
 259         u32 sys_pll3_mnit_ctl;
 260         u32 anamix_misc_ctl;
 261         u32 anamix_clk_mnit_ctl;
 262         u32 reserved3[437];
 263         u32 digprog;
 264 };
 265 #endif
 266
 267 /* System Reset Controller (SRC) */
 268 struct src {
 269         u32 scr;
 270         u32 a53rcr;
 271         u32 a53rcr1;
 272         u32 m4rcr;
 273         u32 reserved1[4];
 274         u32 usbophy1_rcr;
 275         u32 usbophy2_rcr;
 276         u32 mipiphy_rcr;
 277         u32 pciephy_rcr;
 278         u32 hdmi_rcr;
 279         u32 disp_rcr;
 280         u32 reserved2[2];
 281         u32 gpu_rcr;
 282         u32 vpu_rcr;
 283         u32 pcie2_rcr;
 284         u32 mipiphy1_rcr;
 285         u32 mipiphy2_rcr;
 286         u32 reserved3;
 287         u32 sbmr1;
 288         u32 srsr;
 289         u32 reserved4[2];
 290         u32 sisr;
 291         u32 simr;
 292         u32 sbmr2;
 293         u32 gpr1;
 294         u32 gpr2;
 295         u32 gpr3;
 296         u32 gpr4;
 297         u32 gpr5;
 298         u32 gpr6;
 299         u32 gpr7;
 300         u32 gpr8;
 301         u32 gpr9;
 302         u32 gpr10;
 303         u32 reserved5[985];
 304         u32 ddr1_rcr;
 305         u32 ddr2_rcr;
 306 };
 307
 308 #define WDOG_WDT_MASK   BIT(3)
 309 #define WDOG_WDZST_MASK BIT(0)
 310 struct wdog_regs {
 311         u16     wcr;    /* Control */
 312         u16     wsr;    /* Service */
 313         u16     wrsr;   /* Reset Status */
 314         u16     wicr;   /* Interrupt Control */
 315         u16     wmcr;   /* Miscellaneous Control */
 316 };
 317
 318 struct bootrom_sw_info {
 319         u8 reserved_1;
 320         u8 boot_dev_instance;
 321         u8 boot_dev_type;
 322         u8 reserved_2;
 323         u32 core_freq;
 324         u32 axi_freq;
 325         u32 ddr_freq;
 326         u32 tick_freq;
 327         u32 reserved_3[3];
 328 };
 329
 330 #define ROM_SW_INFO_ADDR_B0     (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
 331                                  0x000009e8)
 332 #define ROM_SW_INFO_ADDR_A0     0x000009e8
 333
 334 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
 335                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
 336                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
 337
 338 struct gpc_reg {
 339         u32 lpcr_bsc;
 340         u32 lpcr_ad;
 341         u32 lpcr_cpu1;
 342         u32 lpcr_cpu2;
 343         u32 lpcr_cpu3;
 344         u32 slpcr;
 345         u32 mst_cpu_mapping;
 346         u32 mmdc_cpu_mapping;
 347         u32 mlpcr;
 348         u32 pgc_ack_sel;
 349         u32 pgc_ack_sel_m4;
 350         u32 gpc_misc;
 351         u32 imr1_core0;
 352         u32 imr2_core0;
 353         u32 imr3_core0;
 354         u32 imr4_core0;
 355         u32 imr1_core1;
 356         u32 imr2_core1;
 357         u32 imr3_core1;
 358         u32 imr4_core1;
 359         u32 imr1_cpu1;
 360         u32 imr2_cpu1;
 361         u32 imr3_cpu1;
 362         u32 imr4_cpu1;
 363         u32 imr1_cpu3;
 364         u32 imr2_cpu3;
 365         u32 imr3_cpu3;
 366         u32 imr4_cpu3;
 367         u32 isr1_cpu0;
 368         u32 isr2_cpu0;
 369         u32 isr3_cpu0;
 370         u32 isr4_cpu0;
 371         u32 isr1_cpu1;
 372         u32 isr2_cpu1;
 373         u32 isr3_cpu1;
 374         u32 isr4_cpu1;
 375         u32 isr1_cpu2;
 376         u32 isr2_cpu2;
 377         u32 isr3_cpu2;
 378         u32 isr4_cpu2;
 379         u32 isr1_cpu3;
 380         u32 isr2_cpu3;
 381         u32 isr3_cpu3;
 382         u32 isr4_cpu3;
 383         u32 slt0_cfg;
 384         u32 slt1_cfg;
 385         u32 slt2_cfg;
 386         u32 slt3_cfg;
 387         u32 slt4_cfg;
 388         u32 slt5_cfg;
 389         u32 slt6_cfg;
 390         u32 slt7_cfg;
 391         u32 slt8_cfg;
 392         u32 slt9_cfg;
 393         u32 slt10_cfg;
 394         u32 slt11_cfg;
 395         u32 slt12_cfg;
 396         u32 slt13_cfg;
 397         u32 slt14_cfg;
 398         u32 pgc_cpu_0_1_mapping;
 399         u32 cpu_pgc_up_trg;
 400         u32 mix_pgc_up_trg;
 401         u32 pu_pgc_up_trg;
 402         u32 cpu_pgc_dn_trg;
 403         u32 mix_pgc_dn_trg;
 404         u32 pu_pgc_dn_trg;
 405         u32 lpcr_bsc2;
 406         u32 pgc_cpu_2_3_mapping;
 407         u32 lps_cpu0;
 408         u32 lps_cpu1;
 409         u32 lps_cpu2;
 410         u32 lps_cpu3;
 411         u32 gpc_gpr;
 412         u32 gtor;
 413         u32 debug_addr1;
 414         u32 debug_addr2;
 415         u32 cpu_pgc_up_status1;
 416         u32 mix_pgc_up_status0;
 417         u32 mix_pgc_up_status1;
 418         u32 mix_pgc_up_status2;
 419         u32 m4_mix_pgc_up_status0;
 420         u32 m4_mix_pgc_up_status1;
 421         u32 m4_mix_pgc_up_status2;
 422         u32 pu_pgc_up_status0;
 423         u32 pu_pgc_up_status1;
 424         u32 pu_pgc_up_status2;
 425         u32 m4_pu_pgc_up_status0;
 426         u32 m4_pu_pgc_up_status1;
 427         u32 m4_pu_pgc_up_status2;
 428         u32 a53_lp_io_0;
 429         u32 a53_lp_io_1;
 430         u32 a53_lp_io_2;
 431         u32 cpu_pgc_dn_status1;
 432         u32 mix_pgc_dn_status0;
 433         u32 mix_pgc_dn_status1;
 434         u32 mix_pgc_dn_status2;
 435         u32 m4_mix_pgc_dn_status0;
 436         u32 m4_mix_pgc_dn_status1;
 437         u32 m4_mix_pgc_dn_status2;
 438         u32 pu_pgc_dn_status0;
 439         u32 pu_pgc_dn_status1;
 440         u32 pu_pgc_dn_status2;
 441         u32 m4_pu_pgc_dn_status0;
 442         u32 m4_pu_pgc_dn_status1;
 443         u32 m4_pu_pgc_dn_status2;
 444         u32 res[3];
 445         u32 mix_pdn_flg;
 446         u32 pu_pdn_flg;
 447         u32 m4_mix_pdn_flg;
 448         u32 m4_pu_pdn_flg;
 449         u32 imr1_core2;
 450         u32 imr2_core2;
 451         u32 imr3_core2;
 452         u32 imr4_core2;
 453         u32 imr1_core3;
 454         u32 imr2_core3;
 455         u32 imr3_core3;
 456         u32 imr4_core3;
 457         u32 pgc_ack_sel_pu;
 458         u32 pgc_ack_sel_m4_pu;
 459         u32 slt15_cfg;
 460         u32 slt16_cfg;
 461         u32 slt17_cfg;
 462         u32 slt18_cfg;
 463         u32 slt19_cfg;
 464         u32 gpc_pu_pwrhsk;
 465         u32 slt0_cfg_pu;
 466         u32 slt1_cfg_pu;
 467         u32 slt2_cfg_pu;
 468         u32 slt3_cfg_pu;
 469         u32 slt4_cfg_pu;
 470         u32 slt5_cfg_pu;
 471         u32 slt6_cfg_pu;
 472         u32 slt7_cfg_pu;
 473         u32 slt8_cfg_pu;
 474         u32 slt9_cfg_pu;
 475         u32 slt10_cfg_pu;
 476         u32 slt11_cfg_pu;
 477         u32 slt12_cfg_pu;
 478         u32 slt13_cfg_pu;
 479         u32 slt14_cfg_pu;
 480         u32 slt15_cfg_pu;
 481         u32 slt16_cfg_pu;
 482         u32 slt17_cfg_pu;
 483         u32 slt18_cfg_pu;
 484         u32 slt19_cfg_pu;
 485 };
 486
 487 struct pgc_reg {
 488         u32 pgcr;
 489         u32 pgpupscr;
 490         u32 pgpdnscr;
 491         u32 pgsr;
 492         u32 pgauxsw;
 493         u32 pgdr;
 494 };
 495 #endif
 496 #endif