1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
7 #define __ASM_ARCH_IMX8M_REGS_H__
11 #include <asm/mach-imx/regs-lcdif.h>
13 #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
14 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
16 #define MCU_BOOTROM_BASE_ADDR 0x007E0000
18 #define GPIO1_BASE_ADDR 0X30200000
19 #define GPIO2_BASE_ADDR 0x30210000
20 #define GPIO3_BASE_ADDR 0x30220000
21 #define GPIO4_BASE_ADDR 0x30230000
22 #define GPIO5_BASE_ADDR 0x30240000
23 #define WDOG1_BASE_ADDR 0x30280000
24 #define WDOG2_BASE_ADDR 0x30290000
25 #define WDOG3_BASE_ADDR 0x302A0000
26 #define IOMUXC_BASE_ADDR 0x30330000
27 #define IOMUXC_GPR_BASE_ADDR 0x30340000
28 #define OCOTP_BASE_ADDR 0x30350000
29 #define ANATOP_BASE_ADDR 0x30360000
30 #define SNVS_BASE_ADDR 0x30370000
31 #define CCM_BASE_ADDR 0x30380000
32 #define SRC_BASE_ADDR 0x30390000
33 #define GPC_BASE_ADDR 0x303A0000
34 #define CSU_BASE_ADDR 0x303E0000
36 #define SYSCNT_RD_BASE_ADDR 0x306A0000
37 #define SYSCNT_CMP_BASE_ADDR 0x306B0000
38 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000
40 #define UART1_BASE_ADDR 0x30860000
41 #define UART3_BASE_ADDR 0x30880000
42 #define UART2_BASE_ADDR 0x30890000
43 #define CAAM_BASE_ADDR 0x30900000
44 #define I2C1_BASE_ADDR 0x30A20000
45 #define I2C2_BASE_ADDR 0x30A30000
46 #define I2C3_BASE_ADDR 0x30A40000
47 #define I2C4_BASE_ADDR 0x30A50000
48 #define UART4_BASE_ADDR 0x30A60000
50 #define I2C5_BASE_ADDR 0x30AD0000
51 #define I2C6_BASE_ADDR 0x30AE0000
53 #define USDHC1_BASE_ADDR 0x30B40000
54 #define USDHC2_BASE_ADDR 0x30B50000
55 #define QSPI0_AMBA_BASE 0x08000000
56 #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP)
57 #define USDHC3_BASE_ADDR 0x30B60000
59 #define UART_BASE_ADDR(n) ( \
61 static_assert((n) >= 1 && (n) <= 4); \
64 (n) == 1 ? UART1_BASE_ADDR : \
65 (n) == 2 ? UART2_BASE_ADDR : \
66 (n) == 3 ? UART3_BASE_ADDR : \
70 #define TZASC_BASE_ADDR 0x32F80000
72 #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
73 0x30320000 : 0x32e00000
75 #define SRC_IPS_BASE_ADDR 0x30390000
76 #define SRC_DDRC_RCR_ADDR 0x30391000
77 #define SRC_DDRC2_RCR_ADDR 0x30391004
79 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
80 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
81 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
83 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
84 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
86 #define GICD_BASE 0x38800000
87 #define GICR_BASE 0x38880000
89 #define DDRC_DDR_SS_GPR0 0x3d000000
90 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
91 #define DDR_CSD1_BASE_ADDR 0x40000000
93 #define IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN BIT(22)
94 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
95 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20)
96 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19)
97 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
98 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
99 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16)
100 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
101 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL BIT(13)
102 #define FEC_QUIRK_ENET_MAC
104 #ifdef CONFIG_ARMV8_PSCI /* Final jump location */
105 #define CPU_RELEASE_ADDR 0x900000
108 #define CAAM_ARB_BASE_ADDR (0x00100000)
109 #define CAAM_ARB_END_ADDR (0x00107FFF)
110 #define CAAM_IPS_BASE_ADDR (0x30900000)
111 #define CFG_SYS_FSL_SEC_OFFSET (0)
112 #define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
113 CFG_SYS_FSL_SEC_OFFSET)
114 #define CFG_SYS_FSL_JR0_OFFSET (0x1000)
115 #define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
116 CFG_SYS_FSL_JR0_OFFSET)
117 #if !defined(__ASSEMBLY__)
118 #include <asm/types.h>
119 #include <linux/bitops.h>
122 #define GPR_TZASC_EN BIT(0)
123 #define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
124 #define GPR_TZASC_EN_LOCK BIT(16)
125 #define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
127 #define SRC_SCR_M4_ENABLE_OFFSET 3
128 #define SRC_SCR_M4_ENABLE_MASK BIT(3)
129 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
130 #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
131 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL
132 #define SRC_DDR2_ENABLE_MASK 0x8F000000UL
133 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
134 #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
135 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
136 #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
138 #define SNVS_LPSR 0x4c
139 #define SNVS_LPLVDR 0x64
140 #define SNVS_LPPGDR_INIT 0x41736166
142 struct iomuxc_gpr_base_regs {
179 struct fuse_bank0_regs {
188 struct fuse_bank0_regs {
198 struct fuse_bank1_regs {
209 struct fuse_bank3_regs {
220 struct fuse_bank9_regs {
227 struct fuse_bank38_regs {
228 u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
238 struct fuse_bank39_regs {
274 u32 pllout_monitor_cfg;
275 u32 frac_pllout_div_cfg;
276 u32 sscg_pllout_div_cfg;
280 u32 audio_pll1_gnrl_ctl;
281 u32 audio_pll1_fdiv_ctl0;
282 u32 audio_pll1_fdiv_ctl1;
283 u32 audio_pll1_sscg_ctl;
284 u32 audio_pll1_mnit_ctl;
285 u32 audio_pll2_gnrl_ctl;
286 u32 audio_pll2_fdiv_ctl0;
287 u32 audio_pll2_fdiv_ctl1;
288 u32 audio_pll2_sscg_ctl;
289 u32 audio_pll2_mnit_ctl;
290 u32 video_pll1_gnrl_ctl;
291 u32 video_pll1_fdiv_ctl0;
292 u32 video_pll1_fdiv_ctl1;
293 u32 video_pll1_sscg_ctl;
294 u32 video_pll1_mnit_ctl;
296 u32 dram_pll_gnrl_ctl;
297 u32 dram_pll_fdiv_ctl0;
298 u32 dram_pll_fdiv_ctl1;
299 u32 dram_pll_sscg_ctl;
300 u32 dram_pll_mnit_ctl;
301 u32 gpu_pll_gnrl_ctl;
303 u32 gpu_pll_locked_ctl1;
304 u32 gpu_pll_mnit_ctl;
305 u32 vpu_pll_gnrl_ctl;
307 u32 vpu_pll_locked_ctl1;
308 u32 vpu_pll_mnit_ctl;
309 u32 arm_pll_gnrl_ctl;
311 u32 arm_pll_locked_ctl1;
312 u32 arm_pll_mnit_ctl;
313 u32 sys_pll1_gnrl_ctl;
314 u32 sys_pll1_div_ctl;
315 u32 sys_pll1_locked_ctl1;
317 u32 sys_pll1_mnit_ctl;
318 u32 sys_pll2_gnrl_ctl;
319 u32 sys_pll2_div_ctl;
320 u32 sys_pll2_locked_ctl1;
321 u32 sys_pll2_mnit_ctl;
322 u32 sys_pll3_gnrl_ctl;
323 u32 sys_pll3_div_ctl;
324 u32 sys_pll3_locked_ctl1;
325 u32 sys_pll3_mnit_ctl;
327 u32 anamix_clk_mnit_ctl;
333 /* System Reset Controller (SRC) */
374 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
375 #define PWMCR_DOZEEN (1 << 24)
376 #define PWMCR_WAITEN (1 << 23)
377 #define PWMCR_DBGEN (1 << 22)
378 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
379 #define PWMCR_CLKSRC_IPG (1 << 16)
380 #define PWMCR_EN (1 << 0)
391 #define WDOG_WDT_MASK BIT(3)
392 #define WDOG_WDZST_MASK BIT(0)
394 u16 wcr; /* Control */
395 u16 wsr; /* Service */
396 u16 wrsr; /* Reset Status */
397 u16 wicr; /* Interrupt Control */
398 u16 wmcr; /* Miscellaneous Control */
401 struct bootrom_sw_info {
403 u8 boot_dev_instance;
413 #define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
415 #define ROM_SW_INFO_ADDR_A0 0x000009e8
417 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
418 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
419 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
429 u32 mmdc_cpu_mapping;
481 u32 pgc_cpu_0_1_mapping;
489 u32 pgc_cpu_2_3_mapping;
498 u32 cpu_pgc_up_status1;
499 u32 mix_pgc_up_status0;
500 u32 mix_pgc_up_status1;
501 u32 mix_pgc_up_status2;
502 u32 m4_mix_pgc_up_status0;
503 u32 m4_mix_pgc_up_status1;
504 u32 m4_mix_pgc_up_status2;
505 u32 pu_pgc_up_status0;
506 u32 pu_pgc_up_status1;
507 u32 pu_pgc_up_status2;
508 u32 m4_pu_pgc_up_status0;
509 u32 m4_pu_pgc_up_status1;
510 u32 m4_pu_pgc_up_status2;
514 u32 cpu_pgc_dn_status1;
515 u32 mix_pgc_dn_status0;
516 u32 mix_pgc_dn_status1;
517 u32 mix_pgc_dn_status2;
518 u32 m4_mix_pgc_dn_status0;
519 u32 m4_mix_pgc_dn_status1;
520 u32 m4_mix_pgc_dn_status2;
521 u32 pu_pgc_dn_status0;
522 u32 pu_pgc_dn_status1;
523 u32 pu_pgc_dn_status2;
524 u32 m4_pu_pgc_dn_status0;
525 u32 m4_pu_pgc_dn_status1;
526 u32 m4_pu_pgc_dn_status2;
541 u32 pgc_ack_sel_m4_pu;