1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
7 #define __ASM_ARCH_IMX8M_REGS_H__
11 #include <asm/mach-imx/regs-lcdif.h>
13 #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
14 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
16 #define M4_BOOTROM_BASE_ADDR 0x007E0000
18 #define GPIO1_BASE_ADDR 0X30200000
19 #define GPIO2_BASE_ADDR 0x30210000
20 #define GPIO3_BASE_ADDR 0x30220000
21 #define GPIO4_BASE_ADDR 0x30230000
22 #define GPIO5_BASE_ADDR 0x30240000
23 #define WDOG1_BASE_ADDR 0x30280000
24 #define WDOG2_BASE_ADDR 0x30290000
25 #define WDOG3_BASE_ADDR 0x302A0000
26 #define IOMUXC_BASE_ADDR 0x30330000
27 #define IOMUXC_GPR_BASE_ADDR 0x30340000
28 #define OCOTP_BASE_ADDR 0x30350000
29 #define ANATOP_BASE_ADDR 0x30360000
30 #define CCM_BASE_ADDR 0x30380000
31 #define SRC_BASE_ADDR 0x30390000
32 #define GPC_BASE_ADDR 0x303A0000
34 #define SYSCNT_RD_BASE_ADDR 0x306A0000
35 #define SYSCNT_CMP_BASE_ADDR 0x306B0000
36 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000
38 #define UART1_BASE_ADDR 0x30860000
39 #define UART3_BASE_ADDR 0x30880000
40 #define UART2_BASE_ADDR 0x30890000
41 #define I2C1_BASE_ADDR 0x30A20000
42 #define I2C2_BASE_ADDR 0x30A30000
43 #define I2C3_BASE_ADDR 0x30A40000
44 #define I2C4_BASE_ADDR 0x30A50000
45 #define UART4_BASE_ADDR 0x30A60000
46 #define USDHC1_BASE_ADDR 0x30B40000
47 #define USDHC2_BASE_ADDR 0x30B50000
49 #define USDHC3_BASE_ADDR 0x30B60000
52 #define TZASC_BASE_ADDR 0x32F80000
54 #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
55 0x30320000 : 0x32e00000
57 #define SRC_IPS_BASE_ADDR 0x30390000
58 #define SRC_DDRC_RCR_ADDR 0x30391000
59 #define SRC_DDRC2_RCR_ADDR 0x30391004
61 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
62 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
63 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
65 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
66 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
68 #define DDRC_DDR_SS_GPR0 0x3d000000
69 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
70 #define DDR_CSD1_BASE_ADDR 0x40000000
72 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
73 #define FEC_QUIRK_ENET_MAC
75 #define CAAM_ARB_BASE_ADDR (0x00100000)
76 #define CAAM_ARB_END_ADDR (0x00107FFF)
77 #define CAAM_IPS_BASE_ADDR (0x30900000)
78 #define CONFIG_SYS_FSL_SEC_OFFSET (0)
79 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
80 CONFIG_SYS_FSL_SEC_OFFSET)
81 #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
82 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
83 CONFIG_SYS_FSL_JR0_OFFSET)
84 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
85 #if !defined(__ASSEMBLY__)
86 #include <asm/types.h>
87 #include <linux/bitops.h>
90 #define GPR_TZASC_EN BIT(0)
91 #define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
92 #define GPR_TZASC_EN_LOCK BIT(16)
93 #define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
95 #define SRC_SCR_M4_ENABLE_OFFSET 3
96 #define SRC_SCR_M4_ENABLE_MASK BIT(3)
97 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
98 #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
99 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL
100 #define SRC_DDR2_ENABLE_MASK 0x8F000000UL
101 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
102 #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
103 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
104 #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
106 struct iomuxc_gpr_base_regs {
143 struct fuse_bank0_regs {
152 struct fuse_bank0_regs {
162 struct fuse_bank1_regs {
173 struct fuse_bank3_regs {
184 struct fuse_bank9_regs {
191 struct fuse_bank38_regs {
192 u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
202 struct fuse_bank39_regs {
238 u32 pllout_monitor_cfg;
239 u32 frac_pllout_div_cfg;
240 u32 sscg_pllout_div_cfg;
244 u32 audio_pll1_gnrl_ctl;
245 u32 audio_pll1_fdiv_ctl0;
246 u32 audio_pll1_fdiv_ctl1;
247 u32 audio_pll1_sscg_ctl;
248 u32 audio_pll1_mnit_ctl;
249 u32 audio_pll2_gnrl_ctl;
250 u32 audio_pll2_fdiv_ctl0;
251 u32 audio_pll2_fdiv_ctl1;
252 u32 audio_pll2_sscg_ctl;
253 u32 audio_pll2_mnit_ctl;
254 u32 video_pll1_gnrl_ctl;
255 u32 video_pll1_fdiv_ctl0;
256 u32 video_pll1_fdiv_ctl1;
257 u32 video_pll1_sscg_ctl;
258 u32 video_pll1_mnit_ctl;
260 u32 dram_pll_gnrl_ctl;
261 u32 dram_pll_fdiv_ctl0;
262 u32 dram_pll_fdiv_ctl1;
263 u32 dram_pll_sscg_ctl;
264 u32 dram_pll_mnit_ctl;
265 u32 gpu_pll_gnrl_ctl;
267 u32 gpu_pll_locked_ctl1;
268 u32 gpu_pll_mnit_ctl;
269 u32 vpu_pll_gnrl_ctl;
271 u32 vpu_pll_locked_ctl1;
272 u32 vpu_pll_mnit_ctl;
273 u32 arm_pll_gnrl_ctl;
275 u32 arm_pll_locked_ctl1;
276 u32 arm_pll_mnit_ctl;
277 u32 sys_pll1_gnrl_ctl;
278 u32 sys_pll1_div_ctl;
279 u32 sys_pll1_locked_ctl1;
281 u32 sys_pll1_mnit_ctl;
282 u32 sys_pll2_gnrl_ctl;
283 u32 sys_pll2_div_ctl;
284 u32 sys_pll2_locked_ctl1;
285 u32 sys_pll2_mnit_ctl;
286 u32 sys_pll3_gnrl_ctl;
287 u32 sys_pll3_div_ctl;
288 u32 sys_pll3_locked_ctl1;
289 u32 sys_pll3_mnit_ctl;
291 u32 anamix_clk_mnit_ctl;
297 /* System Reset Controller (SRC) */
338 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
339 #define PWMCR_DOZEEN (1 << 24)
340 #define PWMCR_WAITEN (1 << 23)
341 #define PWMCR_DBGEN (1 << 22)
342 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
343 #define PWMCR_CLKSRC_IPG (1 << 16)
344 #define PWMCR_EN (1 << 0)
355 #define WDOG_WDT_MASK BIT(3)
356 #define WDOG_WDZST_MASK BIT(0)
358 u16 wcr; /* Control */
359 u16 wsr; /* Service */
360 u16 wrsr; /* Reset Status */
361 u16 wicr; /* Interrupt Control */
362 u16 wmcr; /* Miscellaneous Control */
365 struct bootrom_sw_info {
367 u8 boot_dev_instance;
377 #define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
379 #define ROM_SW_INFO_ADDR_A0 0x000009e8
381 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
382 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
383 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
393 u32 mmdc_cpu_mapping;
445 u32 pgc_cpu_0_1_mapping;
453 u32 pgc_cpu_2_3_mapping;
462 u32 cpu_pgc_up_status1;
463 u32 mix_pgc_up_status0;
464 u32 mix_pgc_up_status1;
465 u32 mix_pgc_up_status2;
466 u32 m4_mix_pgc_up_status0;
467 u32 m4_mix_pgc_up_status1;
468 u32 m4_mix_pgc_up_status2;
469 u32 pu_pgc_up_status0;
470 u32 pu_pgc_up_status1;
471 u32 pu_pgc_up_status2;
472 u32 m4_pu_pgc_up_status0;
473 u32 m4_pu_pgc_up_status1;
474 u32 m4_pu_pgc_up_status2;
478 u32 cpu_pgc_dn_status1;
479 u32 mix_pgc_dn_status0;
480 u32 mix_pgc_dn_status1;
481 u32 mix_pgc_dn_status2;
482 u32 m4_mix_pgc_dn_status0;
483 u32 m4_mix_pgc_dn_status1;
484 u32 m4_mix_pgc_dn_status2;
485 u32 pu_pgc_dn_status0;
486 u32 pu_pgc_dn_status1;
487 u32 pu_pgc_dn_status2;
488 u32 m4_pu_pgc_dn_status0;
489 u32 m4_pu_pgc_dn_status1;
490 u32 m4_pu_pgc_dn_status2;
505 u32 pgc_ack_sel_m4_pu;