1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
7 #define __ASM_ARCH_IMX8M_REGS_H__
9 #include <asm/mach-imx/regs-lcdif.h>
11 #define ROM_VERSION_A0 0x800
12 #define ROM_VERSION_B0 0x83C
14 #define M4_BOOTROM_BASE_ADDR 0x007E0000
16 #define SAI1_BASE_ADDR 0x30010000
17 #define SAI6_BASE_ADDR 0x30030000
18 #define SAI5_BASE_ADDR 0x30040000
19 #define SAI4_BASE_ADDR 0x30050000
20 #define SPBA2_BASE_ADDR 0x300F0000
21 #define AIPS1_BASE_ADDR 0x301F0000
22 #define GPIO1_BASE_ADDR 0X30200000
23 #define GPIO2_BASE_ADDR 0x30210000
24 #define GPIO3_BASE_ADDR 0x30220000
25 #define GPIO4_BASE_ADDR 0x30230000
26 #define GPIO5_BASE_ADDR 0x30240000
27 #define ANA_TSENSOR_BASE_ADDR 0x30260000
28 #define ANA_OSC_BASE_ADDR 0x30270000
29 #define WDOG1_BASE_ADDR 0x30280000
30 #define WDOG2_BASE_ADDR 0x30290000
31 #define WDOG3_BASE_ADDR 0x302A0000
32 #define SDMA2_BASE_ADDR 0x302C0000
33 #define GPT1_BASE_ADDR 0x302D0000
34 #define GPT2_BASE_ADDR 0x302E0000
35 #define GPT3_BASE_ADDR 0x302F0000
36 #define ROMCP_BASE_ADDR 0x30310000
37 #define LCDIF_BASE_ADDR 0x30320000
38 #define IOMUXC_BASE_ADDR 0x30330000
39 #define IOMUXC_GPR_BASE_ADDR 0x30340000
40 #define OCOTP_BASE_ADDR 0x30350000
41 #define ANATOP_BASE_ADDR 0x30360000
42 #define SNVS_HP_BASE_ADDR 0x30370000
43 #define CCM_BASE_ADDR 0x30380000
44 #define SRC_BASE_ADDR 0x30390000
45 #define GPC_BASE_ADDR 0x303A0000
46 #define SEMAPHORE1_BASE_ADDR 0x303B0000
47 #define SEMAPHORE2_BASE_ADDR 0x303C0000
48 #define RDC_BASE_ADDR 0x303D0000
49 #define CSU_BASE_ADDR 0x303E0000
51 #define AIPS2_BASE_ADDR 0x305F0000
52 #define PWM1_BASE_ADDR 0x30660000
53 #define PWM2_BASE_ADDR 0x30670000
54 #define PWM3_BASE_ADDR 0x30680000
55 #define PWM4_BASE_ADDR 0x30690000
56 #define SYSCNT_RD_BASE_ADDR 0x306A0000
57 #define SYSCNT_CMP_BASE_ADDR 0x306B0000
58 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000
59 #define GPT6_BASE_ADDR 0x306E0000
60 #define GPT5_BASE_ADDR 0x306F0000
61 #define GPT4_BASE_ADDR 0x30700000
62 #define PERFMON1_BASE_ADDR 0x307C0000
63 #define PERFMON2_BASE_ADDR 0x307D0000
64 #define QOSC_BASE_ADDR 0x307F0000
66 #define SPDIF1_BASE_ADDR 0x30810000
67 #define ECSPI1_BASE_ADDR 0x30820000
68 #define ECSPI2_BASE_ADDR 0x30830000
69 #define ECSPI3_BASE_ADDR 0x30840000
70 #define UART1_BASE_ADDR 0x30860000
71 #define UART3_BASE_ADDR 0x30880000
72 #define UART2_BASE_ADDR 0x30890000
73 #define SPDIF2_BASE_ADDR 0x308A0000
74 #define SAI2_BASE_ADDR 0x308B0000
75 #define SAI3_BASE_ADDR 0x308C0000
76 #define SPBA1_BASE_ADDR 0x308F0000
77 #define CAAM_BASE_ADDR 0x30900000
78 #define AIPS3_BASE_ADDR 0x309F0000
79 #define MIPI_PHY_BASE_ADDR 0x30A00000
80 #define MIPI_DSI_BASE_ADDR 0x30A10000
81 #define I2C1_BASE_ADDR 0x30A20000
82 #define I2C2_BASE_ADDR 0x30A30000
83 #define I2C3_BASE_ADDR 0x30A40000
84 #define I2C4_BASE_ADDR 0x30A50000
85 #define UART4_BASE_ADDR 0x30A60000
86 #define MIPI_CSI_BASE_ADDR 0x30A70000
87 #define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000
88 #define CSI1_BASE_ADDR 0x30A90000
89 #define MU_A_BASE_ADDR 0x30AA0000
90 #define MU_B_BASE_ADDR 0x30AB0000
91 #define SEMAPHOR_HS_BASE_ADDR 0x30AC0000
92 #define USDHC1_BASE_ADDR 0x30B40000
93 #define USDHC2_BASE_ADDR 0x30B50000
94 #define MIPI_CS2_BASE_ADDR 0x30B60000
95 #define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
96 #define CSI2_BASE_ADDR 0x30B80000
97 #define QSPI0_BASE_ADDR 0x30BB0000
98 #define QSPI0_AMBA_BASE 0x08000000
99 #define SDMA1_BASE_ADDR 0x30BD0000
100 #define ENET1_BASE_ADDR 0x30BE0000
102 #define HDMI_CTRL_BASE_ADDR 0x32C00000
103 #define AIPS4_BASE_ADDR 0x32DF0000
104 #define DC1_BASE_ADDR 0x32E00000
105 #define DC2_BASE_ADDR 0x32E10000
106 #define DC3_BASE_ADDR 0x32E20000
107 #define HDMI_SEC_BASE_ADDR 0x32E40000
108 #define TZASC_BASE_ADDR 0x32F80000
109 #define MTR_BASE_ADDR 0x32FB0000
110 #define PLATFORM_CTRL_BASE_ADDR 0x32FE0000
112 #define MXS_APBH_BASE 0x33000000
113 #define MXS_GPMI_BASE 0x33002000
114 #define MXS_BCH_BASE 0x33004000
116 #define USB1_BASE_ADDR 0x38100000
117 #define USB2_BASE_ADDR 0x38200000
118 #define USB1_PHY_BASE_ADDR 0x381F0000
119 #define USB2_PHY_BASE_ADDR 0x382F0000
121 #define MXS_LCDIF_BASE LCDIF_BASE_ADDR
123 #define SRC_IPS_BASE_ADDR 0x30390000
124 #define SRC_DDRC_RCR_ADDR 0x30391000
125 #define SRC_DDRC2_RCR_ADDR 0x30391004
127 #define DDRC_DDR_SS_GPR0 0x3d000000
128 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
129 #define DDR_CSD1_BASE_ADDR 0x40000000
131 #if !defined(__ASSEMBLY__)
132 #include <asm/types.h>
133 #include <linux/bitops.h>
136 #define GPR_TZASC_EN BIT(0)
137 #define GPR_TZASC_EN_LOCK BIT(16)
139 #define SRC_SCR_M4_ENABLE_OFFSET 3
140 #define SRC_SCR_M4_ENABLE_MASK BIT(3)
141 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
142 #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
143 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL
144 #define SRC_DDR2_ENABLE_MASK 0x8F000000UL
145 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
146 #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
147 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
148 #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
150 struct iomuxc_gpr_base_regs {
186 struct fuse_bank0_regs {
195 struct fuse_bank1_regs {
236 u32 pllout_monitor_cfg;
237 u32 frac_pllout_div_cfg;
238 u32 sscg_pllout_div_cfg;
241 struct fuse_bank9_regs {
248 /* System Reset Controller (SRC) */
297 u32 mmdc_cpu_mapping;
349 u32 pgc_cpu_0_1_mapping;
357 u32 pgc_cpu_2_3_mapping;
366 u32 cpu_pgc_up_status1;
367 u32 mix_pgc_up_status0;
368 u32 mix_pgc_up_status1;
369 u32 mix_pgc_up_status2;
370 u32 m4_mix_pgc_up_status0;
371 u32 m4_mix_pgc_up_status1;
372 u32 m4_mix_pgc_up_status2;
373 u32 pu_pgc_up_status0;
374 u32 pu_pgc_up_status1;
375 u32 pu_pgc_up_status2;
376 u32 m4_pu_pgc_up_status0;
377 u32 m4_pu_pgc_up_status1;
378 u32 m4_pu_pgc_up_status2;
382 u32 cpu_pgc_dn_status1;
383 u32 mix_pgc_dn_status0;
384 u32 mix_pgc_dn_status1;
385 u32 mix_pgc_dn_status2;
386 u32 m4_mix_pgc_dn_status0;
387 u32 m4_mix_pgc_dn_status1;
388 u32 m4_mix_pgc_dn_status2;
389 u32 pu_pgc_dn_status0;
390 u32 pu_pgc_dn_status1;
391 u32 pu_pgc_dn_status2;
392 u32 m4_pu_pgc_dn_status0;
393 u32 m4_pu_pgc_dn_status1;
394 u32 m4_pu_pgc_dn_status2;
409 u32 pgc_ack_sel_m4_pu;
438 #define WDOG_WDT_MASK BIT(3)
439 #define WDOG_WDZST_MASK BIT(0)
441 u16 wcr; /* Control */
442 u16 wsr; /* Service */
443 u16 wrsr; /* Reset Status */
444 u16 wicr; /* Interrupt Control */
445 u16 wmcr; /* Miscellaneous Control */
448 struct bootrom_sw_info {
450 u8 boot_dev_instance;
460 #define ROM_SW_INFO_ADDR_B0 0x00000968
461 #define ROM_SW_INFO_ADDR_A0 0x000009e8
463 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
464 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
465 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0