1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
7 #define __ASM_ARCH_IMX8M_REGS_H__
11 #include <asm/mach-imx/regs-lcdif.h>
13 #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
14 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
16 #define M4_BOOTROM_BASE_ADDR 0x007E0000
18 #define GPIO1_BASE_ADDR 0X30200000
19 #define GPIO2_BASE_ADDR 0x30210000
20 #define GPIO3_BASE_ADDR 0x30220000
21 #define GPIO4_BASE_ADDR 0x30230000
22 #define GPIO5_BASE_ADDR 0x30240000
23 #define WDOG1_BASE_ADDR 0x30280000
24 #define WDOG2_BASE_ADDR 0x30290000
25 #define WDOG3_BASE_ADDR 0x302A0000
26 #define IOMUXC_BASE_ADDR 0x30330000
27 #define IOMUXC_GPR_BASE_ADDR 0x30340000
28 #define OCOTP_BASE_ADDR 0x30350000
29 #define ANATOP_BASE_ADDR 0x30360000
30 #define CCM_BASE_ADDR 0x30380000
31 #define SRC_BASE_ADDR 0x30390000
32 #define GPC_BASE_ADDR 0x303A0000
34 #define SYSCNT_RD_BASE_ADDR 0x306A0000
35 #define SYSCNT_CMP_BASE_ADDR 0x306B0000
36 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000
38 #define UART1_BASE_ADDR 0x30860000
39 #define UART3_BASE_ADDR 0x30880000
40 #define UART2_BASE_ADDR 0x30890000
41 #define I2C1_BASE_ADDR 0x30A20000
42 #define I2C2_BASE_ADDR 0x30A30000
43 #define I2C3_BASE_ADDR 0x30A40000
44 #define I2C4_BASE_ADDR 0x30A50000
45 #define UART4_BASE_ADDR 0x30A60000
46 #define USDHC1_BASE_ADDR 0x30B40000
47 #define USDHC2_BASE_ADDR 0x30B50000
49 #define USDHC3_BASE_ADDR 0x30B60000
51 #define UART_BASE_ADDR(n) ( \
53 static_assert((n) >= 1 && (n) <= 4); \
56 (n) == 1 ? UART1_BASE_ADDR : \
57 (n) == 2 ? UART2_BASE_ADDR : \
58 (n) == 3 ? UART3_BASE_ADDR : \
62 #define TZASC_BASE_ADDR 0x32F80000
64 #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
65 0x30320000 : 0x32e00000
67 #define SRC_IPS_BASE_ADDR 0x30390000
68 #define SRC_DDRC_RCR_ADDR 0x30391000
69 #define SRC_DDRC2_RCR_ADDR 0x30391004
71 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
72 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
73 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
75 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
76 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
78 #define DDRC_DDR_SS_GPR0 0x3d000000
79 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
80 #define DDR_CSD1_BASE_ADDR 0x40000000
82 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
83 #define FEC_QUIRK_ENET_MAC
85 #define CAAM_ARB_BASE_ADDR (0x00100000)
86 #define CAAM_ARB_END_ADDR (0x00107FFF)
87 #define CAAM_IPS_BASE_ADDR (0x30900000)
88 #define CONFIG_SYS_FSL_SEC_OFFSET (0)
89 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
90 CONFIG_SYS_FSL_SEC_OFFSET)
91 #define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
92 #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
93 CONFIG_SYS_FSL_JR0_OFFSET)
94 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
95 #if !defined(__ASSEMBLY__)
96 #include <asm/types.h>
97 #include <linux/bitops.h>
100 #define GPR_TZASC_EN BIT(0)
101 #define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
102 #define GPR_TZASC_EN_LOCK BIT(16)
103 #define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
105 #define SRC_SCR_M4_ENABLE_OFFSET 3
106 #define SRC_SCR_M4_ENABLE_MASK BIT(3)
107 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
108 #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
109 #define SRC_DDR1_ENABLE_MASK 0x8F000000UL
110 #define SRC_DDR2_ENABLE_MASK 0x8F000000UL
111 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
112 #define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
113 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
114 #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
116 struct iomuxc_gpr_base_regs {
153 struct fuse_bank0_regs {
162 struct fuse_bank0_regs {
172 struct fuse_bank1_regs {
183 struct fuse_bank3_regs {
194 struct fuse_bank9_regs {
201 struct fuse_bank38_regs {
202 u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
212 struct fuse_bank39_regs {
248 u32 pllout_monitor_cfg;
249 u32 frac_pllout_div_cfg;
250 u32 sscg_pllout_div_cfg;
254 u32 audio_pll1_gnrl_ctl;
255 u32 audio_pll1_fdiv_ctl0;
256 u32 audio_pll1_fdiv_ctl1;
257 u32 audio_pll1_sscg_ctl;
258 u32 audio_pll1_mnit_ctl;
259 u32 audio_pll2_gnrl_ctl;
260 u32 audio_pll2_fdiv_ctl0;
261 u32 audio_pll2_fdiv_ctl1;
262 u32 audio_pll2_sscg_ctl;
263 u32 audio_pll2_mnit_ctl;
264 u32 video_pll1_gnrl_ctl;
265 u32 video_pll1_fdiv_ctl0;
266 u32 video_pll1_fdiv_ctl1;
267 u32 video_pll1_sscg_ctl;
268 u32 video_pll1_mnit_ctl;
270 u32 dram_pll_gnrl_ctl;
271 u32 dram_pll_fdiv_ctl0;
272 u32 dram_pll_fdiv_ctl1;
273 u32 dram_pll_sscg_ctl;
274 u32 dram_pll_mnit_ctl;
275 u32 gpu_pll_gnrl_ctl;
277 u32 gpu_pll_locked_ctl1;
278 u32 gpu_pll_mnit_ctl;
279 u32 vpu_pll_gnrl_ctl;
281 u32 vpu_pll_locked_ctl1;
282 u32 vpu_pll_mnit_ctl;
283 u32 arm_pll_gnrl_ctl;
285 u32 arm_pll_locked_ctl1;
286 u32 arm_pll_mnit_ctl;
287 u32 sys_pll1_gnrl_ctl;
288 u32 sys_pll1_div_ctl;
289 u32 sys_pll1_locked_ctl1;
291 u32 sys_pll1_mnit_ctl;
292 u32 sys_pll2_gnrl_ctl;
293 u32 sys_pll2_div_ctl;
294 u32 sys_pll2_locked_ctl1;
295 u32 sys_pll2_mnit_ctl;
296 u32 sys_pll3_gnrl_ctl;
297 u32 sys_pll3_div_ctl;
298 u32 sys_pll3_locked_ctl1;
299 u32 sys_pll3_mnit_ctl;
301 u32 anamix_clk_mnit_ctl;
307 /* System Reset Controller (SRC) */
348 #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
349 #define PWMCR_DOZEEN (1 << 24)
350 #define PWMCR_WAITEN (1 << 23)
351 #define PWMCR_DBGEN (1 << 22)
352 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
353 #define PWMCR_CLKSRC_IPG (1 << 16)
354 #define PWMCR_EN (1 << 0)
365 #define WDOG_WDT_MASK BIT(3)
366 #define WDOG_WDZST_MASK BIT(0)
368 u16 wcr; /* Control */
369 u16 wsr; /* Service */
370 u16 wrsr; /* Reset Status */
371 u16 wicr; /* Interrupt Control */
372 u16 wmcr; /* Miscellaneous Control */
375 struct bootrom_sw_info {
377 u8 boot_dev_instance;
387 #define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
389 #define ROM_SW_INFO_ADDR_A0 0x000009e8
391 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
392 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
393 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
403 u32 mmdc_cpu_mapping;
455 u32 pgc_cpu_0_1_mapping;
463 u32 pgc_cpu_2_3_mapping;
472 u32 cpu_pgc_up_status1;
473 u32 mix_pgc_up_status0;
474 u32 mix_pgc_up_status1;
475 u32 mix_pgc_up_status2;
476 u32 m4_mix_pgc_up_status0;
477 u32 m4_mix_pgc_up_status1;
478 u32 m4_mix_pgc_up_status2;
479 u32 pu_pgc_up_status0;
480 u32 pu_pgc_up_status1;
481 u32 pu_pgc_up_status2;
482 u32 m4_pu_pgc_up_status0;
483 u32 m4_pu_pgc_up_status1;
484 u32 m4_pu_pgc_up_status2;
488 u32 cpu_pgc_dn_status1;
489 u32 mix_pgc_dn_status0;
490 u32 mix_pgc_dn_status1;
491 u32 mix_pgc_dn_status2;
492 u32 m4_mix_pgc_dn_status0;
493 u32 m4_mix_pgc_dn_status1;
494 u32 m4_mix_pgc_dn_status2;
495 u32 pu_pgc_dn_status0;
496 u32 pu_pgc_dn_status1;
497 u32 pu_pgc_dn_status2;
498 u32 m4_pu_pgc_dn_status0;
499 u32 m4_pu_pgc_dn_status1;
500 u32 m4_pu_pgc_dn_status2;
515 u32 pgc_ack_sel_m4_pu;