1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Peng Fan <peng.fan at nxp.com>
8 #include <linux/bitops.h>
11 #include <asm/arch/clock_imx8mq.h>
12 #elif defined(CONFIG_IMX8MM)
13 #include <asm/arch/clock_imx8mm.h>
15 #error "Error no clock.h"
18 #define MHZ(X) ((X) * 1000000UL)
20 /* Mainly for compatible to imx common code. */
44 CLK_ROOT_PRE_DIV1 = 0,
55 CLK_ROOT_POST_DIV1 = 0,
121 struct clk_root_map {
122 enum clk_root_index entry;
123 enum clk_slice_type slice_type;
145 u32 nm_post_root_set;
146 u32 nm_post_root_clr;
147 u32 nm_post_root_tog;
153 u32 db_post_root_set;
154 u32 db_post_root_clr;
155 u32 db_post_root_tog;
162 u32 access_ctrl_root_set;
163 u32 access_ctrl_root_clr;
164 u32 access_ctrl_root_tog;
168 u32 reserved_0[4096];
169 struct ccm_ccgr ccgr_array[192];
170 u32 reserved_1[3328];
171 struct ccm_root core_root[5];
173 struct ccm_root bus_root[12];
175 struct ccm_root ahb_ipg_root[4];
177 struct ccm_root dram_sel;
178 struct ccm_root core_sel;
180 struct ccm_root ip_root[78];
189 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
192 .alt_root_sel = (_m), \
193 .alt_pre_div = (_p), \
194 .apb_root_sel = (_s), \
195 .apb_pre_div = (_k), \
198 struct dram_bypass_clk_setting {
201 enum root_pre_div alt_pre_div;
203 enum root_pre_div apb_pre_div;
206 #define CCGR_CLK_ON_MASK 0x03
207 #define CLK_SRC_ON_MASK 0x03
209 #define CLK_ROOT_ON BIT(28)
210 #define CLK_ROOT_OFF (0 << 28)
211 #define CLK_ROOT_ENABLE_MASK BIT(28)
212 #define CLK_ROOT_ENABLE_SHIFT 28
213 #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
215 /* For SEL, only use 1 bit */
216 #define CLK_ROOT_SRC_MUX_MASK 0x07000000
217 #define CLK_ROOT_SRC_MUX_SHIFT 24
218 #define CLK_ROOT_SRC_0 0x00000000
219 #define CLK_ROOT_SRC_1 0x01000000
220 #define CLK_ROOT_SRC_2 0x02000000
221 #define CLK_ROOT_SRC_3 0x03000000
222 #define CLK_ROOT_SRC_4 0x04000000
223 #define CLK_ROOT_SRC_5 0x05000000
224 #define CLK_ROOT_SRC_6 0x06000000
225 #define CLK_ROOT_SRC_7 0x07000000
227 #define CLK_ROOT_PRE_DIV_MASK (0x00070000)
228 #define CLK_ROOT_PRE_DIV_SHIFT 16
229 #define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
231 #define CLK_ROOT_AUDO_SLOW_EN 0x1000
233 #define CLK_ROOT_AUDO_DIV_MASK 0x700
234 #define CLK_ROOT_AUDO_DIV_SHIFT 0x8
235 #define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
237 /* For CORE: mask is 0x7; For IPG: mask is 0x3 */
238 #define CLK_ROOT_POST_DIV_MASK 0x3f
239 #define CLK_ROOT_CORE_POST_DIV_MASK 0x7
240 #define CLK_ROOT_IPG_POST_DIV_MASK 0x3
241 #define CLK_ROOT_POST_DIV_SHIFT 0
242 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
243 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
244 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
245 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
246 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
247 #define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
248 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
249 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
251 void dram_pll_init(ulong pll_val);
252 void dram_enable_bypass(ulong clk_val);
253 void dram_disable_bypass(void);
254 u32 imx_get_fecclk(void);
255 u32 imx_get_uartclk(void);
256 int clock_init(void);
257 void init_clk_usdhc(u32 index);
258 void init_uart_clk(u32 index);
259 void init_wdog_clk(void);
260 unsigned int mxc_get_clock(enum mxc_clock clk);
261 int clock_enable(enum clk_ccgr_index index, bool enable);
262 int clock_root_enabled(enum clk_root_index clock_id);
263 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
264 enum root_post_div post_div, enum clk_root_src clock_src);
265 int clock_set_target_val(enum clk_root_index clock_id, u32 val);
266 int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
267 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
268 int clock_get_postdiv(enum clk_root_index clock_id,
269 enum root_post_div *post_div);
270 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
271 void mxs_set_lcdclk(u32 base_addr, u32 freq);
272 int set_clk_qspi(void);
273 void enable_ocotp_clk(unsigned char enable);
274 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
275 int set_clk_enet(enum enet_freq type);