1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018, 2021 NXP
6 #ifndef __ASM_ARCH_IMX8_REGS_H__
7 #define __ASM_ARCH_IMX8_REGS_H__
11 #define LPUART_BASE 0x5A060000
13 #define GPT1_BASE_ADDR 0x5D140000
14 #define SCU_LPUART_BASE 0x33220000
15 #define GPIO1_BASE_ADDR 0x5D080000
16 #define GPIO2_BASE_ADDR 0x5D090000
17 #define GPIO3_BASE_ADDR 0x5D0A0000
18 #define GPIO4_BASE_ADDR 0x5D0B0000
19 #define GPIO5_BASE_ADDR 0x5D0C0000
20 #define GPIO6_BASE_ADDR 0x5D0D0000
21 #define GPIO7_BASE_ADDR 0x5D0E0000
22 #define GPIO8_BASE_ADDR 0x5D0F0000
23 #define LPI2C1_BASE_ADDR 0x5A800000
24 #define LPI2C2_BASE_ADDR 0x5A810000
25 #define LPI2C3_BASE_ADDR 0x5A820000
26 #define LPI2C4_BASE_ADDR 0x5A830000
27 #define LPI2C5_BASE_ADDR 0x5A840000
29 #define FEC_QUIRK_ENET_MAC
32 #define LVDS0_PHYCTRL_BASE 0x56221000
33 #define LVDS1_PHYCTRL_BASE 0x56241000
34 #define MIPI0_SS_BASE 0x56220000
35 #define MIPI1_SS_BASE 0x56240000
38 #define APBH_DMA_ARB_BASE_ADDR 0x5B810000
39 #define APBH_DMA_ARB_END_ADDR 0x5B81FFFF
40 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
42 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
43 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
45 #define PASS_OVER_INFO_ADDR 0x0010fe00
47 #define USB_BASE_ADDR 0x5b0d0000
48 #define USB_PHY0_BASE_ADDR 0x5b100000
50 #define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
52 #endif /* __ASM_ARCH_IMX8_REGS_H__ */