1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014 Freescale Semiconductor, Inc.
6 #define MXC_CPU_MX23 0x23
7 #define MXC_CPU_MX25 0x25
8 #define MXC_CPU_MX27 0x27
9 #define MXC_CPU_MX28 0x28
10 #define MXC_CPU_MX31 0x31
11 #define MXC_CPU_MX35 0x35
12 #define MXC_CPU_MX51 0x51
13 #define MXC_CPU_MX53 0x53
14 #define MXC_CPU_MX6SL 0x60
15 #define MXC_CPU_MX6DL 0x61
16 #define MXC_CPU_MX6SX 0x62
17 #define MXC_CPU_MX6Q 0x63
18 #define MXC_CPU_MX6UL 0x64
19 #define MXC_CPU_MX6ULL 0x65
20 #define MXC_CPU_MX6ULZ 0x6B
21 #define MXC_CPU_MX6SOLO 0x66 /* dummy */
22 #define MXC_CPU_MX6SLL 0x67
23 #define MXC_CPU_MX6D 0x6A
24 #define MXC_CPU_MX6DP 0x68
25 #define MXC_CPU_MX6QP 0x69
26 #define MXC_CPU_MX7S 0x71 /* dummy ID */
27 #define MXC_CPU_MX7D 0x72
28 #define MXC_CPU_IMX8MQ 0x82
29 #define MXC_CPU_IMX8MD 0x83 /* dummy ID */
30 #define MXC_CPU_IMX8MQL 0x84 /* dummy ID */
31 #define MXC_CPU_IMX8MM 0x85 /* dummy ID */
32 #define MXC_CPU_IMX8MML 0x86 /* dummy ID */
33 #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
34 #define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
35 #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
36 #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
37 #define MXC_CPU_IMX8MN 0x8b /* dummy ID */
38 #define MXC_CPU_IMX8MP 0x182/* dummy ID */
39 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
40 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */
41 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
42 #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
43 #define MXC_CPU_VF610 0xF6 /* dummy ID */
45 #define MXC_SOC_MX6 0x60
46 #define MXC_SOC_MX7 0x70
47 #define MXC_SOC_IMX8M 0x80
48 #define MXC_SOC_IMX8 0x90 /* dummy */
49 #define MXC_SOC_MX7ULP 0xE0 /* dummy */
51 #define CHIP_REV_1_0 0x10
52 #define CHIP_REV_1_1 0x11
53 #define CHIP_REV_1_2 0x12
54 #define CHIP_REV_1_5 0x15
55 #define CHIP_REV_2_0 0x20
56 #define CHIP_REV_2_1 0x21
57 #define CHIP_REV_2_5 0x25
58 #define CHIP_REV_3_0 0x30
60 #define CHIP_REV_A 0x0
61 #define CHIP_REV_B 0x1
63 #define BOARD_REV_1_0 0x0
64 #define BOARD_REV_2_0 0x1
65 #define BOARD_VER_OFFSET 0x8
68 #define CS0_64M_CS1_64M 1
69 #define CS0_64M_CS1_32M_CS2_32M 2
70 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
72 u32 get_imx_reset_cause(void);
73 ulong get_systemPLLCLK(void);
77 ulong get_PERCLK1(void);
78 ulong get_PERCLK2(void);
79 ulong get_PERCLK3(void);