2 * LayerScape Internal Memory Map
4 * Copyright 2014 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H
10 #define __ARCH_FSL_LSCH3_IMMAP_H_
12 /* This is chassis generation 3 */
15 unsigned long freq_processor[CONFIG_MAX_CPUS];
16 unsigned long freq_systembus;
17 unsigned long freq_ddrbus;
18 unsigned long freq_localbus;
19 unsigned long freq_qe;
20 #ifdef CONFIG_SYS_DPAA_FMAN
21 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
23 #ifdef CONFIG_SYS_DPAA_QBMAN
24 unsigned long freq_qman;
26 #ifdef CONFIG_SYS_DPAA_PME
27 unsigned long freq_pme;
31 /* Global Utilities Block */
33 u32 porsr1; /* POR status 1 */
34 u32 porsr2; /* POR status 2 */
36 u32 gpporcr1; /* General-purpose POR configuration */
37 u32 gpporcr2; /* General-purpose POR configuration 2 */
38 u32 dcfg_fusesr; /* Fuse status register */
41 u8 res_034[0x70-0x34];
42 u32 devdisr; /* Device disable control */
43 u32 devdisr2; /* Device disable control 2 */
44 u32 devdisr3; /* Device disable control 3 */
45 u32 devdisr4; /* Device disable control 4 */
46 u32 devdisr5; /* Device disable control 5 */
47 u32 devdisr6; /* Device disable control 6 */
48 u32 devdisr7; /* Device disable control 7 */
49 u8 res_08c[0x90-0x8c];
50 u32 coredisru; /* uppper portion for support of 64 cores */
51 u32 coredisrl; /* lower portion for support of 64 cores */
52 u8 res_098[0xa0-0x98];
53 u32 pvr; /* Processor version */
54 u32 svr; /* System version */
55 u32 mvr; /* Manufacturing version */
56 u8 res_0ac[0x100-0xac];
57 u32 rcwsr[32]; /* Reset control word status */
59 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
60 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
61 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
62 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
63 u8 res_180[0x200-0x180];
64 u32 scratchrw[32]; /* Scratch Read/Write */
65 u8 res_280[0x300-0x280];
66 u32 scratchw1r[4]; /* Scratch Read (Write once) */
67 u8 res_310[0x400-0x310];
68 u32 bootlocptrl; /* Boot location pointer low-order addr */
69 u32 bootlocptrh; /* Boot location pointer high-order addr */
70 u8 res_408[0x500-0x408];
71 u8 res_500[0x740-0x500]; /* add more registers when needed */
72 u32 tp_ityp[64]; /* Topology Initiator Type Register */
76 } tp_cluster[3]; /* Core Cluster n Topology Register */
77 u8 res_858[0x1000-0x858];
80 #define TP_ITYP_AV 0x00000001 /* Initiator available */
81 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
82 #define TP_ITYP_TYPE_ARM 0x0
83 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
84 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
85 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
86 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
87 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
88 #define TY_ITYP_VER_A7 0x1
89 #define TY_ITYP_VER_A53 0x2
90 #define TY_ITYP_VER_A57 0x3
92 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
93 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
94 #define TP_INIT_PER_CLUSTER 4
96 struct ccsr_clk_cluster_group {
100 u8 res_14[0x20-0x14];
102 u8 res_60[0x80-0x60];
105 u8 res_84[0xa0-0x84];
107 u8 res_e0[0x100-0xe0];
110 struct ccsr_clk_ctrl {
112 u32 csr; /* core cluster n clock control status */
113 u8 res_04[0x20-0x04];
116 #endif /* __ARCH_FSL_LSCH3_IMMAP_H */