1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2018 NXP
4 * Copyright 2014 Freescale Semiconductor, Inc.
7 #ifndef __FSL_STREAM_ID_H
8 #define __FSL_STREAM_ID_H
11 * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
12 * devices are not hardwired and are programmed by sw. There are a limited
13 * number of stream IDs available, and the partitioning of them is scenario
14 * dependent. This header defines the partitioning between legacy,
15 * PCI, and DPAA2 devices.
17 * This partitioning can be customized in this file depending
18 * on the specific hardware config:
20 * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
21 * -all legacy devices get a unique stream ID assigned and programmed in
22 * their AMQR registers by u-boot
25 * -there is a range of stream IDs set aside for PCI in this
26 * file. U-boot will scan the PCI bus and for each device discovered:
27 * -allocate a streamID
28 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
29 * -set a msi-map entry in the PEXn controller node in the
30 * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
31 * for more info on the msi-map definition)
32 * -set a iommu-map entry in the PEXn controller node in the
33 * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
34 * for more info on the iommu-map definition)
37 * -u-boot will allocate a range of stream IDs to be used by the Management
38 * Complex for containers and will set these values in the MC DPC image.
39 * -u-boot will fixup the iommu-map property in the fsl-mc node in the
40 * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
41 * for more info on the msi-map definition)
42 * -the MC is responsible for allocating and setting up 'isolation context
43 * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
45 * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
46 * each of the different bus masters. The relationship between
47 * the AMQ registers and stream IDs is defined in the table below:
48 * AMQ bit streamID bit
49 * ---------------------------
50 * PL[18] 9 // privilege bit
51 * BMT[17] 8 // bypass translation
52 * VA[16] 7 // reserved
54 * ICID[14:7] - // unused
55 * ICID[6:0] 6-0 // isolation context id
56 * ----------------------------
60 #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
61 #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
63 #define FSL_INVALID_STREAM_ID 0
65 #define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
68 #define FSL_USB1_STREAM_ID 1
69 #define FSL_USB2_STREAM_ID 2
70 #define FSL_SDMMC_STREAM_ID 3
71 #define FSL_SATA1_STREAM_ID 4
73 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
74 #define FSL_SATA2_STREAM_ID 5
77 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
78 #define FSL_DMA_STREAM_ID 6
79 #elif defined(CONFIG_ARCH_LS1088A)
80 #define FSL_DMA_STREAM_ID 5
83 /* PCI - programmed in PEXn_LUT */
84 #define FSL_PEX_STREAM_ID_START 7
86 #ifdef CONFIG_ARCH_LX2160A
87 #define FSL_PEX_STREAM_ID_NUM (0x100)
90 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
91 #define FSL_PEX_STREAM_ID_END 22
92 #elif defined(CONFIG_ARCH_LS1088A)
93 #define FSL_PEX_STREAM_ID_END 18
97 /* DPAA2 - set in MC DPC and alloced by MC */
98 #define FSL_DPAA2_STREAM_ID_START 23
99 #define FSL_DPAA2_STREAM_ID_END 63