2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
10 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
11 #define gur_in32(a) in_le32(a)
12 #define gur_out32(a, v) out_le32(a, v)
13 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
14 #define gur_in32(a) in_be32(a)
15 #define gur_out32(a, v) out_be32(a, v)
18 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
19 #define scfg_in32(a) in_le32(a)
20 #define scfg_out32(a, v) out_le32(a, v)
21 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
22 #define scfg_in32(a) in_be32(a)
23 #define scfg_out32(a, v) out_be32(a, v)
32 #define CPU_TYPE_ENTRY(n, v, nc) \
33 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
35 #define SVR_WO_E 0xFFFFFE
36 #define SVR_LS1043 0x879204
37 #define SVR_LS2045 0x870120
38 #define SVR_LS2080 0x870110
39 #define SVR_LS2085 0x870100
41 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
42 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
43 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
44 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
46 #ifdef CONFIG_FSL_LSCH3
47 void fsl_lsch3_early_init_f(void);
48 #elif defined(CONFIG_FSL_LSCH2)
49 void fsl_lsch2_early_init_f(void);
52 void cpu_name(char *name);
53 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */