2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
10 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
11 #define gur_in32(a) in_le32(a)
12 #define gur_out32(a, v) out_le32(a, v)
13 #elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
14 #define gur_in32(a) in_be32(a)
15 #define gur_out32(a, v) out_be32(a, v)
18 #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
19 #define scfg_in32(a) in_le32(a)
20 #define scfg_out32(a, v) out_le32(a, v)
21 #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
22 #define scfg_in32(a) in_be32(a)
23 #define scfg_out32(a, v) out_be32(a, v)
26 #ifdef CONFIG_SYS_FSL_PEX_LUT_LE
27 #define pex_lut_in32(a) in_le32(a)
28 #define pex_lut_out32(a, v) out_le32(a, v)
29 #elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
30 #define pex_lut_in32(a) in_be32(a)
31 #define pex_lut_out32(a, v) out_be32(a, v)
40 #define CPU_TYPE_ENTRY(n, v, nc) \
41 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
43 #define SVR_WO_E 0xFFFFFE
44 #define SVR_LS1012A 0x870400
45 #define SVR_LS1043A 0x879200
46 #define SVR_LS1023A 0x879208
47 #define SVR_LS1046A 0x870700
48 #define SVR_LS1026A 0x870708
49 #define SVR_LS2045A 0x870120
50 #define SVR_LS2080A 0x870110
51 #define SVR_LS2085A 0x870100
52 #define SVR_LS2040A 0x870130
54 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
55 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
56 #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
57 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
58 #define IS_SVR_REV(svr, maj, min) \
59 ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
61 /* ahci port register default value */
62 #define AHCI_PORT_PHY_1_CFG 0xa003fffe
63 #define AHCI_PORT_TRANS_CFG 0x08000029
64 #define AHCI_PORT_AXICC_CFG 0x3fffffff
66 /* AHCI (sata) register map */
68 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
69 u32 pcfg; /* port config */
70 u32 ppcfg; /* port phy1 config */
71 u32 pp2c; /* port phy2 config */
72 u32 pp3c; /* port phy3 config */
73 u32 pp4c; /* port phy4 config */
74 u32 pp5c; /* port phy5 config */
75 u32 axicc; /* AXI cache control */
76 u32 paxic; /* port AXI config */
77 u32 axipc; /* AXI PROT control */
78 u32 ptc; /* port Trans Config */
79 u32 pts; /* port Trans Status */
80 u32 plc; /* port link config */
81 u32 plc1; /* port link config1 */
82 u32 plc2; /* port link config2 */
83 u32 pls; /* port link status */
84 u32 pls1; /* port link status1 */
85 u32 pcmdc; /* port CMD config */
86 u32 ppcs; /* port phy control status */
87 u32 pberr; /* port 0/1 BIST error */
88 u32 cmds; /* port 0/1 CMD status error */
91 #ifdef CONFIG_FSL_LSCH3
92 void fsl_lsch3_early_init_f(void);
93 #elif defined(CONFIG_FSL_LSCH2)
94 void fsl_lsch2_early_init_f(void);
97 void cpu_name(char *name);
98 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
99 void erratum_a009635(void);
102 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
103 void erratum_a010315(void);
106 bool soc_has_dp_ddr(void);
107 bool soc_has_aiop(void);
108 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */