1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * LayerScape Internal Memory Map
5 * Copyright 2017-2018 NXP
6 * Copyright 2014 Freescale Semiconductor, Inc.
9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
10 #define __ARCH_FSL_LSCH3_IMMAP_H_
12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
18 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
22 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
23 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
24 #ifndef CONFIG_NXP_LSCH3_2
25 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
27 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
28 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
29 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
30 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
31 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
33 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
34 #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
36 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
37 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
38 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
39 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
41 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
42 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
43 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
44 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
46 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
47 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
48 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
49 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
50 #ifdef CONFIG_NXP_LSCH3_2
51 #define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000)
52 #define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000)
53 #define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000)
54 #define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000)
56 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
57 #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
58 #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
60 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
61 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
63 /* TZ Address Space Controller Definitions */
64 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
65 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
66 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
67 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
68 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
69 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
70 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
71 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
72 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
73 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
74 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
75 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
76 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
79 #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
80 #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
83 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
86 #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
87 #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
88 #define CONFIG_SYS_FSL_SEC_ADDR \
89 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
90 #define CONFIG_SYS_FSL_JR0_ADDR \
91 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
94 #ifdef CONFIG_NXP_LSCH3_2
95 /* RCW_SRC field in Power-On Reset Control Register 1 */
96 #define RCW_SRC_MASK 0x07800000
97 #define RCW_SRC_BIT 23
99 /* CFG_RCW_SRC[3:0] */
100 #define RCW_SRC_TYPE_MASK 0x8
101 #define RCW_SRC_ADDR_OFFSET_8MB 0x800000
103 /* RCW SRC HARDCODED */
104 #define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
106 #define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
107 #define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
108 #define RCW_SRC_I2C1_VAL 0xa /* 0xa */
109 #define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
110 #define RCW_SRC_FLEXSPI_NAND2K_VAL 0xc /* 0xc */
111 #define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
112 #define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
113 #define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
115 #define RCW_SRC_MASK (0xFF800000)
116 #define RCW_SRC_BIT 23
117 /* CFG_RCW_SRC[6:0] */
118 #define RCW_SRC_TYPE_MASK (0x70)
120 /* RCW SRC HARDCODED */
121 #define RCW_SRC_HARDCODED_VAL (0x10) /* 0x10 - 0x1f */
122 /* Hardcoded will also have CFG_RCW_SRC[7] as 1. 0x90 - 0x9f */
125 #define RCW_SRC_NOR_VAL (0x20)
126 #define NOR_TYPE_MASK (0x10)
127 #define NOR_16B_VAL (0x0) /* 0x20 - 0x2f */
128 #define NOR_32B_VAL (0x10) /* 0x30 - 0x3f */
130 /* RCW SRC Serial Flash
131 * 1. SERIAL NOR (QSPI)
132 * 2. OTHERS (SD/MMC, SPI, I2C1
134 #define RCW_SRC_SERIAL_MASK (0x7F)
135 #define RCW_SRC_QSPI_VAL (0x62) /* 0x62 */
136 #define RCW_SRC_SD_CARD_VAL (0x40) /* 0x40 */
137 #define RCW_SRC_EMMC_VAL (0x41) /* 0x41 */
138 #define RCW_SRC_I2C1_VAL (0x49) /* 0x49 */
142 /* Security Monitor */
143 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
146 #define SMMU_SCR0 (SMMU_BASE + 0x0)
147 #define SMMU_SCR1 (SMMU_BASE + 0x4)
148 #define SMMU_SCR2 (SMMU_BASE + 0x8)
149 #define SMMU_SACR (SMMU_BASE + 0x10)
150 #define SMMU_IDR0 (SMMU_BASE + 0x20)
151 #define SMMU_IDR1 (SMMU_BASE + 0x24)
153 #define SMMU_NSCR0 (SMMU_BASE + 0x400)
154 #define SMMU_NSCR2 (SMMU_BASE + 0x408)
155 #define SMMU_NSACR (SMMU_BASE + 0x410)
157 #define SCR0_CLIENTPD_MASK 0x00000001
158 #define SCR0_USFCFG_MASK 0x00000400
162 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
163 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
164 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
165 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
166 #ifdef CONFIG_ARCH_LS1088A
167 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
168 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
169 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
171 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
172 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
173 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
174 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
177 /* Device Configuration */
178 #define DCFG_BASE 0x01e00000
179 #define DCFG_PORSR1 0x000
180 #define DCFG_PORSR1_RCW_SRC 0xff800000
181 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
182 #define DCFG_RCWSR13 0x130
183 #define DCFG_RCWSR13_DSPI (0 << 8)
184 #define DCFG_RCWSR15 0x138
185 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
187 #define DCFG_DCSR_BASE 0X700100000ULL
188 #define DCFG_DCSR_PORCR1 0x000
190 /* Interrupt Sampling Control */
191 #define ISC_BASE 0x01F70000
192 #define IRQCR_OFFSET 0x14
194 /* Supplemental Configuration */
195 #define SCFG_BASE 0x01fc0000
196 #define SCFG_USB3PRM1CR 0x000
197 #define SCFG_USB3PRM1CR_INIT 0x27672b2a
198 #define SCFG_USB_TXVREFTUNE 0x9
199 #define SCFG_USB_SQRXTUNE_MASK 0x7
200 #define SCFG_QSPICLKCTLR 0x10
202 #define DCSR_BASE 0x700000000ULL
203 #define DCSR_USB_PHY1 0x4600000
204 #define DCSR_USB_PHY2 0x4610000
205 #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
206 #define USB_PHY_RX_EQ_VAL_1 0x0000
207 #define USB_PHY_RX_EQ_VAL_2 0x0080
208 #define USB_PHY_RX_EQ_VAL_3 0x0380
209 #define USB_PHY_RX_EQ_VAL_4 0x0b80
211 #define TP_ITYP_AV 0x00000001 /* Initiator available */
212 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
213 #define TP_ITYP_TYPE_ARM 0x0
214 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
215 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
216 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
217 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
218 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
219 #define TY_ITYP_VER_A7 0x1
220 #define TY_ITYP_VER_A53 0x2
221 #define TY_ITYP_VER_A57 0x3
222 #define TY_ITYP_VER_A72 0x4
224 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
225 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
226 #define TP_INIT_PER_CLUSTER 4
227 /* This is chassis generation 3 */
230 unsigned long freq_processor[CONFIG_MAX_CPUS];
231 /* frequency of platform PLL */
232 unsigned long freq_systembus;
233 unsigned long freq_ddrbus;
234 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
235 unsigned long freq_ddrbus2;
237 unsigned long freq_localbus;
238 unsigned long freq_qe;
239 #ifdef CONFIG_SYS_DPAA_FMAN
240 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
242 #ifdef CONFIG_SYS_DPAA_QBMAN
243 unsigned long freq_qman;
245 #ifdef CONFIG_SYS_DPAA_PME
246 unsigned long freq_pme;
250 /* Global Utilities Block */
252 u32 porsr1; /* POR status 1 */
253 u32 porsr2; /* POR status 2 */
254 u8 res_008[0x20-0x8];
255 u32 gpporcr1; /* General-purpose POR configuration */
256 u32 gpporcr2; /* General-purpose POR configuration 2 */
259 u8 res_030[0x60-0x30];
260 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
261 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
262 #if defined(CONFIG_ARCH_LS1088A)
263 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
264 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
266 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
267 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
269 u32 dcfg_fusesr; /* Fuse status register */
270 u8 res_064[0x70-0x64];
271 u32 devdisr; /* Device disable control 1 */
272 u32 devdisr2; /* Device disable control 2 */
273 u32 devdisr3; /* Device disable control 3 */
274 u32 devdisr4; /* Device disable control 4 */
275 u32 devdisr5; /* Device disable control 5 */
276 u32 devdisr6; /* Device disable control 6 */
277 u8 res_088[0x94-0x88];
278 u32 coredisr; /* Device disable control 7 */
279 #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
280 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
281 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
282 #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
283 #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
284 #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
285 #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
286 #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
287 #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
288 #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
289 #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
290 #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
291 #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
292 #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
293 #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
294 #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
295 #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
296 #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
297 #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
298 #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
299 #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
300 #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
301 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
302 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
303 u8 res_098[0xa0-0x98];
304 u32 pvr; /* Processor version */
305 u32 svr; /* System version */
306 u8 res_0a8[0x100-0xa8];
307 u32 rcwsr[30]; /* Reset control word status */
309 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
310 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
311 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
312 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
313 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
314 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
316 #if defined(CONFIG_ARCH_LS2080A)
317 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
318 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
319 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
320 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
321 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
322 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
323 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
324 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
325 #define FSL_CHASSIS3_SRDS1_REGSR 29
326 #define FSL_CHASSIS3_SRDS2_REGSR 29
327 #elif defined(CONFIG_ARCH_LS1088A)
328 #define FSL_CHASSIS3_EC1_REGSR 26
329 #define FSL_CHASSIS3_EC2_REGSR 26
330 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
331 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
332 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
333 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
334 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
335 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
336 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
337 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
338 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
339 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
340 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
341 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
342 #define FSL_CHASSIS3_SRDS1_REGSR 29
343 #define FSL_CHASSIS3_SRDS2_REGSR 30
345 #define RCW_SB_EN_REG_INDEX 9
346 #define RCW_SB_EN_MASK 0x00000400
348 u8 res_178[0x200-0x178];
349 u32 scratchrw[16]; /* Scratch Read/Write */
350 u8 res_240[0x300-0x240];
351 u32 scratchw1r[4]; /* Scratch Read (Write once) */
352 u8 res_310[0x400-0x310];
353 u32 bootlocptrl; /* Boot location pointer low-order addr */
354 u32 bootlocptrh; /* Boot location pointer high-order addr */
355 u8 res_408[0x520-0x408];
358 u8 res_528[0x530-0x528]; /* add more registers when needed */
360 u8 res_534[0x550-0x534]; /* add more registers when needed */
363 u8 res_558[0x570-0x558]; /* add more registers when needed */
365 u8 res_574[0x590-0x574]; /* add more registers when needed */
368 u8 res_598[0x620-0x598]; /* add more registers when needed */
369 u32 gencr[7]; /* General Control Registers */
370 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
371 u32 cgensr1; /* Core General Status Register */
372 u8 res_644[0x660-0x644]; /* add more registers when needed */
373 u32 cgencr1; /* Core General Control Register */
374 u8 res_664[0x740-0x664]; /* add more registers when needed */
375 u32 tp_ityp[64]; /* Topology Initiator Type Register */
379 } tp_cluster[4]; /* Core cluster n Topology Register */
380 u8 res_864[0x920-0x864]; /* add more registers when needed */
381 u32 ioqoscr[8]; /*I/O Quality of Services Register */
383 u8 res_944[0x960-0x944]; /* add more registers when needed */
385 u8 res_964[0x990-0x964]; /* add more registers when needed */
387 u8 res_994[0xa00-0x994]; /* add more registers when needed */
388 u32 sdbgcr; /*Secure Debug Confifuration Register */
389 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
392 u8 res_858[0x1000-0xc00];
395 struct ccsr_clk_cluster_group {
399 u8 res_14[0x20-0x14];
401 u8 res_60[0x80-0x60];
404 u8 res_84[0xa0-0x84];
406 u8 res_e0[0x100-0xe0];
409 struct ccsr_clk_ctrl {
411 u32 csr; /* core cluster n clock control status */
412 u8 res_04[0x20-0x04];
417 u32 rstcr; /* 0x000 */
418 u32 rstcrsp; /* 0x004 */
419 u8 res_008[0x10-0x08]; /* 0x008 */
420 u32 rstrqmr1; /* 0x010 */
421 u32 rstrqmr2; /* 0x014 */
422 u32 rstrqsr1; /* 0x018 */
423 u32 rstrqsr2; /* 0x01c */
424 u32 rstrqwdtmrl; /* 0x020 */
425 u32 rstrqwdtmru; /* 0x024 */
426 u8 res_028[0x30-0x28]; /* 0x028 */
427 u32 rstrqwdtsrl; /* 0x030 */
428 u32 rstrqwdtsru; /* 0x034 */
429 u8 res_038[0x60-0x38]; /* 0x038 */
430 u32 brrl; /* 0x060 */
431 u32 brru; /* 0x064 */
432 u8 res_068[0x80-0x68]; /* 0x068 */
433 u32 pirset; /* 0x080 */
434 u32 pirclr; /* 0x084 */
435 u8 res_088[0x90-0x88]; /* 0x088 */
436 u32 brcorenbr; /* 0x090 */
437 u8 res_094[0x100-0x94]; /* 0x094 */
438 u32 rcw_reqr; /* 0x100 */
439 u32 rcw_completion; /* 0x104 */
440 u8 res_108[0x110-0x108]; /* 0x108 */
441 u32 pbi_reqr; /* 0x110 */
442 u32 pbi_completion; /* 0x114 */
443 u8 res_118[0xa00-0x118]; /* 0x118 */
444 u32 qmbm_warmrst; /* 0xa00 */
445 u32 soc_warmrst; /* 0xa04 */
446 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
447 u32 ip_rev1; /* 0xbf8 */
448 u32 ip_rev2; /* 0xbfc */
453 u32 rstctl; /* Reset Control Register */
454 u32 pllcr0; /* PLL Control Register 0 */
455 u32 pllcr1; /* PLL Control Register 1 */
456 u32 pllcr2; /* PLL Control Register 2 */
457 u32 pllcr3; /* PLL Control Register 3 */
458 u32 pllcr4; /* PLL Control Register 4 */
459 u32 pllcr5; /* PLL Control Register 5 */
462 u8 res1[0x90 - 0x40];
463 u32 srdstcalcr; /* TX Calibration Control */
464 u32 srdstcalcr1; /* TX Calibration Control1 */
465 u8 res2[0xa0 - 0x98];
466 u32 srdsrcalcr; /* RX Calibration Control */
467 u32 srdsrcalcr1; /* RX Calibration Control1 */
468 u8 res3[0xb0 - 0xa8];
469 u32 srdsgr0; /* General Register 0 */
470 u8 res4[0x800 - 0xb4];
472 u32 gcr0; /* General Control Register 0 */
473 u32 gcr1; /* General Control Register 1 */
474 u32 gcr2; /* General Control Register 2 */
475 u32 ssc0; /* Speed Switch Control 0 */
476 u32 rec0; /* Receive Equalization Control 0 */
477 u32 rec1; /* Receive Equalization Control 1 */
478 u32 tec0; /* Transmit Equalization Control 0 */
479 u32 ssc1; /* Speed Switch Control 1 */
480 u8 res1[0x840 - 0x820];
482 u8 res5[0x19fc - 0xa00];
485 #endif /*__ASSEMBLY__*/
486 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */