arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * LayerScape Internal Memory Map
   4  *
   5  * Copyright (C) 2017 NXP Semiconductors
   6  * Copyright 2014 Freescale Semiconductor, Inc.
   7  */
   8
   9 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
  10 #define __ARCH_FSL_LSCH3_IMMAP_H_
  11
  12 #define CONFIG_SYS_IMMR                         0x01000000
  13 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  14 #define CONFIG_SYS_FSL_DDR2_ADDR                (CONFIG_SYS_IMMR + 0x00090000)
  15 #define CONFIG_SYS_FSL_DDR3_ADDR                0x08210000
  16 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00E00000)
  17 #define CONFIG_SYS_FSL_PMU_ADDR                 (CONFIG_SYS_IMMR + 0x00E30000)
  18 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00E60000)
  19 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR        (CONFIG_SYS_IMMR + 0x00300000)
  20 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR        (CONFIG_SYS_IMMR + 0x00310000)
  21 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR        (CONFIG_SYS_IMMR + 0x00370000)
  22 #define SYS_FSL_QSPI_ADDR                       (CONFIG_SYS_IMMR + 0x010c0000)
  23 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x01140000)
  24 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x01240000)
  25 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011C0500)
  26 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011C0600)
  27 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR      0x023d0000
  28 #define CONFIG_SYS_FSL_TIMER_ADDR               0x023e0000
  29 #define CONFIG_SYS_FSL_PMU_CLTBENR              (CONFIG_SYS_FSL_PMU_ADDR + \
  30                                                  0x18A0)
  31 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
  32 #define FSL_LSCH3_SVR           (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
  33
  34 #define CONFIG_SYS_FSL_WRIOP1_ADDR              (CONFIG_SYS_IMMR + 0x7B80000)
  35 #define CONFIG_SYS_FSL_WRIOP1_MDIO1     (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
  36 #define CONFIG_SYS_FSL_WRIOP1_MDIO2     (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
  37 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR        (CONFIG_SYS_IMMR + 0xEA0000)
  38
  39 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR            0x70012c000ULL
  40 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR           0x70012d000ULL
  41 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR           0x700132000ULL
  42 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR           0x700133000ULL
  43
  44 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01000000)
  45 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01010000)
  46 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01020000)
  47 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01030000)
  48 #define GPIO4_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01330000)
  49 #define GPIO4_GPDIR_ADDR                        (GPIO4_BASE_ADDR + 0x0)
  50 #define GPIO4_GPDAT_ADDR                        (GPIO4_BASE_ADDR + 0x8)
  51
  52 #define CONFIG_SYS_XHCI_USB1_ADDR               (CONFIG_SYS_IMMR + 0x02100000)
  53 #define CONFIG_SYS_XHCI_USB2_ADDR               (CONFIG_SYS_IMMR + 0x02110000)
  54
  55 /* TZ Address Space Controller Definitions */
  56 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
  57 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
  58 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
  59 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
  60 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
  61 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  62 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  63 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  64 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  65 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  66 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  67 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  68 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  69
  70 /* SATA */
  71 #define AHCI_BASE_ADDR1                         (CONFIG_SYS_IMMR + 0x02200000)
  72 #define AHCI_BASE_ADDR2                         (CONFIG_SYS_IMMR + 0x02210000)
  73
  74 /* SFP */
  75 #define CONFIG_SYS_SFP_ADDR             (CONFIG_SYS_IMMR + 0x00e80200)
  76
  77 /* SEC */
  78 #define CONFIG_SYS_FSL_SEC_OFFSET               0x07000000ull
  79 #define CONFIG_SYS_FSL_JR0_OFFSET               0x07010000ull
  80 #define CONFIG_SYS_FSL_SEC_ADDR \
  81         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
  82 #define CONFIG_SYS_FSL_JR0_ADDR \
  83         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
  84
  85 #ifdef CONFIG_TFABOOT
  86 #ifdef CONFIG_FSL_LSCH3_2
  87 /* RCW_SRC field in Power-On Reset Control Register 1 */
  88 #define RCW_SRC_MASK                    0x07800000
  89 #define RCW_SRC_BIT                     23
  90
  91 /* CFG_RCW_SRC[3:0] */
  92 #define RCW_SRC_TYPE_MASK               0x8
  93 #define RCW_SRC_ADDR_OFFSET_8MB         0x800000
  94
  95 /* RCW SRC HARDCODED */
  96 #define RCW_SRC_HARDCODED_VAL           0x0     /* 0x00 - 0x07 */
  97
  98 #define RCW_SRC_SDHC1_VAL               0x8     /* 0x8 */
  99 #define RCW_SRC_SDHC2_VAL               0x9     /* 0x9 */
 100 #define RCW_SRC_I2C1_VAL                0xa     /* 0xa */
 101 #define RCW_SRC_RESERVED_UART_VAL       0xb     /* 0xb */
 102 #define RCW_SRC_FLEXSPI_NAND2K_VAL      0xc     /* 0xc */
 103 #define RCW_SRC_FLEXSPI_NAND4K_VAL      0xd     /* 0xd */
 104 #define RCW_SRC_RESERVED_1_VAL          0xe     /* 0xe */
 105 #define RCW_SRC_FLEXSPI_NOR_24B         0xf     /* 0xf */
 106 #else
 107 #define RCW_SRC_MASK                    (0xFF800000)
 108 #define RCW_SRC_BIT                     23
 109 /* CFG_RCW_SRC[6:0] */
 110 #define RCW_SRC_TYPE_MASK               (0x70)
 111
 112 /* RCW SRC HARDCODED */
 113 #define RCW_SRC_HARDCODED_VAL           (0x10)     /* 0x10 - 0x1f */
 114 /* Hardcoded will also have CFG_RCW_SRC[7] as 1.   0x90 - 0x9f */
 115
 116 /* RCW SRC NOR */
 117 #define RCW_SRC_NOR_VAL                 (0x20)
 118 #define NOR_TYPE_MASK                   (0x10)
 119 #define NOR_16B_VAL                     (0x0)       /* 0x20 - 0x2f */
 120 #define NOR_32B_VAL                     (0x10)       /* 0x30 - 0x3f */
 121
 122 /* RCW SRC Serial Flash
 123  * 1. SERIAL NOR (QSPI)
 124  * 2. OTHERS (SD/MMC, SPI, I2C1
 125  */
 126 #define RCW_SRC_SERIAL_MASK             (0x7F)
 127 #define RCW_SRC_QSPI_VAL                (0x62)     /* 0x62 */
 128 #define RCW_SRC_SD_CARD_VAL             (0x40)     /* 0x40 */
 129 #define RCW_SRC_EMMC_VAL                (0x41)     /* 0x41 */
 130 #define RCW_SRC_I2C1_VAL                (0x49)     /* 0x49 */
 131 #endif
 132 #endif
 133
 134 /* Security Monitor */
 135 #define CONFIG_SYS_SEC_MON_ADDR         (CONFIG_SYS_IMMR + 0x00e90000)
 136
 137 /* MMU 500 */
 138 #define SMMU_SCR0                       (SMMU_BASE + 0x0)
 139 #define SMMU_SCR1                       (SMMU_BASE + 0x4)
 140 #define SMMU_SCR2                       (SMMU_BASE + 0x8)
 141 #define SMMU_SACR                       (SMMU_BASE + 0x10)
 142 #define SMMU_IDR0                       (SMMU_BASE + 0x20)
 143 #define SMMU_IDR1                       (SMMU_BASE + 0x24)
 144
 145 #define SMMU_NSCR0                      (SMMU_BASE + 0x400)
 146 #define SMMU_NSCR2                      (SMMU_BASE + 0x408)
 147 #define SMMU_NSACR                      (SMMU_BASE + 0x410)
 148
 149 #define SCR0_CLIENTPD_MASK              0x00000001
 150 #define SCR0_USFCFG_MASK                0x00000400
 151
 152
 153 /* PCIe */
 154 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
 155 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
 156 #define CONFIG_SYS_PCIE3_ADDR                   (CONFIG_SYS_IMMR + 0x2600000)
 157 #define CONFIG_SYS_PCIE4_ADDR                   (CONFIG_SYS_IMMR + 0x2700000)
 158 #ifdef CONFIG_ARCH_LS1088A
 159 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x2000000000ULL
 160 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x2800000000ULL
 161 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x3000000000ULL
 162 #else
 163 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x1000000000ULL
 164 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x1200000000ULL
 165 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x1400000000ULL
 166 #define CONFIG_SYS_PCIE4_PHYS_ADDR              0x1600000000ULL
 167 #endif
 168
 169 /* Device Configuration */
 170 #define DCFG_BASE               0x01e00000
 171 #define DCFG_PORSR1                     0x000
 172 #define DCFG_PORSR1_RCW_SRC             0xff800000
 173 #define DCFG_PORSR1_RCW_SRC_NOR         0x12f00000
 174 #define DCFG_RCWSR13                    0x130
 175 #define DCFG_RCWSR13_DSPI               (0 << 8)
 176 #define DCFG_RCWSR15                    0x138
 177 #define DCFG_RCWSR15_IFCGRPABASE_QSPI   0x3
 178
 179 #define DCFG_DCSR_BASE          0X700100000ULL
 180 #define DCFG_DCSR_PORCR1                0x000
 181
 182 /* Interrupt Sampling Control */
 183 #define ISC_BASE                0x01F70000
 184 #define IRQCR_OFFSET            0x14
 185
 186 /* Supplemental Configuration */
 187 #define SCFG_BASE               0x01fc0000
 188 #define SCFG_USB3PRM1CR                 0x000
 189 #define SCFG_USB3PRM1CR_INIT            0x27672b2a
 190 #define SCFG_USB_TXVREFTUNE             0x9
 191 #define SCFG_USB_SQRXTUNE_MASK  0x7
 192 #define SCFG_QSPICLKCTLR        0x10
 193
 194 #define DCSR_BASE               0x700000000ULL
 195 #define DCSR_USB_PHY1                   0x4600000
 196 #define DCSR_USB_PHY2                   0x4610000
 197 #define DCSR_USB_PHY_RX_OVRD_IN_HI      0x200C
 198 #define USB_PHY_RX_EQ_VAL_1             0x0000
 199 #define USB_PHY_RX_EQ_VAL_2             0x0080
 200 #define USB_PHY_RX_EQ_VAL_3             0x0380
 201 #define USB_PHY_RX_EQ_VAL_4             0x0b80
 202
 203 #define TP_ITYP_AV              0x00000001      /* Initiator available */
 204 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
 205 #define TP_ITYP_TYPE_ARM        0x0
 206 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
 207 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
 208 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
 209 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
 210 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
 211 #define TY_ITYP_VER_A7          0x1
 212 #define TY_ITYP_VER_A53         0x2
 213 #define TY_ITYP_VER_A57         0x3
 214 #define TY_ITYP_VER_A72         0x4
 215
 216 #define TP_CLUSTER_EOC          0x80000000      /* end of clusters */
 217 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 218 #define TP_INIT_PER_CLUSTER     4
 219 /* This is chassis generation 3 */
 220 #ifndef __ASSEMBLY__
 221 struct sys_info {
 222         unsigned long freq_processor[CONFIG_MAX_CPUS];
 223         /* frequency of platform PLL */
 224         unsigned long freq_systembus;
 225         unsigned long freq_ddrbus;
 226 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 227         unsigned long freq_ddrbus2;
 228 #endif
 229         unsigned long freq_localbus;
 230         unsigned long freq_qe;
 231 #ifdef CONFIG_SYS_DPAA_FMAN
 232         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
 233 #endif
 234 #ifdef CONFIG_SYS_DPAA_QBMAN
 235         unsigned long freq_qman;
 236 #endif
 237 #ifdef CONFIG_SYS_DPAA_PME
 238         unsigned long freq_pme;
 239 #endif
 240 };
 241
 242 /* Global Utilities Block */
 243 struct ccsr_gur {
 244         u32     porsr1;         /* POR status 1 */
 245         u32     porsr2;         /* POR status 2 */
 246         u8      res_008[0x20-0x8];
 247         u32     gpporcr1;       /* General-purpose POR configuration */
 248         u32     gpporcr2;       /* General-purpose POR configuration 2 */
 249         u32     gpporcr3;
 250         u32     gpporcr4;
 251         u8      res_030[0x60-0x30];
 252 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK       0x1F
 253 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK    0x1F
 254 #if defined(CONFIG_ARCH_LS1088A)
 255 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT      25
 256 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT   20
 257 #else
 258 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT      2
 259 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT   7
 260 #endif
 261         u32     dcfg_fusesr;    /* Fuse status register */
 262         u8      res_064[0x70-0x64];
 263         u32     devdisr;        /* Device disable control 1 */
 264         u32     devdisr2;       /* Device disable control 2 */
 265         u32     devdisr3;       /* Device disable control 3 */
 266         u32     devdisr4;       /* Device disable control 4 */
 267         u32     devdisr5;       /* Device disable control 5 */
 268         u32     devdisr6;       /* Device disable control 6 */
 269         u8      res_088[0x94-0x88];
 270         u32     coredisr;       /* Device disable control 7 */
 271 #define FSL_CHASSIS3_DEVDISR2_DPMAC1    0x00000001
 272 #define FSL_CHASSIS3_DEVDISR2_DPMAC2    0x00000002
 273 #define FSL_CHASSIS3_DEVDISR2_DPMAC3    0x00000004
 274 #define FSL_CHASSIS3_DEVDISR2_DPMAC4    0x00000008
 275 #define FSL_CHASSIS3_DEVDISR2_DPMAC5    0x00000010
 276 #define FSL_CHASSIS3_DEVDISR2_DPMAC6    0x00000020
 277 #define FSL_CHASSIS3_DEVDISR2_DPMAC7    0x00000040
 278 #define FSL_CHASSIS3_DEVDISR2_DPMAC8    0x00000080
 279 #define FSL_CHASSIS3_DEVDISR2_DPMAC9    0x00000100
 280 #define FSL_CHASSIS3_DEVDISR2_DPMAC10   0x00000200
 281 #define FSL_CHASSIS3_DEVDISR2_DPMAC11   0x00000400
 282 #define FSL_CHASSIS3_DEVDISR2_DPMAC12   0x00000800
 283 #define FSL_CHASSIS3_DEVDISR2_DPMAC13   0x00001000
 284 #define FSL_CHASSIS3_DEVDISR2_DPMAC14   0x00002000
 285 #define FSL_CHASSIS3_DEVDISR2_DPMAC15   0x00004000
 286 #define FSL_CHASSIS3_DEVDISR2_DPMAC16   0x00008000
 287 #define FSL_CHASSIS3_DEVDISR2_DPMAC17   0x00010000
 288 #define FSL_CHASSIS3_DEVDISR2_DPMAC18   0x00020000
 289 #define FSL_CHASSIS3_DEVDISR2_DPMAC19   0x00040000
 290 #define FSL_CHASSIS3_DEVDISR2_DPMAC20   0x00080000
 291 #define FSL_CHASSIS3_DEVDISR2_DPMAC21   0x00100000
 292 #define FSL_CHASSIS3_DEVDISR2_DPMAC22   0x00200000
 293 #define FSL_CHASSIS3_DEVDISR2_DPMAC23   0x00400000
 294 #define FSL_CHASSIS3_DEVDISR2_DPMAC24   0x00800000
 295         u8      res_098[0xa0-0x98];
 296         u32     pvr;            /* Processor version */
 297         u32     svr;            /* System version */
 298         u8      res_0a8[0x100-0xa8];
 299         u32     rcwsr[30];      /* Reset control word status */
 300
 301 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT   2
 302 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK    0x1f
 303 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT   10
 304 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 305 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT  18
 306 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK   0x3f
 307
 308 #if defined(CONFIG_ARCH_LS2080A)
 309 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
 310 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 311 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
 312 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
 313 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
 314 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
 315 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK   FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
 316 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 317 #define FSL_CHASSIS3_SRDS1_REGSR        29
 318 #define FSL_CHASSIS3_SRDS2_REGSR        29
 319 #elif defined(CONFIG_ARCH_LS1088A)
 320 #define FSL_CHASSIS3_EC1_REGSR  26
 321 #define FSL_CHASSIS3_EC2_REGSR  26
 322 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK     0x00000007
 323 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT    0
 324 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK     0x00000038
 325 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT    3
 326 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK   0xFFFF0000
 327 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT  16
 328 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK   0x0000FFFF
 329 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT  0
 330 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK   FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
 331 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
 332 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK   FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
 333 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT  FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
 334 #define FSL_CHASSIS3_SRDS1_REGSR        29
 335 #define FSL_CHASSIS3_SRDS2_REGSR        30
 336 #endif
 337 #define RCW_SB_EN_REG_INDEX     9
 338 #define RCW_SB_EN_MASK          0x00000400
 339
 340         u8      res_178[0x200-0x178];
 341         u32     scratchrw[16];  /* Scratch Read/Write */
 342         u8      res_240[0x300-0x240];
 343         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 344         u8      res_310[0x400-0x310];
 345         u32     bootlocptrl;    /* Boot location pointer low-order addr */
 346         u32     bootlocptrh;    /* Boot location pointer high-order addr */
 347         u8      res_408[0x520-0x408];
 348         u32     usb1_amqr;
 349         u32     usb2_amqr;
 350         u8      res_528[0x530-0x528];   /* add more registers when needed */
 351         u32     sdmm1_amqr;
 352         u8      res_534[0x550-0x534];   /* add more registers when needed */
 353         u32     sata1_amqr;
 354         u32     sata2_amqr;
 355         u8      res_558[0x570-0x558];   /* add more registers when needed */
 356         u32     misc1_amqr;
 357         u8      res_574[0x590-0x574];   /* add more registers when needed */
 358         u32     spare1_amqr;
 359         u32     spare2_amqr;
 360         u8      res_598[0x620-0x598];   /* add more registers when needed */
 361         u32     gencr[7];       /* General Control Registers */
 362         u8      res_63c[0x640-0x63c];   /* add more registers when needed */
 363         u32     cgensr1;        /* Core General Status Register */
 364         u8      res_644[0x660-0x644];   /* add more registers when needed */
 365         u32     cgencr1;        /* Core General Control Register */
 366         u8      res_664[0x740-0x664];   /* add more registers when needed */
 367         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 368         struct {
 369                 u32     upper;
 370                 u32     lower;
 371         } tp_cluster[4];        /* Core cluster n Topology Register */
 372         u8      res_864[0x920-0x864];   /* add more registers when needed */
 373         u32 ioqoscr[8]; /*I/O Quality of Services Register */
 374         u32 uccr;
 375         u8      res_944[0x960-0x944];   /* add more registers when needed */
 376         u32 ftmcr;
 377         u8      res_964[0x990-0x964];   /* add more registers when needed */
 378         u32 coredisablesr;
 379         u8      res_994[0xa00-0x994];   /* add more registers when needed */
 380         u32 sdbgcr; /*Secure Debug Confifuration Register */
 381         u8      res_a04[0xbf8-0xa04];   /* add more registers when needed */
 382         u32 ipbrr1;
 383         u32 ipbrr2;
 384         u8      res_858[0x1000-0xc00];
 385 };
 386
 387 struct ccsr_clk_cluster_group {
 388         struct {
 389                 u8      res_00[0x10];
 390                 u32     csr;
 391                 u8      res_14[0x20-0x14];
 392         } hwncsr[3];
 393         u8      res_60[0x80-0x60];
 394         struct {
 395                 u32     gsr;
 396                 u8      res_84[0xa0-0x84];
 397         } pllngsr[3];
 398         u8      res_e0[0x100-0xe0];
 399 };
 400
 401 struct ccsr_clk_ctrl {
 402         struct {
 403                 u32 csr;        /* core cluster n clock control status */
 404                 u8  res_04[0x20-0x04];
 405         } clkcncsr[8];
 406 };
 407
 408 struct ccsr_reset {
 409         u32 rstcr;                      /* 0x000 */
 410         u32 rstcrsp;                    /* 0x004 */
 411         u8 res_008[0x10-0x08];          /* 0x008 */
 412         u32 rstrqmr1;                   /* 0x010 */
 413         u32 rstrqmr2;                   /* 0x014 */
 414         u32 rstrqsr1;                   /* 0x018 */
 415         u32 rstrqsr2;                   /* 0x01c */
 416         u32 rstrqwdtmrl;                /* 0x020 */
 417         u32 rstrqwdtmru;                /* 0x024 */
 418         u8 res_028[0x30-0x28];          /* 0x028 */
 419         u32 rstrqwdtsrl;                /* 0x030 */
 420         u32 rstrqwdtsru;                /* 0x034 */
 421         u8 res_038[0x60-0x38];          /* 0x038 */
 422         u32 brrl;                       /* 0x060 */
 423         u32 brru;                       /* 0x064 */
 424         u8 res_068[0x80-0x68];          /* 0x068 */
 425         u32 pirset;                     /* 0x080 */
 426         u32 pirclr;                     /* 0x084 */
 427         u8 res_088[0x90-0x88];          /* 0x088 */
 428         u32 brcorenbr;                  /* 0x090 */
 429         u8 res_094[0x100-0x94];         /* 0x094 */
 430         u32 rcw_reqr;                   /* 0x100 */
 431         u32 rcw_completion;             /* 0x104 */
 432         u8 res_108[0x110-0x108];        /* 0x108 */
 433         u32 pbi_reqr;                   /* 0x110 */
 434         u32 pbi_completion;             /* 0x114 */
 435         u8 res_118[0xa00-0x118];        /* 0x118 */
 436         u32 qmbm_warmrst;               /* 0xa00 */
 437         u32 soc_warmrst;                /* 0xa04 */
 438         u8 res_a08[0xbf8-0xa08];        /* 0xa08 */
 439         u32 ip_rev1;                    /* 0xbf8 */
 440         u32 ip_rev2;                    /* 0xbfc */
 441 };
 442
 443 struct ccsr_serdes {
 444         struct {
 445                 u32     rstctl; /* Reset Control Register */
 446                 u32     pllcr0; /* PLL Control Register 0 */
 447                 u32     pllcr1; /* PLL Control Register 1 */
 448                 u32     pllcr2; /* PLL Control Register 2 */
 449                 u32     pllcr3; /* PLL Control Register 3 */
 450                 u32     pllcr4; /* PLL Control Register 4 */
 451                 u32     pllcr5; /* PLL Control Register 5 */
 452                 u8      res[0x20 - 0x1c];
 453         } bank[2];
 454         u8      res1[0x90 - 0x40];
 455         u32     srdstcalcr;     /* TX Calibration Control */
 456         u32     srdstcalcr1;    /* TX Calibration Control1 */
 457         u8      res2[0xa0 - 0x98];
 458         u32     srdsrcalcr;     /* RX Calibration Control */
 459         u32     srdsrcalcr1;    /* RX Calibration Control1 */
 460         u8      res3[0xb0 - 0xa8];
 461         u32     srdsgr0;        /* General Register 0 */
 462         u8      res4[0x800 - 0xb4];
 463         struct serdes_lane {
 464                 u32     gcr0;   /* General Control Register 0 */
 465                 u32     gcr1;   /* General Control Register 1 */
 466                 u32     gcr2;   /* General Control Register 2 */
 467                 u32     ssc0;   /* Speed Switch Control 0 */
 468                 u32     rec0;   /* Receive Equalization Control 0 */
 469                 u32     rec1;   /* Receive Equalization Control 1 */
 470                 u32     tec0;   /* Transmit Equalization Control 0 */
 471                 u32     ssc1;   /* Speed Switch Control 1 */
 472                 u8      res1[0x840 - 0x820];
 473         } lane[8];
 474         u8 res5[0x19fc - 0xa00];
 475 };
 476
 477 #endif /*__ASSEMBLY__*/
 478 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */